Altera Arria V Avalon-MM User Manual

Arria V Avalon-MM Interface for PCIe Solutions

User Guide

Last updated for Altera Complete Design Suite: 14.1

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Bridge

PCIe Hard IP

Block

PIPE

Interface

PHY IP Core

for PCIe

(PCS/PMA)

Serial Data

Transmission

Application

Layer

(User Logic)

Avalon-MM

Interface

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Datasheet

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Avalon-MM Interface for PCIe Datasheet

Altera® Arria® V FPGAs include a configurable, hardened protocol stack for PCI Express compliant with PCI Express Base Specification 2.1 or 3.0.

The Hard IP for PCI Express PCIe IP core using the Avalon ® Memory-Mapped (Avalon-MM) interface removes some of the complexities associated with the PCIe protocol. For example, it handles all of the Transaction Layer Protocol (TLP) encoding and decoding. Consequently, you can complete your design more quickly. The Avalon-MM interface is implemented as a bridge in FPGA soft logic. It is available in Qsys. The following figure shows the high-level modules and connecting interfaces for this variant.

Figure 1-1: Arria V PCIe Variant with Avalon-MM Interface

that is

Table 1-1: PCI Express Data Throughput

The following table shows the aggregate bandwidth of a PCI Express link for Gen1 and Gen2 for 1, 2, 4, and 8 lanes. The protocol specifies 2.5 giga-transfers per second for Gen1 and 5 giga-transfers per second for Gen2. This table provides bandwidths for a single transmit (TX) or receive (RX) channel. The numbers double for duplex operation. Gen1 and Gen2 use 8B/10B encoding which introduces a 20% overhead.

PCI Express Gen1 (2.5 Gbps)

PCI Express Gen2 (5.0 Gbps)

2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

Link Width in Gigabits Per Second (Gbps)

×1 ×2 ×4 ×8

2 4 8 16

4 8 16

N/A

ISO 9001:2008 Registered

1-2

Features

Refer to the PCI Express High Performance Reference Design for more information about calculating bandwidth for the hard IP implementation of PCI Express in many Altera FPGAs.

Related Information

• PCI Express Base Specification 2.1 or 3.0

• PCI Express High Performance Reference Design

• Creating a System with Qsys

Features

New features in the Quartus® II 14.1 software release:

• Reduced Quartus II compilation warnings by 50%. The Arria V Hard IP for PCI Express with the Avalon-MM interface supports the following features:

• Complete protocol stack including the Transaction, Data Link, and Physical Layers implemented as

• Support for ×1, ×2, ×4, and ×8 configurations with Gen1 and Gen2 lane rates for Root Ports and

• Dedicated 16 KByte receive buffer.

• Optional hard reset controller for Gen2.

• Optional support for Configuration via Protocol (CvP) using the PCIe link allowing the I/O and core

• Qsys example designs demonstrating parameterization, design modules, and connectivity.

• Extended credit allocation settings to better optimize the RX buffer space based on application type.

• Optional end-to-end cyclic redundancy code (ECRC) generation and checking and advanced error

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hard IP.

Endpoints.

bitstreams to be stored separately.

reporting (AER) for high reliability applications. Easy to use:

• Flexible configuration.

• No license requirement.

• Example designs to get started.

Table 1-2: Feature Comparison for all Hard IP for PCI Express IP Cores

The table compares the features of the four Hard IP for PCI Express IP Cores.

Feature Avalon‑ST Interface Avalon‑MM Interface Avalon‑MM DMA

IP Core License Free Free Free

Native Endpoint Supported Supported Supported

Legacy Endpoint

(1)

Not recommended for new designs.

Altera Corporation

(1)

Supported Not Supported Not Supported

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Root port Supported Supported Not Supported

Gen1 ×1, ×2, ×4, ×8 ×1, ×2, ×4, ×8 x8

Gen2 ×1, ×2, ×4 ×1, ×2, ×4 ×4

Features

Feature Avalon‑ST Interface Avalon‑MM Interface Avalon‑MM DMA

1-3

64-bit Application Layer interface

128-bit Application Layer interface

Transaction Layer Packet type (TLP)

Supported Supported Not supported

Supported Supported Supported

• Memory Read Request

• Memory Read RequestLocked

• Memory Write Request

• I/O Read Request

• I/O Write Request

• Configuration Read Request (Root Port)

• Configuration Write Request (Root Port)

• Message Request

• Message Request with Data Payload

• Completion Message

• Completion with Data

• Completion for Locked

• Memory Read Request

• Memory Write Request

• I/O Read Request— Root Port only

• I/O Write Request— Root Port only

• Configuration Read Request (Root Port)

• Configuration Write Request (Root Port)

• Completion Message

• Completion with Data

• Memory Read Request (single dword)

• Memory Write Request (single dword)

• Memory Read Request

• Memory Write Request

• Completion Message

• Completion with Data

Read without Data

Datasheet

Payload size 128–512 bytes 128 or 256 bytes 128 or 256 bytes

Number of tags

32 or 64 16 16 supported for nonposted requests

62.5 MHz clock Supported Supported Not Supported

Multi-function

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Supports up to 8 functions Supports single function

only

Supports single function only

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Features

Feature Avalon‑ST Interface Avalon‑MM Interface Avalon‑MM DMA

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Out-of-order

Not supported Supported Supported completions (transparent to the Application Layer)

Requests that cross 4

Not supported Supported Supported KByte address boundary (transparent to the Application Layer)

Polarity Inversion of

Supported Supported Supported PIPE interface signals

ECRC forwarding on

Supported Not supported Not supported RX and TX

Number of MSI

1, 2, 4, 8, or 16 1, 2, 4, 8, or 16 1, 2, 4, 8, or 16 requests

MSI-X Supported Supported Supported

Legacy interrupts Supported Supported Supported

Expansion ROM Supported Not supported Not supported

The purpose of the Arria VAvalon-MM Interface for PCIe Solutions User Guide is to explain how to use this IP core and not to explain the PCI Express protocol. Although there is inevitable overlap between these two purposes, this document should be used in conjunction with an understanding of the PCI Express Base Specification.

Note:

This release provides separate user guides for the different variants. The Related Information provides links to all versions.

Related Information

• V-Series Avalon-MM DMA Interface for PCIe Solutions User Guide

• Arria V Avalon-MM Interface for PCIe Solutions User Guide

• Arria V Avalon-ST Interface for PCIe Solutions User Guide

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Release Information

Table 1-3: Hard IP for PCI Express Release Information

Item Description

Version 14.1

Release Date December 2014

Ordering Codes No ordering code is required

Product IDs There are no encrypted files for the Arria V Hard IP

Vendor ID

Device Family Support

Release Information

for PCI Express. The Product ID and Vendor ID are not required because this IP core does not require a license.

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Table 1-4: Device Family Support

Device Family Support

Arria V Final. The IP core is verified with final timing

models. The IP core meets all functional and timing requirements for the device family and can be used in production designs.

Other device families Refer to the Related Information below for other

device families:

Related Information

• Arria V GZ Avalon-MM Interface for PCIe Solutions User Guide

• Arria V GZ Avalon-ST Interface for PCIe Solutions User Guide

• Arria 10 Avalon-MM Interface for PCIe Solutions User Guide

• Arria 10 Avalon-MM DMA Interface for PCIe Solutions User Guide

• Arria 10 Avalon-ST Interface for PCIe Solutions User Guide

• Cyclone V Avalon-MM Interface for PCIe Solutions User Guide

• Cyclone V Avalon-ST Interface for PCIe Solutions User Guide

• IP Compiler for PCI Express User Guide

• Stratix V Avalon-MM Interface for PCIe Solutions User Guide

• Stratix V Avalon-ST Interface for PCIe Solutions User Guide

• Stratix V Avalon-ST Interface with SR-IOV for PCIe Solutions User Guide

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Altera FPGA

User Application

Logic

PCIe

Hard IP

PCIe

Hard IP

User Application

Logic

PCI Express Link

Altera FPGA

1-6

Configurations

The Avalon-MM Arria V Hard IP for PCI Express includes a full hard IP implementation of the PCI Express stack comprising the following layers:

• Physical (PHY), including:

• Physical Media Attachment (PMA)

• Physical Coding Sublayer (PCS)

• Media Access Control (MAC)

• Data Link Layer (DL)

• Transaction Layer (TL) When configured as an Endpoint, the Arria V Hard IP for PCI Express using the Avalon-MM supports

memory read and write requests and completions with or without data.

Figure 1-2: PCI Express Application with a Single Root Port and Endpoint

The following figure shows a PCI Express link between two Arria V FPGAs. One is configured as a Root Port and the other as an Endpoint.

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Figure 1-3: PCI Express Application Using Configuration via Protocol

The Arria V design below includes the following components:

• A Root Port that connects directly to a second FPGA that includes an Endpoint.

• Two Endpoints that connect to a PCIe switch.

• A host CPU that implements CvP using the PCI Express link connects through the switch. For more information about configuration over a PCI Express link below.

Datasheet

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PCIe Link

PCIe Hard IP

Switch

PCIe

Hard IP

User Application

Logic

PCIe Hard IP

PCIe Link

User Application

Logic

Altera FPGA with Hard IP for PCI Express

Active Serial or

Active Quad

Device Configuration

Configuration via Protocol (CvP)

using the PCI Express Link

Serial or

Quad Flash

USB

Download

cable

PCIe

Hard IP

User

Application

Logic

Altera FPGA with Hard IP for PCI Express

Config Control

CvP

USB

Host CPU

PCIe

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Example Designs

1-7

Related Information

Configuration via Protocol (CvP)Implementation in Altera FPGAs User Guide

Example Designs

The following example designs are available for the Avalon-MM Arria V Hard IP for PCI Express IP Core. You can download them from the <install_dir>/ip/altera/altera_pcie/altera_pcie_<dev>__hip_avmm/

example_designs directory:

• ep_g1x1.qsys

• ep_g1x4.qsys

• ep_g1x8.qsys

• ep_g2x1.qsys

• ep_g2x4.qsys

Click on the link below to get started with the example design provided in this user guide.

Related Information

Getting Started with the Avalon-MM Arria V Hard IP for PCI Express on page 2-1

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Debug Features

Debug features allow observation and control of the Hard IP for faster debugging of system-level problems.

Related Information

Debugging on page 13-1

IP Core Verification

To ensure compliance with the PCI Express specification, Altera performs extensive verification. The simulation environment uses multiple testbenches that consist of industry-standard bus functional models (BFMs) driving the PCI Express link interface. Altera performs the following tests in the simulation environment:

• Directed and pseudorandom stimuli are applied to test the Application Layer interface, Configuration Space, and all types and sizes of TLPs

• Error injection tests that inject errors in the link, TLPs, and Data Link Layer Packets (DLLPs), and check for the proper responses

• PCI-SIG® Compliance Checklist tests that specifically test the items in the checklist

• Random tests that test a wide range of traffic patterns

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Altera provides the following two example designs that you can leverage to test your PCBs and complete compliance base board testing (CBB testing) at PCI-SIG.

Related Information

• PCI SIG Gen3 x8 Merged Design - Stratix V

• PCI SIG Gen2 x8 Merged Design - Stratix V

Compatibility Testing Environment

Altera has performed significant hardware testing to ensure a reliable solution. In addition, Altera internally tests every release with motherboards and PCI Express switches from a variety of manufac‐ turers. All PCI-SIG compliance tests are run with each IP core release.

Performance and Resource Utilization

Because the PCIe protocol stack is implemented in hardened logic, it uses less than 1% of device resources.

The Avalon-MM bridge is implemented in soft logic and functions as a front end to the hardened protocol stack. The following table shows the typical device resource utilization for selected configura‐ tions using the current version of the Quartus II software. With the exception of M10K memory blocks, the numbers of ALMs and logic registers in the following tables are rounded up to the nearest 50.

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Table 1-5: Performance and Resource Utilization Avalon-MM Hard IP for PCI Express

Recommended Speed Grades

1-9

Data Rate or Interface

Width

ALMs Memory M10K Logic Registers

Avalon-MM Bridge

Gen1 ×4 1250 27 1700

Gen2 ×8 2100 35 3050

Avalon-MM Interface–Completer Only

64 600 11 900

128 1350 22 2300

Avalon-MM–Completer Only Single DWord

64 160 0 230

Note: Soft calibration of the transceiver module requires additional logic. The amount of logic required

depends on the configuration.

Related Information

Fitter Resources Reports

Recommended Speed Grades

Table 1-6: Arria V Recommended Speed Grades for Link Widths and Application Layer Clock Frequencies

Altera recommends setting the Quartus II Analysis & Synthesis Settings Optimization Technique to Speed when the Application Layer clock frequency is 250 MHz. For information about optimizing synthesis, refer to Setting Up and Running Analysis and Synthesis in Quartus II Help. For more information about how to effect the

Optimization Technique settings, refer to Area and Timing Optimization in volume 2 of the Quartus II Handbook. .

Link Rate Link Width Interface

Width

×1 64 bits 62.5

×2 64 bits 125 –4,–5,–6

Gen1

×4 64 bits 125 –4,–5,–6

×8 128 bits 125 –4,–5,–6

(2)

This is a power-saving mode of operation

Application Clock

Frequency (MHz)

(2)

,125 –4,–5,–6

Recommended Speed Grades

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Steps in Creating a Design for PCI Express

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Link Rate Link Width Interface

Width

×1 64 bits

Gen2

×2 64 bits 125 –4,–5

Application Clock

Frequency (MHz)

125

×4 128 bits 125 –4,–5

Related Information

• Area and Timing Optimization

• Altera Software Installation and Licensing Manual

• Setting up and Running Analysis and Synthesis

Steps in Creating a Design for PCI Express

Before you begin

Select the PCIe variant that best meets your design requirements.

• Is your design an Endpoint or Root Port?

• What Generation do you intend to implement?

• What link width do you intend to implement?

• What bandwidth does your application require?

• Does your design require CvP?

Recommended Speed Grades

–4,–5

1. Select parameters for that variant.

2. Simulate using an Altera-provided example design. All of Altera's PCI Express example designs are

available under <install_dir>/ip/altera/altera_pcie/. Alternatively, create a simulation model and use your own custom or third-party BFM. The Qsys Generate menu generates simulation models. Altera supports ModelSim-Altera for all IP. The PCIe cores support the Aldec RivieraPro, Cadence NCsim, Mentor Graphics ModelSim, and Synopsys VCS and VCS-MX simulators.

3. Compile your design using the Quartus II software. If the versions of your design and the Quartus II software you are running do not match, regenerate your PCIe design.

4. Download your design to an Altera development board or your own PCB. Click on the All Develop‐ ment Kits link below for a list of Altera's development boards.

5. Test the hardware. You can use Altera's SignalTap® II Logic Analyzer or a third-party protocol analyzer to observe behavior.

6. Substitute your Application Layer logic for the Application Layer logic in Altera's testbench. Then repeat Steps 3–6. In Altera's testbenches, the PCIe core is typically called the DUT (device under test). The Application Layer logic is typically called APPS.

Related Information

• Parameter Settings on page 3-1

• Getting Started with the Avalon-MM Arria V Hard IP for PCI Express

• All Development Kits

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Getting Started with the Avalon‑MM Arria V

Transaction,

Data Link,

and PHY

Layers

O n-C hip

Memory

DMA

Qsys System Design for PCI Express

PCI Express

Link

PCI

Express

Avalon-MM

Bridge

Interconnect

Avalon-MM Hard IP for PCI Express

Transceiver

Reconfiguration

Controller

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You can download a design example for the Avalon-MM Arria V Hard IP for PCI Express from the

<install_dir>/ip/altera/altera_pcie/altera_pcie-<dev>_hip_avmm/example_designs directory. This walkthrough

uses the a Gen1 x4 Endpoint, ep_g1x4.qsys. The design examples contain the following components:

• Avalon-MM Arria V Hard IP for PCI Express IP core

• On-Chip memory

• DMA controller

• Transceiver Reconfiguration Controller

• Two Avalon-MM pipeline bridges

Figure 2-1: Qsys Generated Endpoint

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ISO 9001:2008 Registered

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Running Qsys

The design example transfers data between an on-chip memory buffer located on the Avalon-MM side and a PCI Express memory buffer located on the root complex side. The data transfer uses the DMA component which is programmed by the PCI Express software application running on the Root Complex processor.

The example design also includes the Transceiver Reconfiguration Controller which allows you to dynamically reconfigure transceiver settings. This component is necessary for high performance transceiver designs.

Related Information

• Generating the Example Design on page 2-3

• Creating a System with Qsys

This document provides an introduction to Qsys.

Running Qsys

1. Choose Programs > Altera > Quartus II><version_number> (Windows Start menu) to run the

Quartus II software. Alternatively, you can also use the Quartus II Web Edition software.

2. On the File menu, select New, then Qsys System File.

3. Open the ep_g1x4.qsys example design.

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The following figure shows a Qsys system that includes the Transceiver Reconfiguration Controller and the Altera PCIe Reconfig Driver IP Cores. The Transceiver Reconfiguration Controller performs dynamic reconfiguration of the analog transceiver settings to optimize signal quality. You must include these components to the Qsys system to run successfully in hardware.

Figure 2-2: Qsys Avalon-MM Design for PCIe with Transceiver Reconfiguration Components

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Refer to Creating a System with Qsys in volume 1 of the Quartus II Handbook for more information about how to use Qsys. For an explanation of each Qsys menu item, refer to About Qsys in Quartus II Help.

Related Information

• Creating a System with Qsys

• About Qsys

Generating the Example Design

1. On the Generate menu, select Generate Testbench System. The Generation dialog box appears.

2. Under Testbench System, set the following options: a. For Create testbench Qsys system, select Standard, BFMs for standard Qsys interfaces.

b. For Create testbench simulation model, select Verilog.

3. You can retain the default values for all other parameters.

4. Click Generate.

5. After Qsys reports Generation Completed, click Close.

6. On the File menu, click Save.

The following table lists the testbench and simulation directories Qsys generates.

Generating the Example Design

2-3

Table 2-1: Qsys System Generated Directories

Directory Location

Qsys system

Testbench

Simulation Model

The design example simulation includes the following components and software:

• The Qsys system

• A testbench. You can view this testbench in Qsys by opening <project_dir>/ep_g2x4/testbench/ep_g1x4_

tb.qsys.

• The ModelSim software

Note:

You can also use any other supported third-party simulator to simulate your design.

Complete the following steps to run the Qsys testbench:

1. In a terminal window, change to the <project_dir>/ep_g1x4/testbench/mentor directory.

2. Start the ModelSim® simulator.

3. Type the following commands in a terminal window:

<project_dir>/ep_g1x4

<project_dir>/ep_g1x4/testbench/<cad_vendor>

<project_dir>/ep_g1x4/testbench/ep_g2x4_tb/

simulation/

a. do msim_setup.tcl b. ld_debug c. run 140000 ns

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Running A Gate-Level Simulation

The driver performs the following transactions with status of the transactions displayed in the ModelSim simulation message window:

1. Various configuration accesses to the Avalon-MM Arria V Hard IP for PCI Express in your system after the link is initialized

2. Setup of the Address Translation Table for requests that are coming from the DMA component

3. Setup of the DMA controller to read 512 Bytes of data from the Transaction Layer Direct BFM shared

memory

4. Setup of the DMA controller to write the same data back to the Transaction Layer Direct BFM shared memory

5. Data comparison and report of any mismatch

Related Information

Simulating Altera Designs

Running A Gate-Level Simulation

The PCI Express testbenches run simulations at the register transfer level (RTL). However, it is possible to create you own gate-level simulations. Contact your Altera Sales Representative for instructions and an example that illustrate how to create a gate-level simulation from the RTL testbench.

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Simulating the Single DWord Design

You can use the same testbench to simulate the Completer-Only Single Dword IP core by changing the settings in the driver file.

1. In a terminal window, change to the <project_dir>/<variant>/testbench/<variant>_tb/simulation/submodules directory.

2. Open altpcietb_bfm_driver_avmm.v in your text editor.

3. To enable target memory tests and specify the completer-only single dword variant, specify the

following parameters:

a. parameter RUN_TGT_MEM_TST = 1; b. parameter RUN_DMA_MEM_TST = 0; c. parameter AVALON_MM_LITE = 1;

4. Change to the <project_dir>/variant/testbench/mentor directory.

5. Start the ModelSim simulator.

6. To run the simulation, type the following commands in a terminal window: a. do msim_setup.tcl

b. ld_debug (The debug suffix stops optimizations, improving visibility in the ModelSim waveforms.) c. run 140000 ns

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Understanding Channel Placement Guidelines

Arria V transceivers are organized in banks. The transceiver bank boundaries are important for clocking resources, bonding channels, and fitting. Refer to the channel placement figures following Serial Interface Signals for illustrations of channel placement.

Generating Quartus II Synthesis Files

1. On the Generate menu, select Generate HDL.

2. For Create HDL design files for synthesis, select Verilog.

You can leave the default settings for all other items.

3. Click Generate to generate files for Quartus II synthesis.

4. Click Finish when the generation completes.

Compiling the Design in the Quartus II Software

To compile the Qsys design example in the Quartus II software, you must create a Quartus II project and add your Qsys files to that project.

Understanding Channel Placement Guidelines

2-5

Complete the following steps to create your Quartus II project:

1. Click the New Project Wizard icon.

2. Click Next in the New Project Wizard: Introduction (The introduction does not appear if you

previously turned it off)

3. On the Directory, Name, Top-Level Entity page, enter the following information: a. The working directory shown is correct. You do not have to change it.

b. For the project name, browse to the synthesis directory that includes your Qsys project,

<working_dir>/ep_g1x4/synthesis. Select your variant name, ep_g1x4.v. Then, click Open.

c. If the top-level design entity and Qsys system names are identical, the Quartus II software treats the

Qsys system as the top-level design entity.

4. Click Next to display the Add Files page.

5. Complete the following steps to add the Quartus II IP File (.qip)to the project: a. Click the browse button. The Select File dialog box appears.

b. In the Files of type list, select IP Variation Files (*.qip). c. Browse to the <working_dir>/ep_g1x4/synthesis directory. d. Click ep_g1x4.qip and then click Open. e. On the Add Files page, click Add, then click OK.

6. Click Next to display the Device page.

7. On the Family & Device Settings page, choose the following target device family and options: a. In the Family list, select Arria V (GT/GX/ST/SX).

b. In the Devices list, select Arria V GX Extended Features.. c. In the Available Devices list, select 5AGXFB3H6F35C6.

8. Click Next to close this page and display the EDA Tool Settings page.

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Compiling the Design in the Quartus II Software

9. From the Simulation list, select ModelSim®. From the Format list, select the HDL language you intend to use for simulation.

10.Click Next to display the Summary page.

11.Check the Summary page to ensure that you have entered all the information correctly.

12.Click Finish to create the Quartus II project.

13.Add the Synopsys Design Constraint (SDC) commands shown in the following example to the

top-level design file for your Quartus II project.

14.To compile your design using the Quartus II software, on the Processing menu, click Start Compila‐ tion. The Quartus II software then performs all the steps necessary to compile your design.

15.After compilation, expand the TimeQuest Timing Analyzer folder in the Compilation Report. Note

whether the timing constraints are achieved in the Compilation Report.

16.If your design does not initially meet the timing constraints, you can find the optimal Fitter settings for your design by using the Design Space Explorer. To use the Design Space Explorer, click Launch Design Space Explorer on the tools menu.

Example 2-1: Synopsys Design Constraints

create_clock -period “100 MHz” -name {refclk_pci_express}{*refclk_*} derive_pll_clocks derive_clock_uncertainty

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# PHY IP reconfig controller constraints # Set reconfig_xcvr clock # Modify to match the actual clock pin name # used for this clock, and also changed to have the correct period set create_clock -period "125 MHz" -name {reconfig_xcvr_clk}{*reconfig_xcvr_clk*}

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Notes:

1. If supported and enabled for your IP variation

2. If functional simulation models are generated

<your_ip>_bb.v - Verilog HDL black box EDA synthesis file <your_ip>_inst.v or .vhd - Sample instantiation template

synthesis - IP synthesis files

<your_ip>.qip - Lists files for synthesis

testbench - Simulation testbench files

<testbench_hdl_files>

<simulator_vendor> - Testbench for supported simulators

<simulation_testbench_files>

<your_ip>.v or .vhd - Top-level IP variation synthesis file

simulation - IP simulation files

<your_ip>.sip - NativeLink simulation integration file

<simulator vendor> - Simulator setup scripts

<simulator_setup_scripts>

<your_ip> - IP core variation files

<your_ip>.qip or .qsys - System or IP integration file

<your_ip>_generation.rpt - IP generation report <your_ip>.bsf - Block symbol schematic file

<your_ip>.ppf - XML I/O pin information file <your_ip>.spd - Combines individual simulation startup scripts

<your_ip>.html - Contains memory map

<your_ip>.sopcinfo - Software tool-chain integration file

<your_ip>_syn.v or .vhd - Timing & resource estimation netlist

<your_ip>.debuginfo - Lists files for synthesis

<your_ip>.v, .vhd, .vo, .vho - HDL or IPFS models

<your_ip>_tb - Testbench for supported simulators

<your_ip>_tb.v or .vhd - Top-level HDL testbench file

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Files Generated for Altera IP Cores Figure 2-3: IP Core Generated Files

The Quartus II software generates the following output for your IP core.

Programming a Device

2-7

Programming a Device

After you compile your design, you can program your targeted Altera device and verify your design in hardware.

For more information about programming Altera FPGAs, refer to Quartus II Programmer.

Getting Started with the Avalon‑MM Arria V Hard IP for PCI Express

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Programming a Device

Related Information

Quartus II Programmer

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Getting Started with the Avalon‑MM Arria V Hard IP for PCI Express

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Parameter Settings

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Avalon-MM System Settings

Table 3-1: System Settings for PCI Express

Parameter Value Description

Number of Lanes ×1, ×2, ×4, ×8 Specifies the maximum number of lanes supported.

Lane Rate Gen1 (2.5 Gbps)

Gen2 (2.5/5.0 Gbps)

Port type Root Port

Native Endpoint

Specifies the maximum data rate at which the link can operate.

Specifies the port type. Altera recommends Native Endpoint for all new Endpoint designs. The Legacy Endpoint is not available for the Avalon-MM Arria V Hard IP for PCI Express.

The Endpoint stores parameters in the Type 0 Configuration Space. The Root Port stores parameters in the Type 1 Configu‐ ration Space.

RX Buffer credit allocation performance for received requests

Minimum

Low

Balanced

Determines the allocation of posted header credits, posted data credits, non-posted header credits, completion header credits, and completion data credits in the 16 KByte RX buffer. The 5 settings allow you to adjust the credit allocation to optimize your system. The credit allocation for the selected setting displays in the message pane.

Refer to the Throughput Optimization chapter for more information about optimizing performance. The Flow Control chapter explains how the RX credit allocation and the

Maximum payload RX Buffer credit allocation and the Maximum payload size that you choose affect the allocation of flow control credits. You can set the Maximum payload size parameter on the Device tab.

ISO 9001:2008 Registered

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Avalon-MM System Settings

Parameter Value Description

The Message window of the GUI dynamically updates the number of credits for Posted, Non-Posted Headers and Data, and Completion Headers and Data as you change this selection.

• Minimum RX Buffer credit allocation -performance for received requests )–This setting configures the minimum PCIe specification allowed for non-posted and posted request credits, leaving most of the RX Buffer space for received completion header and data. Select this option for variations where application logic generates many read requests and only infrequently receives single requests from the PCIe link.

• Low–This setting configures a slightly larger amount of RX Buffer space for non-posted and posted request credits, but still dedicates most of the space for received completion header and data. Select this option for variations where application logic generates many read requests and infrequently receives small bursts of requests from the PCIe link. This option is recommended for typical endpoint applications where most of the PCIe traffic is generated by a DMA engine that is located in the endpoint application layer logic.

• Balanced–This setting allocates approximately half the RX Buffer space to received requests and the other half of the RX Buffer space to received completions. Select this option for variations where the received requests and received completions are roughly equal.

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Reference clock frequency

Use 62.5 MHz application clock

Enable configu‐ ration via PCIe link

Related Information

PCI Express Base Specification 2.1 or 3.0

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100 MHz 125 MHz

The PCI Express Base Specification requires a 100 MHz ±300 ppm reference clock. The 125 MHz reference clock is provided as a convenience for systems that include a 125 MHz clock source.

On/Off This mode is only available only for Gen1 ×1.

On/Off When On, the Quartus II software places the Endpoint in the

location required for configuration via protocol (CvP). For more information about CvP, click the Configuration via Protocol (CvP) link below. CvP is not supported for Gen3 variants.

Parameter Settings

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Base Address Register (BAR) Settings

You can configure up to six 32-bit BARs or three 64-bit BARs.

Table 3-2: BAR Registers

Parameter Value Description

Base Address Register (BAR) Settings

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Type

Disabled

Defining memory as prefetchable allows data in the region to be fetched ahead anticipating that the

64-bit prefetchable memory

32-bit non-prefetchable memory

requestor may require more data from the same region than was originally requested. If you specify that a memory is prefetchable, it must have the

32-bit prefetchable memory

I/O address space

following 2 attributes:

• Reads do not have side effects

• Write merging is allowed The 32-bit prefetchable memory and I/O address

space BARs are only available for the Legacy Endpoint.

Size

Not configurable

Specifies the memory size calculated from other parameters you enter.

Table 3-3: Device ID Registers

The following table lists the default values of the read-only Device ID registers. You can use the parameter editor to change the values of these registers. Refer to Type 0 Configuration Space Registers for the layout of the Device Identification registers.

Vendor ID 16 bits 0x00000000 Sets the read-only value of the Vendor ID register. This

parameter cannot be set to 0xFFFF, per the PCI Express Specification.

Address offset: 0x000.

Device ID 16 bits 0x00000001 Sets the read-only value of the Device ID register. This

Address offset: 0x000.

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Device Capabilities

Revision ID 8 bits 0x00000001 Sets the read-only value of the Revision ID register.

Address offset: 0x008.

Class code 24 bits 0x00000000 Sets the read-only value of the Class Code register.

Address offset: 0x008.

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Subsystem Vendor ID

16 bits 0x00000000 Sets the read-only value of the Subsystem Vendor ID

register in the PCI Type 0 Configuration Space. This parameter cannot be set to 0xFFFF per the PCI Express Base Specification. This value is assigned by PCI-SIG to the device manufacturer. This register is only valid in the Type 0 (Endpoint) Configuration Space.

Address offset: 0x02C.

Subsystem Device ID

16 bits 0x00000000 Sets the read-only value of the Subsystem Device ID

Related Information

PCI Express Base Specification 2.1 or 3.0

Device Capabilities

Table 3-4: Capabilities Registers

Parameter Possible Values Default Value Description

Maximum payload size

Completion timeout range

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128 bytes 256 bytes

ABCD

BCD ABC

None

128 bytes Specifies the maximum payload size supported. This

parameter sets the read-only value of the max payload size supported field of the Device Capabilities register (0x084[2:0]). Address: 0x084.

ABCD Indicates device function support for the optional

completion timeout programmability mechanism. This mechanism allows system software to modify the completion timeout value. This field is applicable only to Root Ports and Endpoints that issue requests on their own behalf. Completion timeouts are specified and enabled in the Device Control 2 register (0x0A8) of the PCI Express Capability Structure Version. For all other

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Parameter Possible Values Default Value Description

Error Reporting

functions this field is reserved and must be hardwired to 0x0000b. Four time value ranges are defined:

• Range A: 50 us to 10 ms

• Range B: 10 ms to 250 ms

• Range C: 250 ms to 4 s

• Range D: 4 s to 64 s Bits are set to show timeout value ranges supported. The

function must implement a timeout value in the range 50 s to 50 ms. The following values specify the range:

• None – Completion timeout programming is not supported

• 0001 Range A

• 0010 Range B

• 0011 Ranges A and B

• 0110 Ranges B and C

• 0111 Ranges A, B, and C

• 1110 Ranges B, C and D

• 1111 Ranges A, B, C, and D

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All other values are reserved. Altera recommends that the completion timeout mechanism expire in no less than 10 ms.

Implement completion timeout disable

On/Off On For Endpoints using PCI Express version 2.1 or 3.0, this

option must be On. The timeout range is selectable. When On, the core supports the completion timeout disable mechanism via the PCI Express Device

Control Register 2. The Application Layer logic must

implement the actual completion timeout mechanism for the required ranges.

Error Reporting

Table 3-5: Error Reporting

Parameter Value Default Value Description

Advanced error reporting (AER)

On/Off Off When On, enables the Advanced Error Reporting (AER)

capability.

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Link Capabilities

Parameter Value Default Value Description

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ECRC checking

On/Off Off When On, enables ECRC checking. Sets the read-only

value of the ECRC check capable bit in the Advanced

Error Capabilities and Control Register. This

parameter requires you to enable the AER capability.

ECRC generation

On/Off Off When On, enables ECRC generation capability. Sets the

read-only value of the ECRC generation capable bit in the Advanced Error Capabilities and Control

AER capability. Not applicable for Avalon-MM DMA.

Link Capabilities

Table 3-6: Link Capabilities

Parameter Value Description

Link port number

0x01 Sets the read-only value of the port number field in the Link

Capabilities Register.

Slot clock configuration

On/Off When On, indicates that the Endpoint or Root Port uses the

same physical reference clock that the system provides on the connector. When Off, the IP core uses an independent clock regardless of the presence of a reference clock on the connector.

MSI and MSI-X Capabilities

Table 3-7: MSI and MSI-X Capabilities

Parameter Value Description

MSI messages requested

Implement MSI-X On/Off When On, enables the MSI-X functionality.

1, 2, 4, 8, 16 Specifies the number of messages the Application Layer can

request. Sets the value of the Multiple Message Capable field of the Message Control register, 0x050[31:16].

MSI-X Capabilities

Bit Range

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Table size [10:0] System software reads this field to determine the MSI-X Table

Table Offset [31:0] Points to the base of the MSI-X Table. The lower 3 bits of the

MSI and MSI-X Capabilities

Parameter Value Description

size <n>, which is encoded as <n–1>. For example, a returned value of 2047 indicates a table size of 2048. This field is readonly. Legal range is 0–2047 (211).

Address offset: 0x068[26:16]

table BAR indicator (BIR) are set to zero by software to form a 32-bit qword-aligned offset. This field is read-only.

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Table BAR Indicator

Pending Bit Array (PBA) Offset

PBA BAR Indicator

[2:0] Specifies which one of a function’s BARs, located beginning at

0x10 in Configuration Space, is used to map the MSI-X table into memory space. This field is read-only. Legal range is 0–5.

[31:0] Used as an offset from the address contained in one of the

function’s Base Address registers to point to the base of the MSI-X PBA. The lower 3 bits of the PBA BIR are set to zero by software to form a 32-bit qword-aligned offset. This field is read-only.

[2:0] Specifies the function Base Address registers, located

beginning at 0x10 in Configuration Space, that maps the MSIX PBA into memory space. This field is read-only. Legal range is 0–5.

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Power Management

Table 3-8: Power Management Parameters

Parameter Value Description

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Endpoint L0s acceptable latency

Endpoint L1 acceptable latency

Maximum of 64 ns Maximum of 128 ns Maximum of 256 ns Maximum of 512 ns Maximum of 1 us Maximum of 2 us Maximum of 4 us No limit

Maximum of 1 us Maximum of 2 us Maximum of 4 us Maximum of 8 us Maximum of 16 us Maximum of 32 us No limit

This design parameter specifies the maximum acceptable latency that the device can tolerate to exit the L0s state for any links between the device and the root complex. It sets the read-only value of the Endpoint L0s acceptable latency field of the Device Capabilities Register (0x084).

This Endpoint does not support the L0s or L1 states. However, in a switched system there may be links connected to switches that have L0s and L1 enabled. This parameter is set to allow system configuration software to read the acceptable latencies for all devices in the system and the exit latencies for each link to determine which links can enable Active State Power Management (ASPM). This setting is disabled for Root Ports.

The default value of this parameter is 64 ns. This is the safest setting for most designs.

This value indicates the acceptable latency that an Endpoint can withstand in the transition from the L1 to L0 state. It is an indirect measure of the Endpoint’s internal buffering. It sets the read-only value of the Endpoint L1 acceptable latency field of the Device Capabilities Register.

This Endpoint does not support the L0s or L1 states. However, a switched system may include links connected to switches that have L0s and L1 enabled. This parameter is set to allow system configuration software to read the acceptable latencies for all devices in the system and the exit latencies for each link to determine which links can enable Active State Power Management (ASPM). This setting is disabled for Root Ports.

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The default value of this parameter is 1 µs. This is the safest setting for most designs.

Parameter Settings

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Avalon Memory‑Mapped System Settings

Table 3-9: Avalon Memory-Mapped System Settings

Parameter Value Description

Avalon Memory‑Mapped System Settings

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Avalon-MM data width

Avalon-MM address width

Peripheral mode

64-bit

128-bit

32-bit 64-bit

Requester/ Completer

Completer-Only

Specifies the data width for the Application Layer to Transaction Layer interface. Refer to Application

Layer Clock Frequencies for All Combinations of Link Width, Data Rate and Application Layer Interface Widths for all legal combinations of data width,

number of lanes, Application Layer clock frequency, and data rate.

Specifies the address width for Avalon-MM RX master ports that access Avalon-MM slaves in the Avalon address domain. When you select 32-bit addresses, the PCI Express Avalon-MM Bridge performs address translation. When you specify 64bits addresses, no address translation is performed in either direction. The destination address specified is forwarded to the Avalon-MM interface without any changes.

For the Avalon-MM interface with DMA, this value must be set to 64.

Specifies whether the Avalon-MM Arria V Hard IP for PCI Express is capable of sending requests to the upstream PCI Express devices, and whether the incoming requests are pipelined.

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Requester/Completer—In this mode, the Hard IP can send request packets on the PCI Express TX link and receive request packets on the PCI Express RX link.

Completer-Only—In this mode, the Hard IP can receive requests, but cannot initiate upstream requests. However, it can transmit completion packets on the PCI Express TX link. This mode removes the Avalon-MM TX slave port and thereby reduces logic utilization.

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Avalon Memory‑Mapped System Settings

Parameter Value Description

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Single DW Completer On/Off

Control register access

On/Off (CRA) Avalon-MM slave port

Enable multiple MSI/MSI-X

On/Off support

This is a non-pipelined version of Completer Only mode. At any time, only a single request can be outstanding. Single dword completer uses fewer resources than Completer Only. This variant is targeted for systems that require simple read and write register accesses from a host CPU. If you select this option, the width of the data for RXM BAR masters is always 32 bits, regardless of the Avalon- MM width.

For the Avalon-MM interface with DMA, this value must be Off .

Allows read and write access to bridge registers from the interconnect fabric using a specialized slave port. This option is required for Requester/Completer variants and optional for Completer Only variants. Enabling this option allows read and write access to bridge registers, except in the Completer-Only single dword variations.

When you turn this option On, the core exports top-level MSI and MSI-X interfaces that you can use to implement a Customer Interrupt Handler for MSI and MSI-X interrupts. For more information about the Custom Interrupt Handler, refer to Interrupts for

End Points Using the Avalon-MM Interface with

Multiple MSI/MSI

X Support. If you turn this option

Off, the core handles interrupts internally.

Auto enabled PCIe interrupt (enabled at power-on)

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On/Off

Turning on this option enables the Avalon-MM Arria V Hard IP for PCI Express interrupt register at power-up. Turning off this option disables the interrupt register at power-up. The setting does not affect run-time configuration of the interrupt enable register.

For the Avalon-MM interface with DMA, this value must be Off.

Parameter Settings

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Enable hard IP status bus On/Off When you turn this option on, your top-level variant

Avalon Memory‑Mapped System Settings

Parameter Value Description

includes the signals necessary to connect to the Transceiver Reconfiguration Controller IP Core, your variant, including:

• Link status signals

• ECC error signals

• TX and RX parity error signals

• Completion header and data signals, indicating the total number of Completion TLPs currently stored in the RX buffer

Altera recommends that you include the Transceiver Reconfiguration Controller IP Core in your design to improve signal quality.

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Enable hard IP status

On/Off When you turn this option on, your top-level variant

extension bus

Avalon to PCIe Address Translation Settings

Number of address pages 1, 2, 4, 8, 16, 32,

64, 128, 256, 512

includes signals that are useful for debugging, including link training and status, error, and the Transaction Layer Configuration Space signals. The top-level variant also includes signals showing the start and end of packets, error, ready, and BAR signals for the native Avalon-ST interface that connects to the Transaction Layer. The following signals are included in the top-level variant:

• Link status signals

• ECC error signals

• Transaction Layer Configuration Space signals

• Avalon-ST packet, error, ready, and BAR signals

Specifies the number of pages required to translate Avalon-MM addresses to PCI Express addresses before a request packet is sent to the Transaction Layer. Each of the 512 possible entries corresponds to a base address of the PCI Express memory segment of a specific size. This parameter is only necessary when you select 32-bit addressing.

Size of address pages 4 KBytes–4

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GBytes

Specifies the size of each memory segment. Each memory segment must be the same size. Refer to

Avalon-MM-to-PCI Express Address Translation Algorithm for 32-Bit Bridge for more information

about address translation. This parameter is only necessary when you select 32-bit addressing.

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+ 136 hidden pages

Altera Arria V Avalon-MM User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Datasheet

Avalon-MM Interface for PCIe Datasheet

Features

Release Information

Device Family Support

Configurations

Example Designs

Debug Features

IP Core Verification

Compatibility Testing Environment

Performance and Resource Utilization

Recommended Speed Grades

Steps in Creating a Design for PCI Express

Running Qsys

Generating the Example Design

Running A Gate-Level Simulation

Simulating the Single DWord Design

Understanding Channel Placement Guidelines

Generating Quartus II Synthesis Files

Compiling the Design in the Quartus II Software

Programming a Device

Parameter Settings

Avalon-MM System Settings

Base Address Register (BAR) Settings

Device Capabilities

Error Reporting

Link Capabilities

MSI and MSI-X Capabilities

Power Management

Avalon Memory‑Mapped System Settings