This document describes the hardware features of the Arria® II GX FPGA
development board, 6G Edition, including the detailed pin-out and component
reference information required to create custom FPGA designs that interface with all
components of the board.
General Description
The Arria II GX FPGA development board, 6G Edition provides a hardware platform
for developing and prototyping low-power, high-performance, and logic-intensive
designs. The board provides a wide range of peripherals and memory interfaces to
facilitate the development of the Arria II GX FPGA designs.
1. Overview
Two high-speed mezzanine card (HSMC) connector is available to add additional
functionality via a variety of HSMCs available from Altera
®
and various partners.
fTo see a list of the latest HSMCs available or to download a copy of the HSMC
specification, refer to the Development Board Daughtercards page of the Altera
website.
Design advancements and innovations, such as the 6.375-Gbps transceiver modules,
the PCI Express hard IP implementation, and programmable power technology
ensure that designs implemented in the Arria II GX FPGAs operate faster, with lower
power, and have a faster time to market than previous FPGA families.
fFor more information on the following topics, refer to the respective documents:
■ Arria II device family, refer to the Arria II GX Device Handbook.
■ PCI Express MegaCore function, refer to the PCI Express Compiler User Guide.
■ HSMC Specification, refer to the High Speed Mezzanine Card (HSMC) Specification.
When handling the board, it is important to observe the following static discharge
precaution:
cWithout proper anti-static handling, the board can be damaged. Therefore, use
anti-static handling precautions when touching the board.
Page 9
Introduction
1A complete set of schematics, a physical layout database, and GERBER files for the
fFor information about powering up the board and installing the demonstration
2. Board Components
This chapter introduces the major components on the Arria II GX FPGA development
board, 6G Edition.
provides a brief description of all component features of the board.
development board reside in the Arria II GX development kit documents directory.
software, refer to the Arria II GX FPGA Development Kit, 6G Edition User Guide.
This chapter consists of the following sections:
■ “Board Overview”
■ “Featured Device: Arria II GX Device” on page 2–4
Figure 2–1 illustrates major component locations and Tabl e 2–1
■ “MAX II CPLD EPM2210 System Controller” on page 2–6
■ “Configuration, Status, and Setup Elements” on page 2–11
■ “Clock Circuitry” on page 2–20
■ “General User Input/Output” on page 2–23
■ “Components and Interfaces” on page 2–27
■ “Memory” on page 2–38
■ “Power Supply” on page 2–49
■ “Statement of China-RoHS Compliance” on page 2–52
Board Overview
This section provides an overview of the Arria II GX FPGA development board, 6G
Edition, including an annotated board image and component descriptions.
provides an overview of the development board features.
Table 2–1. Arria II GX FPGA Development Board, 6G Edition Components (Part 2 of 3)
Board ReferenceTypeDescription
D11, D12, D13Configuration LEDsIlluminates to show the LED sequence that determines which flash
memory image loads to the FPGA when LOAD IMAGE is pressed.
D19, D20, D21,
Ethernet LEDsShows the connection speed as well as transmit or receive activity.
D22, D23
D4, D5HSMC port A LEDsYou can configure these LEDs to indicate transmit or receive activity.
D6HSMC port A present LEDIlluminates when a daughtercard is plugged into the HSMC port A.
D2, D3HSMC port B LEDsYou can configure these LEDs to indicate transmit or receive activity
(only populated when a EP2AGX260 device is installed).
D1HSMC port B present LEDIlluminates when a daughtercard is plugged into the HSMC port B
(only populated when a EP2AGX260 device is installed).
D24, D25, D26PCI Express link LEDsYou can configure these LEDs to display the PCI Express link width
(x1, x4, x8).
Clock Circuitry
U26Programmable oscillator
(125 MHz default)
Programmable oscillator with a default frequency of 125.00 MHz. The
frequency is programmable using the MAX II CPLD EPM2210 System
Controller. For general use such as memories, gigabit Ethernet
(125 M/156.25 M), Serial RapidIO™ (SRIO) (125 M), or PCI Express
(100 M).
U30Programmable oscillator
(100 MHz default)
Programmable oscillator with a default frequency of 100.00 MHz. The
frequency is programmable using the MAX II CPLD EPM2210 System
Controller. For general use such as memories, gigabit Ethernet
(125 M/156.25 M), SRIO (125 M), PCI Express (100 M), or XAUI
(156.25 M). Multiplex with CLKIN_SMA_P based on CLK_SEL
switch value.
Y550 MHz oscillator50.000 MHz crystal oscillator for general purpose logic.
Y6100 MHz oscillator100.000 MHz crystal oscillator for general purpose logic.
U25155.52 MHz oscillator155.520 MHz crystal oscillator for SONET.
J10, J11Clock input SMAsDrive LVPECL-compatible clock inputs into the clock multiplexer buffer
(U33).
J12Clock output SMADrive out 2.5-V CMOS clock output from the FPGA.
General User Input/Output
D7, D8, D9, D10User LEDsFour user LEDs. Illuminates when driven low.
SW2User DIP switchQuad user DIP switches. When the switch is ON, a logic 0 is selected.
PB3CPU reset push-button switchPress to reset the FPGA logic.
PB4MAX II reset push-button
Press to reset the MAX II CPLD EPM2210 System Controller.
switch
PB1, PB2General user push-button
Two user push-button switches. Driven low when pressed.
Tab le 2–7 lists the MAX II CPLD EPM2210 System Controller component reference
and manufacturing information.
Table 2–7. MAX II CPLD EPM2210 System Controller Component Reference and Manufacturing Information
Board ReferenceDescriptionManufacturer
U32IC - MAX II CPLD EPM2210
256FBGA -3 LF 2.5V VCCINT
CorporationEPM2210F256C3Nwww.altera.com
Altera
Manufacturing
Part Number
Manufacturer
Configuration, Status, and Setup Elements
Website
Configuration
This section describes the board's configuration, status, and setup elements.
This section describes the FPGA, flash memory, and MAX II CPLD EPM2210 System
Controller device programming methods supported by the Arria II GX FPGA
development board, 6G Edition. The Arria II GX FPGA development board, 6G
Edition supports the following three configuration methods:
■ Embedded USB-Blaster is the default method for configuring the FPGA at any
time using the Quartus II Programmer in JTAG mode with the supplied USB cable.
■ External USB-Blaster for configuring the FPGA using the external USB-Blaster.
■ Flash memory download is used for configuring the FPGA using stored images
from the flash memory on either power-up or pressing the LOAD IMAGE
push-button switch (PB5).
FPGA Programming over Embedded USB-Blaster
The USB-Blaster is implemented using a USB Type-B connector (J6), a FTDI USB 2.0
PHY device (U15), and an Altera MAX II CPLD (U32). This allows the configuration
of the FPGA using a USB cable directly connected between the USB port on the board
(J6) and a USB port of a PC running the Quartus II software. The JTAG chain is
normally mastered by the embedded USB-Blaster found in the MAX
EPM240Z.
The embedded USB-Blaster is automatically disabled when an external USB-Blaster is
connected to the JTAG chain.
Figure 2–4 illustrates the JTAG chain.
Figure 2–4. JTAG Chain
Each jumper shown in Figure 2–4 is located in the JTAG chain header (J9) on the front
of the board. To connect a device or interface in the chain, the corresponding shunt
must be removed from the jumper. Install a shunt on each of the four jumper positions
to only have the FPGA in the chain.
The MAX II CPLD EPM2210 System Controller must be in the chain to use some of the
GUI interfaces. For this setting, remove the left-most jumper shunt from the JTAG
chain header (J9).
Flash Memory Programming
Flash memory programming is possible through a variety of methods using the Arria
II GX device.
The default method is to use the factory design called the Board Update Portal. This
design is an embedded webserver, which serves the Board Update Portal web page.
The web page allows you to select new FPGA designs including hardware, software,
or both in an industry-standard S-Record File (.flash) and write the design to the user
hardware page (page 1) of the flash memory over the network.
The secondary method is to use the pre-built parallel flash loader (PFL) design
included in the development kit. The development board implements the Altera PFL
megafunction for flash memory programming. The PFL megafunction is a block of
logic that is programmed into an Altera programmable logic device (FPGA or CPLD).
The PFL functions as a utility for writing to a compatible flash memory device. This
pre-built design contains the PFL megafunction that allows you to write either page 0,
page 1, or other areas of flash memory over the USB interface using the Quartus II
software. This method is used to restore the development board to its factory default
settings.
Other methods to program the flash memory can be used as well, including the
®
Nios
II processor.
fFor more information on the Nios II processor, refer to the Nios II Processor page of
the Altera website.
FPGA Programming from Flash Memory
On either power-up or by pressing the load image push-button switch (PB5), the
MAX
II CPLD EPM2210 System Controller's PFL configures the FPGA from the flash
memory when the CONFIG_LED0 is ON. The PFL megafunction reads 16-bit data
from the flash memory and converts it to fast passive parallel (FPP) format. This 8-bit
data is then written to the FPGA's dedicated configuration pins during configuration.
There are two pages reserved for the FPGA configuration data. The factory hardware
page is considered page 0 and is loaded upon power-up if the USER LOAD DIP switch
(SW4.4) is set to '1'. Otherwise, the user hardware page 1 is loaded. Pressing the load
image push-button switch (PB5) loads the FPGA with a hardware page based on
which CONFIG[2:0] LED (D11, D12, D13) is illuminated.
Tab le 2–9 defines the
hardware page that loads when the load image push-button switch (PB5) is pressed.
Table 2–9. Load Image Push-Button Switch (PB5) LED Settings (1)(2)
IMAGE0IMAGE1IMAGE2Design
ONOFFOFFFactory hardware
OFFONOFFUser hardware 1
OFFOFFONUser hardware 2
Notes to Table 2–9:
(1) ON indicates a setting of ’1’.
(2) OFF indicates a setting of ’0’.
FPGA Programming over External USB-Blaster
The JTAG programming header provides another method for configuring the FPGA
(U19) using an external USB-Blaster device with the Quartus II Programmer running
on a PC. The external USB-Blaster is connected to the board through the JTAG
connector (J5). Install a shunt onto the JTAG chain header (J9) pins 1 and 2 to remove
the MAX II CPLD device from the JTAG chain so that the FPGA is the only device on
the JTAG chain.
fFor more information on the following topics, refer to the respective documents:
■ Board Update Portal, refer to the Arria II GX FPGA Development Kit, 6G Edition User
Guide.
■ PFL design, refer to the Arria II GX FPGA Development Kit, 6G Edition User Guide.
■ PFL megafunction, refer to Parallel Flash Loader Megafunction User Guide.
Status Elements
The development board includes status LEDs. This section describes the status
elements.
Tab le 2–10 lists the LED board references, names, and functional descriptions.
Table 2–10. Board-Specific LEDs (Part 1 of 2)
Board ReferenceLED NameDescription
D18PowerBlue LED. Illuminates when 2.5 V power is active.
D14CONF DONEGreen LED. Illuminates when the FPGA is successfully configured. Driven by the
MAX II CPLD EPM2210 System Controller.
D15LoadingGreen LED. Illuminates when the MAX II CPLD EPM2210 System Controller is
actively configuring the FPGA. Driven by the MAX II CPLD EPM2210 System
Controller wire-OR'd with the embedded USB-Blaster CPLD.
D16ErrorRed LED. Illuminates when the MAX II CPLD EPM2210 System Controller fails to
configure the FPGA. Driven by the MAX II CPLD EPM2210 System Controller.
D11, D12, D13CONFIG[2:0]Green LEDs. Illuminates to indicate which hardware page loads from flash
memory.
D19ENET TXGreen LED. Illuminates to indicate Ethernet PHY transmit activity. Driven by the
Marvell 88E1111 PHY.
D20ENET RXGreen LED. Illuminates to indicate Ethernet PHY receive activity. Driven by the
The JTAG chain header switch (J9) is provided to either remove or include devices in
the active JTAG chain. However, the Arria II GX FPGA device is always in the JTAG
chain.
Tab le 2–14 shows the switch controls and its descriptions.
Table 2–14. JTAG Chain Header Switch Controls
SwitchSchematic Signal NameDescriptionDefault
1MAX_JTAG_ENON : Bypass MAX II CPLD EPM2210 System Controller
OFF : MAX II CPLD EPM2210 System Controller in-chain
The load image push-button switch, RESET_CONFIGn (LOAD IMAGE) (PB5), is an
input to the MAX
a reconfiguration of the FPGA from flash memory. The location in the flash memory is
based on the LED_CONFIG_LED[2:0] setting when the button is released. Valid
settings include LED_CONFIG_LED0, LED_CONFIG_LED1, or LED_CONFIG_LED2 on
the three pages in flash memory reserved for FPGA designs.
The image select push-button switch, factory (IMAGE SEL)(PB6), toggles the
LED_CONFIG_LED[2:0] sequence. Refer to
LED_CONFIG_LED[2:0] sequence definitions.
The MAX II reset push-button switch, MAX_RESETn (PB4), resets the MAX II CPLD
EPM2210 System Controller.
II CPLD EPM2210 System Controller. The push-button switch forces
Tab le 2–19 shows the external clock inputs for the Arria II GX FPGA development
board, 6G Edition.
Table 2–19. Arria II GX FPGA Development Board, 6G Edition Clock Inputs
SourceSchematic Signal NamePinI/O StandardDescription
U25CLK_155_PR29LVPECL155.52 MHz oscillator which drives the
transceiver Q2 reference clock input with
100 Ω OCT.
LVDS input to the bottom edge of PLL input.
LVDS input to the transceiver Q2 reference
clock input with 100 Ω OCT.
input to the top edge of PLL input.
SMA or
100.000 MHz
(Default
Frequency) (1)
125.000 MHz
(Default
Frequency) (2)
CLK_155_NR30
CLKIN_BOT_PAJ19LVDSInput to the fan-out buffer (U33) which drives
CLKIN_BOT_NAK19
CLKIN_REF_Q2_PU29Input to the fan-out buffer (U33) which drives
CLKIN_REF_Q2_NU30
CLKIN_TOP_PF18LVDSProgrammable oscillator which drives LVDS
CLKIN_TOP_NF17
CLK_REF_Q1_1_PAA29Programmable oscillator which drives LVDS
CLK_REF_Q1_1_NAA30
CLK_REF_Q1_2_PW29
input to the transceiver Q1 reference clock
input with 100 Ω OCT.
CLK_REF_Q1_2_NW30
CLK_REF_Q3_PN29Programmable oscillator which drives LVDS
CLK_REF_Q3_NN30
input to the transceiver Q3 reference clock
input with 100 Ω OCT.
Samtec HSMCHSMA_CLKIN0AP17LVTTLSingle-ended input from the installed HSMC
port A cable or board.
Samtec HSMCHSMA_CLKIN_P1U6LVDS or LVTTLLVDS input from the installed HSMC port A
HSMA_CLKIN_N1U5
cable or board. Can also support two LVTTL
inputs.
Samtec HSMCHSMA_CLKIN_P2K18LVDS or LVTTLLVDS input from the installed HSMC port A
HSMA_CLKIN_N2J18
cable or board. Can also support two LVTTL
inputs.
Samtec HSMCHSMB_CLKIN0AP16LVTTLSingle-ended input from the installed HSMC
port B cable or board.
PCI Express
Edge
Notes to Table 2–19:
(1) CDCM61001 has a default frequency of 100 MHz, but can also be set by the MAX II CPLD to frequencies of 125 MHz and 156.25 MHz.
(2) CDCM61004 has a default frequency of 125 MHz, but can also be set by the MAX II CPLD to frequencies of 100 MHz and 156.25 MHz.
PCIE_REFCLK_PAE29HCSLHigh-Speed Current Steering Logic (HCSL)
This section describes the user I/O interface to the FPGA, including the push-buttons,
DIP switches, status LEDs, and character LCD.
User-Defined Push-Button Switches
The development board includes three user-defined push-button switches: two
general user push-button switches and one CPU reset. For information on the system
and safe reset push-button switches, refer to
Switches” on page 2–19.
“Reset Configuration Push-button
Board references PB1 and PB2 are push-button switches that allow you to interact
with the Arria II GX device. When the switch is pressed and held down, the device
pin is set to logic 0; when the switch is released, the device pin is set to logic 1. There is
no board-specific function for these general user push-button switches.
The board reference PB3 is the CPU reset push-button switch, CPU_RESET, which is
an input to the Arria II GX device. CPU_RESET is intended to be the master reset
signal for the FPGA design loaded into the Arria II GX device. It also acts as a regular
I/O pin.
Tab le 2–22 lists the user-defined push-button switch schematic signal names and their
corresponding Arria II GX device pin numbers.
Table 2–22. User-defined Push-button Switch Schematic Signal Names and Functions
Tab le 2–23 lists the user-defined push-button switch component reference and the
manufacturing information.
Table 2–23. User-defined Push-button Switch Component Reference and Manufacturing Information
Manufacturer
Board ReferenceDescriptionManufacturer
PB1 to PB3Push-button switchDawning Precision Co.TS-A02SA-2-S100http://www.dawning2.com.tw/
Part NumberManufacturer Website
company.php
User-Defined DIP Switches
Board reference SW2 is a 4-pin DIP switch. The switches in SW2 are user-defined and
provided for additional FPGA input control. There is no board-specific function for
these switches.
Tab le 2–24 lists the user-defined DIP switch schematic signal names and their
corresponding Arria II GX pin numbers.
Table 2–24. User-defined DIP Switch Schematic Signal Names and Functions
Schematic
Board ReferenceDescription
SW2.1
SW2.2USER_DIP1U9
SW2.3USER_DIP2V9
SW2.4USER_DIP3U4
User-defined DIP switch connected to
the FPGA device. When the switch is
in the OFF position, a logic 1 is
selected. When the switch is in the
ON position, a logic 0 is selected.
Signal NameI/O Standard
USER_DIP0
2.5-V
Arria II GX Device
Pin Number
Tab le 2–25 lists the user-defined DIP switch component reference and the
manufacturing information.
Table 2–25. User-defined DIP Switch Component Reference and Manufacturing Information
The development board includes general and HSMC user-defined LEDs. This section
describes all user-defined LEDs. For information on board specific or status LEDs,
refer to
General User-Defined LEDs
Board references D7 through D10 are four user-defined LEDs which allow status and
debugging signals to be driven to the LEDs from the FPGA designs loaded into the
Arria II GX device. The LEDs illuminate when a logic 0 is driven, and turns off when a
logic 1 is driven. There is no board-specific function for these LEDs.
Tab le 2–26 lists the user-defined LED schematic signal names and their corresponding
Arria II GX pin numbers.
Table 2–26. User-defined LED Schematic Signal Names and Functions
Schematic
Board ReferenceDescription
D10
D9USR_LED1J4
D8USR_LED2J5
D7USR_LED3R5
User-defined LEDs.
Driving a logic 0 on the I/O
port turns the LED ON. Driving
a logic 1 on the I/O port turns
the LED OFF.
Signal NameI/O Standard
USR_LED0
2.5-V
Arria II GX Device
Pin Number
G1
Tab le 2–27 lists the user-defined LED component reference and the manufacturing
information.
Table 2–27. User-defined LED Component Reference and Manufacturing Information
Device
Board Reference
D7 to D10Green LEDsLite-OnLTST-C170KGKTwww.us.liteon.com/opto.index.html
DescriptionManufacturer
Manufacturer
Part NumberManufacturer Website
HSMC User-Defined LEDs
The HSMC port A and B have two LEDs located nearby. There are no board-specific
functions for the HSMC LEDs. However, the LEDs are labeled TX and RX, and are
intended to display data flow to and from the connected HSMC daughtercards. The
LEDs are driven by the Arria II GX device.
Tab le 2–28 lists the HSMC user-defined LED schematic signal names and their
corresponding Arria II GX pin numbers.
Table 2–28. HSMC User-defined LED Schematic Signal Names and Functions
Tab le 2–29 lists the HSMC user-defined LED component reference and the
manufacturing information.
Table 2–29. HSMC User-defined LED Component Reference and Manufacturing Information
Manufacturer
Board ReferenceDescriptionManufacturer
Part NumberManufacturer Website
D2 to D5Green LEDsLite-OnLTST-C170KGKTwww.us.liteon.com/opto.index.html
LCD
The development board contains a single 14-pin 0.1" pitch dual-row header that
interfaces to a 16 character
receptacle that mounts directly to the board's 14-pin header, so it can be easily
removed for access to components under the display. You can also use the header for
debugging or other purposes.
Tab le 2–30 summarizes the LCD pin assignments. The signal names and directions are
relative to the Arria II GX FPGA.
Table 2–30. LCD Pin Assignments, Schematic Signal Names, and Functions
× 2 line Lumex LCD display. The LCD has a 14-pin
Schematic Signal
Board ReferenceDescription
NameI/O Standard
J3.7LCD data busLCD_DATA0
J3.8LCD data busLCD_DATA1H3
J3.9LCD data busLCD_DATA2E1
J3.10LCD data busLCD_DATA3F2
J3.11LCD data busLCD_DATA4D2
J3.12LCD data busLCD_DATA5D1
2.5-V
J3.13LCD data busLCD_DATA6C2
J3.14LCD data busLCD_DATA7C1
J3.4LCD data or command selectLCD_D_CnJ1
J3.5LCD write enableLCD_WEnH1
J3.6LCD chip selectLCD_CSnJ2
Tab le 2–31 shows the LCD pin definitions, and is an excerpt from the Lumex data
sheet.
fFor more information such as timing, character maps, interface guidelines, and other
related documentation, visit www.lumex.com.
Table 2–31. LCD Pin Definitions and Functions (Part 1 of 2)
2×16 character display, 5×8 dot matrixLumex Inc.LCM-S01602DSR/Cwww.lumex.com
Manufacturer
Part Number
Components and Interfaces
This section describes the development board's communication ports and interface
cards relative to the Arria II GX device. The development board supports the
following communication ports:
■ PCI Express
■ 10/100/1000 Ethernet
■ HSMC
PCI Express
The Arria II GX FPGA development board, 6G Edition is designed to fit entirely into a
PC motherboard with a ×8 PCI Express slot that can accommodate a full height long
form factor add-in card. This interface uses the Arria II GX device's PCI Express hard
IP block, saving logic resources for the user logic application.
fFor more information on using the PCI Express hard IP block, refer to the PCI Express
Compiler User Guide.
Manufacturer
Website
The PCI Express interface supports auto-negotiating channel width from ×1 to ×4 to
×8 as well as the connection speed of Gen1 at 2.5 Gbps/lane for a maximum of
20
Gbps full-duplex.
The power for the board can be sourced entirely from the PCI Express edge connector
when installed into a PC motherboard. Although the board can also be powered by a
laptop power supply for use on a lab bench, it is not recommended to power from
both supplies at the same time. Ideal diode power sharing devices have been
designed into this board to prevent damages or back-current from one supply to the
other.
The PCIE_REFCLK_P signal is a 100 MHz differential input that is driven from the PC
motherboard on to this board through the edge connector. This signal is connected
directly to a Arria II GX REFCLK input pin pair using DC coupling. This clock is
terminated on the motherboard and therefore, no on-board termination is required.
This clock can have spread-spectrum properties that change its period between
9.847
ps to 10.203 ps. The I/O standard is HCSL.
Figure 2–8 shows the PCI Express reference clock levels.
Figure 2–8. PCI Express Reference Clock Levels
The JTAG and SMB are optional signals in the PCI Express specification. Both types of
signals are wired to the Arria II GX device but are not required for normal operation.
The PCI Express control DIP switch allows the presence detect grounding to be
altered to enable a ×1, ×4, or ×8 width edge connector. The PCI Express control DIP
switch does not support auto-negotiation.
Tab le 2–33 summarizes the PCI Express pin assignments. The signal names and
directions are relative to the Arria II GX FPGA.
Table 2–33. PCI Express Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 2)
A Marvell 88E1111 PHY device is used for 10/100/1000 BASE-T Ethernet connection.
The device is an auto-negotiating Ethernet PHY with an RGMII interface to the FPGA.
The MAC function must be provided in the FPGA for typical networking
applications. The Marvell 88E1111 PHY uses 2.5-V and 1.0-V power rails and requires
a 25 MHz reference clock driven from a dedicated oscillator. It interfaces to a HALO
HFJ11-1G02E model RJ45 with internal magnetics that can be used for driving copper
lines with Ethernet traffic.
Figure 2–9 shows the RGMII interface between the FPGA (MAC) and Marvell 88E1111
PHY.
Figure 2–9. RGMII Interface between FPGA (MAC) and Marvell 88E1111 PHY
RXD[3:0]
10/100/1000 Mbps
Ethernet MAC
TXD[3:0]
Marvell 88E1111
PHY
Device
Transformer
RJ45
RGMII Interface
Tab le 2–34 lists the Ethernet PHY interface pin assignments.
Table 2–34. Ethernet PHY Pin Assignments, Signal Names and Functions
Tab le 2–35 lists the Ethernet PHY interface component reference and manufacturing
information.
Table 2–35. Ethernet PHY Component Reference and Manufacturing Information
Board ReferenceDescriptionManufacturer
U24Ethernet PHY BASE-T deviceMarvell
Semiconductor
High-Speed Mezzanine Cards
The development board contains two HSMC interfaces called port A and port B. The
HSMC port B is only available in the Arria II GX FPGA development board, 6G
Edition. HSMC port A interface supports both single-ended and differential signaling
while HSMC port B interface only supports single-ended signaling. The HSMC
interface also allows JTAG, SMB, clock outputs and inputs, as well as power for
compatible HSMC cards. The HSMC is an Altera-developed open specification, which
allows you to expand the functionality of the development board through the
addition of daughtercards (HSMCs).
fFor more information about the HSMC specification such as signaling standards,
signal integrity, compatible connectors, and mechanical information, refer to the High
Speed Mezzanine Card (HSMC) Specification manual.
The HSMC connector has a total of 172 pins, including 120 signal pins, 39 power pins,
and 13 ground pins. The ground pins are located between the two rows of signal and
power pins, acting both as a shield and a reference. The HSMC host connector is
based on the 0.5 mm-pitch QSH/QTH family of high-speed, board-to-board
connectors from Samtec. There are three banks in this connector. Bank 1 has every
third pin removed as done in the QSH-DP/QTH-DP series. Bank 2 and bank 3 have
all the pins populated as done in the QSH/QTH series.
Manufacturing
Part Number
Manufacturer
Website
88E1111-B2-CAAIC000www.marvell.com
Figure 2–10 shows the bank arrangement of signals with respect to the Samtec
The HSMC interface has programmable bi-directional I/O pins that can be used as
2.5-V LVCMOS, which is 3.3-V LVTTL-compatible. These pins can also be used as
various differential I/O standards including, but not limited to, LVDS, mini-LVDS,
and RSDS with up to 17 full-duplex channels.
1As noted in the High Speed Mezzanine Card (HSMC) Specification manual, LVDS and
single-ended I/O standards are only guaranteed to function when mixed according to
either the generic single-ended pin-out or generic differential pin-out.
Tab le 2–36 lists the HSMC port A interface pin assignments, signal names, and
functions.
Table 2–36. HSMC Port A Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 4)
Table 2–37. HSMC Port B Pin Assignments, Schematic Signal Names, and Functions (Part 4 of 4)
Arria II GX
Board
ReferenceDescription
J1.158Dedicated CMOS I/O bit 75HSMB_D75
J1.160HSMC port B presence detectHSMB_PSNT_nAG28
D2User LED to show RX data activity on
HSMC port B
D3User LED to show TX data activity on HSMC
port B
Schematic Signal
NameI/O Standard
HSMB_RX_LEDAF23
HSMB_TX_LEDAE24
2.5-V
Device
Pin Number
V5
Tab le 2–38 lists the HSMC connector component reference and manufacturing
information.
Table 2–38. HSMC Connector Component Reference and Manufacturing Information
Board ReferenceDescriptionManufacturer
J1 and J2HSMC, custom version of QSH-DP
family high-speed socket.
SamtecASP-122953-01www.samtec.com
Memory
This section describes the board's memory interface support and also their signal
names, types, and connectivity relative to the Arria II GX device. The board has the
following memory interfaces:
■ DDR3
■ DDR2 SODIMM
■ SSRAM
■ Flash
fFor more information about the memory interfaces, refer to the following documents:
■ Timing Analysis section in volume 4 of the External Memory Interface Handbook.
■ DDR, DDR2, and DDR3 SDRAM Design Tutorials section in volume 6 of the
External Memory Interface Handbook.
Manufacturing
Part Number
Manufacturer
Website
DDR3
There is a single DDR3 device, providing 128-Mbyte interface with a 16-bit data bus.
This memory interface is designed to run at a maximum frequency of 333 MHz for a
maximum theoretical bandwidth of over 10.6 Gbps. The internal bus in the FPGA is
typically 2 or 4 times the width at full-rate or half-rate respectively. For example, a
333
MHz 16-bit interface will become a 166.5 MHz 64-bit bus.
Tab le 2–39 lists the DDR3 pin assignments, signal names, and functions. The signal
names and types are relative to the Arria II device in terms of I/O setting and
direction.
Table 2–39. DDR3 Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 2)
Arria II GX
Schematic Signal
Board ReferenceDescription
U13.E3Data bus byte lane 0DDR3_DQ0
U13.F7Data bus byte lane 0DDR3_DQ1B7
U13.F2Data bus byte lane 0DDR3_DQ2K17
U13.F8Data bus byte lane 0DDR3_DQ3A6
U13.H3Data bus byte lane 0DDR3_DQ4A3
U13.H8Data bus byte lane 0DDR3_DQ5A4
U13.G2Data bus byte lane 0DDR3_DQ6L16
U13.H7Data bus byte lane 0DDR3_DQ7B3
U13.E7Write mask byte lane 0DDR3_DM0B9
U13.F3Data strobe P byte lane 0DDR3_DQS_P0G14
U13.G3Data strobe N byte lane 0DDR3_DQS_N0F15
U13.D7Data bus byte lane 1DDR3_DQ8D13
U13.C3Data bus byte lane 1DDR3_DQ9F13
U13.C8Data bus byte lane 1DDR3_DQ10A2
U13.C2Data bus byte lane 1DDR3_DQ11J15
U13.A7Data bus byte lane 1DDR3_DQ12D12
U13.A2Data bus byte lane 1DDR3_DQ13G15
U13.B8Data bus byte lane 1DDR3_DQ14B4
U13.A3Data bus byte lane 1DDR3_DQ15G13
U13.D3Write mask byte lane 1DDR3_DM1K15
U13.C7Data strobe P byte lane 1DDR3_DQS_P1F12
U13.B7Data strobe N byte lane 1DDR3_DQS_N1E12
NameI/O Standard
1.5-V SSTL Class I
Device
Pin Number
J16
Tab le 2–40 lists the DDR3 component reference and manufacturing information.
Table 2–40. DDR3 Component Reference and Manufacturing Information
Manufacturing
Board ReferenceDescriptionManufacturer
U138 M × 16 × 8 banks, 667M, CL9 MicronMT41J64M16LA-15Ewww.micron.com
Part Number
Manufacturer
Website
DDR2 SODIMM
There is a DDR2 200-pin SODIMM device, providing 1-Gbyte single-rank DIMM with
a 64-bit data bus. This memory interface is designed to run at a maximum fequency of
333 MHz for a maximum theoretical bandwidth of over 42.6 Gbps. The internal bus in
the FPGA is typically 2 or 4 times the width at full rate or half rate respectively. For
example, a 333
Tab le 2–41 lists the DDR2 SODIMM pin assignments, signal names, and its functions.
The signal names and types are relative to the Arria II device in terms of I/O setting
and direction.
Module128 M × 8 banks, 400M, CL6MicronMT8HTF12864HZ-800G1www.micron.com
Manufacturing
Part Number
Manufacturer
Website
SSRAM
The SSRAM device consists of a single standard synchronous SRAM, providing
2
Mbyte of with a 36-bit data bus. This device is part of the shared FSM bus which
connects to the flash memory, SRAM, and MAX
The device speed is 200 MHz single-data-rate. There is no minimum speed for this
device. The theoretical bandwidth of this 32-bit memory interface is 6.4 Gbps for
continuous bursts. The read latency for any address is two clocks, in which at
200
MHz, the latency is 10 ns and at 50 MHz, the latency is 40 ns. The write latency is
one clock.
Tab le 2–43 lists the SSRAMpin assignments, signal names, and functions. The signal
names and types are relative to the Arria II GX device in terms of I/O setting and
direction.
Tab le 2–44 lists the SSRAM component reference and manufacturing information.
Table 2–44. SSRAM Component Reference and Manufacturing Information
Manufacturing
Board ReferenceDescriptionManufacturer
U22Standard Synchronous Pipelined
SCD, 512K × 36, 200 MHz
ISSI Inc.IS61VPS51236A-200B3www.issi.com
Part Number
Flash
The flash interface consists of a single synchronous flash memory device, providing
64 Mbyte with a 16-bit data bus. This device is part of the shared FSM bus which
connects to the flash memory, SRAM, and MAX II CPLD EPM2210 System Controller.
There are two 512-Mbyte die per package. The parameter blocks are 32 K and main
blocks are 128
space.
This 16-bit data memory interface can sustain burst read operations at up to 52 MHz
for a throughput of 832 Mbps. The write performance is 270 µs for a single word and
310
µs for a 32-word buffer. The erase time is 800 ms for a 128 K main block.
Tab le 2–45 lists the flash pin assignments, signal names, and functions. The signal
names and types are relative to the Arria II GX device in terms of I/O setting and
direction.
Table 2–45. Flash Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 2)
Board ReferenceDescriptionSchematic Signal NameI/O Standard
U23.A1Address busFSM_A1
U23.B1Address busFSM_A2D29
U23.C1Address busFSM_A3J21
U23.D1Address busFSM_A4L13
U23.D2Address busFSM_A5C8
U23.A2Address busFSM_A6N9
U23.C2Address busFSM_A7D20
U23.A3Address busFSM_A8A23
U23.B3Address busFSM_A9B24
U23.C3Address busFSM_A10C24
U23.D3Address busFSM_A11E25
U23.C4Address busFSM_A12F21
U23.A5Address busFSM_A13J19
U23.B5Address busFSM_A14H19
U23.C5Address busFSM_A15K21
U23.D7Address busFSM_A16L21
U23.D8Address busFSM_A17F25
K. The parameters of this device are located at the top of the address
The development board's power is provided through a laptop style DC power input.
The input voltage must be in the range of 14
down to various power rails used by the components on the board and installed into
the HSMC connectors.
An on-board multi-channel analog-to-digital converter (ADC) is used to measure both
the voltage and current for several specific board rails. The power utilization is
displayed using a GUI that can graph power consumption versus time.
Power Distribution System
Figure 2–11 shows the power distribution system on the development board.
Regulator inefficiencies and sharing are reflected in the currents shown, which are
conservative absolute maximum levels.
There are 14 power supply rails which have on-board voltage and current sense
capabilities. These 8-channel differential 24-bit ADC devices and rails are split from
the primary supply plane by a low-value sense resistor for the ADC to measure
voltage and current. An SPI bus connects these ADC devices to the MAX II CPLD
EPM2210 System Controller as well as the Arria II GX FPGA.
Figure 2–12 shows the block diagram for the power measurement circuitry.
Figure 2–12. Power Measurement Circuit
Tab le 2–47 lists the targeted rails. The Net Name column specifies the name of the rail
being measured and the Device Pin column specifies the devices attached to the rail. If
no subnet is named, the power is the total output power for that voltage.
Table 2–47. Power Rails Measurement Based on the Rotary Switch Position (Part 1 of 2)
SwitchSchematic Signal NameVoltage (V)Device PinDescription
0A2VCCIO_B3B_B5B_B6B2.5VCCIO_B3BBank 3B I/O power (HSMB)
VCCIO_B5BBank 5B I/O power (HSMB)
VCCIO_B7BBank 7B I/O power (HSMB)
1A2VCCIO_B5A2.5VCCIO_B5ABank 5A I/O power (FSM, flash)
2A2VCCIO_B6A2.5VCCIO_B6ABank 6A I/O power (SSRAM, MAX II, user I/O)
3A2VCCIO_B7B_B8A2.5VCCIO_B7BBank 7B I/O power (HSMA)
4A2VCCPD2.5VCCPDI/O pre-drivers and input buffers
VCCIO_B8ABank 8A I/O power (HSMA)
5A2VCCIO_B3A_B41.8VCCIO_B3ABank 3A I/O power (DDR2 SODIMM)
This document uses the typographic conventions shown in the following table.
Visual CueMeaning
Bold Type with Initial Capital
Letters
bold type Indicates directory names, project names, disk drive names, file names, file name
Italic Type with Initial Capital Letters Indicates document titles. For example, AN 519: Design Guidelines.
Italic type Indicates variables. For example, n + 1.
Initial Capital LettersIndicates keyboard keys and menu names. For example, Delete key and the Options
“Subheading Title”Quotation marks indicate references to sections in a document and titles of Quartus
Courier typeIndicates signal, port, register, bit, block, and primitive names. For example, data1,
1., 2., 3., and
a., b., c., and so on.
■ ■Bullets indicate a list of items when the sequence of the items is not important.
1 The hand points to information that requires special attention.
c
w
r The angled arrow instructs you to press Enter.
f The feet direct you to more information about a particular topic.
Indicates command names, dialog box titles, dialog box options, and other GUI
labels. For example, Save As dialog box.
extensions, and software utility names. For example, \qdesigns directory, d: drive,
and chiptrip.gdf file.
Variable names are enclosed in angle brackets (< >). For example, <file name> and
<project name>.pof file.
menu.
II Help topics. For example, “Typographic Conventions.”
tdi, and input. Active-low signals are denoted by suffix n. For example,
resetn.
Indicates command line commands and anything that must be typed exactly as it
appears. For example, c:\qdesigns\tutorial\chiptrip.gdf.
Also indicates sections of an actual file, such as a Report File, references to parts of
files (for example, the AHDL keyword SUBDESIGN), and logic function names (for
example, TRI).
Numbered steps indicate a list of items when the sequence of the items is important,
such as the steps listed in a procedure.
A caution calls attention to a condition or possible situation that can damage or
destroy the product or your work.
A warning calls attention to a condition or possible situation that can cause you
injury.