Alinco DJ-X10 Service Manual
DJ-X10
S e r v i c e M a n u a l
CON TE NTS
• SPECIFICATIONS
• CIRCUIT DESCRIPTION
•SEMICONDUCTOR DATA........................................7
• EXPLODED V IE W
• PARTS LIST...............................................................17
•ADJUSTMENT...........................................................21
• PC BOARD VIEW
• BLOCK DIAGRAM
• CIRCUIT DIAGRAM
....................................................
..................... .................
....................................................
....................................................
..................................................
.................................................. 33
2
3
14
24
31
ES AL IN CO , IN C
S P E C I F I C A T I O N S
Frequency range
Radio systems received
Frequency steps
Sensitivity
CTYP-)
Memory channels
Search pass mode channels
Priority channel 1
Memory banks
Channels per bank 40
Search bands
Scan speed Approx. 25 CH/sec
Antenna connector
Power supply
External power supply
Rated AF output
Power consumption At rated output Approx. 200 mA
Weight
Dimensions
Operating
temperature range
Frequency stability
0.1 - 1999.999950 MHz .
WFM, NFM, AM, USB, LSB.CW
50 Hz, 100 Hz, 1 kHz, 2 kHz, 5*Hz, 6.25 kHz, 9 kHz, 10 kHz, 12.5 kHz, 15 kHz, 20 kHz, 25 kHz,
30 kHz, 50 kHz, 100 kHz, 125 kHz, 150 kHz, 200 kHz. 250 kHz, 500 kHz
AM
SSB
NFM
WFM
0.1-0.5 MHz 10pV(20dBp)
0.5 - 5 MHz 1.5 pV( 3.5 dBp)
5 - 3 0 MHz 1 pV(0 dBp)
30 M Hz- .1000 MHz 1 pV(0 dBp)
(1 kHz 30 %mod *10 dB S/N)
0 .5 -5 MHz , -.0.5 pV(-6 dBp)
5 -3 0 MHz 0.25 |jV(-12 dB|j)
30 MHz ~ 1000 MHz 0.5 pV(-6 dBp)
(10 dB S/N)
5 -3 0 MHz 0.35 pV(-9 dBp)
30 - 1000 MHz 0.25 pV(-12 dBp)
1000 - 1300 MHz 1.5 pV(3.5 dBp)
1300 - 1999 MHz 10 pV(20 dBp)
(1 kHz 3.5 kHz 12 dB SINAD)
30 - 1000 MHz 1.5 pV(3.5 dBp)
(12 dB SINAD)
1200
1000
30
20
BNC, 50il
4.8V DC (Ni-Cd)/6V DC (AA dry cell)
8 - 15V DC
Min. 100 mW, 10% THD
Squelched Approx. 140 mA
BS ON Approx. 30 mA
Approx. 320 g
57 x 150 x 27.5 mm (without projections)
-10 - +50°C
±10 ppm
C I R C U I T D E S C R IP T I O N
1) Frequency
• Signals in the 0.1 - 449.99 MH z and 1500 ~ 2000 MHz bands are converted into the 736.25 MHz first IF
signal by the first local oscillator signal.
• Signals in the 450 ~ 1499.99 M Hz band are converted into the 275.45 MHz first IF signal by this same
first local oscillator signal.
• The first IF signal is converted into the 45.05 MHz second IF signal from the two second local oscillator
signals (671.2 and 230.4 MHz) by the second mixer circuit.
• Depending on the mode, the second IF signal is input to one of the two IF amplifier ICs. In one mode,
the second IF signal is mixed with a 34.35 M Hz third local oscillator signal and converted into a third IF
signal of 10.7 MHz, while in the other, it is mixed with a 44.595 MHz third local oscillator signal and
converted into the third IF signal of 455 kHz.
2) Receiver Block
Front-End Circuit
• The received signal from the antenna goes through the antenna circuits (D128, D124 and D125) and is
screened by seven band pass filters consisting of several antenna switches (D131, D111, D127, D112,
D126, D114, D 130, D115, D134, D119, D135, D121, D136, D122 and D133) to remove unwanted
signals.
•T he RF signal is amplified by each of the RF amplifiers Q123 (0.1 - 222 MH z), Q 125 (222 ~ 797 M Hz),
Q12 6 (797 ~ 2000 MHz) and Q118. It is then converted into the first IF signal by the first mixer circuit
(T101, T100, D109 and D 1 16).
• The adjacent signals in first IF signal, the 275.45 M Hz IF signal and the 736.25 MHz IF signal are filtered
out respectively by the band switch (D110 and D102), the IF filter (L113, L110, L107 and L101) and the
IF filter (FL102 and FL101). Then, the signals are input into the second mixer circuit (Q102).
• In the second mixer circuit, the 12.8 M Hz reference signal is mixed with either a 230.4 MHz second local
oscillator signal (amplified 18 times) or a 691. 2 MHz second local oscillator signal (amplified 54 times)
selected by a switch (D101), and is converted into a 45.05 MHz second IF signal.
• In the W FM mode, the second IF signal goes through an IF filter (L301) and is input into pin No. 16 of an
IF IC (IC305). A 10.7 M Hz third IF signal converted by the IC’s internal mixer is output from pin No. 14,
filtered of adjacent signals by a ceramic filter (FL302) and input into pin No. 12. Next, it is demodulated
by IC’s internal limiter amplifier and quadrature detection circuit, and output from pin No. 8 as an AF
signal.
• In the NFM, AM, SSB and C W modes, the second IF signal goes through an IF filter (XF300 and XF301)
and is input to pin No. 16 of an IF IC (IC304). A 455 kHz third IF signal converted by the IC ’s internal
mixer is output from pin No. 3 and is filtered of adjacent signals by a ceramic filter (FL301). Thereafter, a
switch (D 30 6 and D309) selects the m ode. In the NFM m ode, the signal is input to pin No. 5,
demodulated by IC ’s internal limiter amplifier and quadrature detection circuit, and output from pin No. 9
as an AF signal. In the AM mode, the signal is amplified by an AGC amplifier (Q313) and input to pin No.
7 of an IF IC (IC305). It is amplified inside the circuit, demodulated by the detection circuit and output
from pin No. 8 as an AF signal. In the SSB mode, the signal goes through a ceramic filter (FL303) and is
amplified by an AGC amplifier (Q313) and an IF amplifier (Q316). It is then mixed with a carrier signal,
which is generated by the BFO circuit (X302 and Q318) and fed through a buffer (Q317), demodulated
by a balanced modulation circuit consisting of diodes (Q315, D314 and D313), and output as an AF
signal.
• The AF signal for each of the modes is selected with a switch (IC308) and amplified by an AF signal
amplifier (IC309). It is controlled by an AF mute circuit (Q 319) and adjusted for volume by an electronic
volume (IC306). It is then amplified by an audio amplifier (IC307) and input to the speaker.
3) PLL Synthesizer Circuit
•T h e signal from a 12.8 M Hz crystal (X100) oscillator circuit (Q 100) is input to a PLL IC (IC101) to obtain
a 10 MH z reference oscillation signal frequency. The comparison frequency is output from a VCO circuit
(Q 114, L108, D104, D105, D107 and D108), amplified by an amplifier (Q115, Q 113 and Q 116) and
divided by a divider inside the PLL IC. It is then compared against the reference frequency to make the
PLL synthesizer.
•T he V CO output signal (675 ~ 1225 MHz) is amplified by a buffer amplifier (Q115, Q 1 13 and Q120) and
input into the first mixer as the first local oscillator signal.
• Frequencies of 9 kHz steps or less are varied by the VCX O circuit (X300, D 304 and D305) of the D/A
converter (IC303).
4) CPU Terminal Functions: /iPD78076 (E:XA0536) (T:XA0550)
o 8
o _ Û. 0. CL CL Q. Û. Q.
5 ? t— H H h* h- H h-
< < <
c\l •«-
^->> 00 00 000
CL<<(LCLCLQ_CLÜ-CL
CD ir> Tf co cm ^ o
ts£
CO ^ CM û
œ5<5<>><S>Q.Q.Ü.Q.Q.
n. çp in m
CL O. CL CL CL
H H I- I- H
Œ Œ <r Œ Œ
K <3 ÎÎ5 ^ C»5
Q- CM CM CM CM CM
Û. 1- 1- r- f- f-
P1 4 /AN 1 4 — [ i
P15 /AN15 «— E
P16 /AN16 •*— Œ
P17 /AN 1 7 - — ( T
AVSS E
P130/A N0 0 — Œ 70] — - P94
P1 31/AN01 -— (T
AVR E F1 CE
P70/S12/R XD — CL
P71/S02/TXD — Q ï
P72 /SC K 2 /ASC K — Q ï
O
vs s nz S ] — ► P36/BU Z
P2 0/S 11 —- Q I
P21/S01 — - E
P22/SCK1 — Q I
P23 /ST B — Q I 1 ] — P3 2/T02
P24/B US Y — Qz
P25/S 1 0 /SB 0 — Q I
P2 6/S 00/SB1 — Q I
P2 7 /S C K 0 S
P8 0 /A 0 — m 1 3 — P 101/T16/T06
P81/A1 -—E s a — P 100/T15 /T0 5
P82/A 2 » — [ S S I - P67 /A STB
P8 3/A 3 — |S
P8 4/A 4 •*—[ S 3 H — P 65/W R
U ) Ö S Q i- M < t) ^ m < Ü S # ® 0 ’-C M n W ^ W 0 i-C M «IQ
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cooBcoô^côcîî^îBtâî^^^c^cn^1« con. 3
Û-Û-Û-Û-Û-Û-Û-Û- Û. Û. Û. Û. Û. Û.
No.
1
Name Pin Name
P14/AN 14
CO
2 P15/AN 15 CB1
3
4
5
6
7 P131/AN01
8
9
10
11
12 VSS
13 P20/S11
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
P16/AN 16 CB2 0
P17/AN17
CB3 0
AVSS GND GND
P130/AN00
BARTU
VCXOIN O
AVREF1
VCC
P70/S12/RXD RXD ' I
P71/S02/TXD TXD O CLONE TX OUTPUT
P72/SCK2/ASCK
PCNTS 0
GND
RBO
P21/S01 RB1
P22//SCK1 RB2
P23/STB RB3
P24/BUSY RB4 I
P25/S10/SBO RB5
P26/S00/SB1 SRCHK
P27//SCK0
P80/A0
P81/A1
NOVOEDET
AO
A1 0
P82/A2 A2
P83/A3
A3 0
P84/A4 A4 0
P85/A5
P86/A6
A5 0
A6 0
P87/A7 A7 0
P40/AD0 DDO I/O
P41/AD1 DD1 I/O
P42/AD2
DD2 I/O
I/O
0 16KEY MATRIX
0 16KEY MATRIX
16KEY MATRIX
16KEY MATRIX
0
VCXO CONTROL
CLONE RX INPUT
DC DC POWER CONTROL
I
16KEY MATRIX
I 16KEY MATRIX
I
16KEY MATRIX
I 16KEY MATRIX
16KEY MATRIX
I
16KEY MATRIX
I SRCH KEY
0
EEPROM ADRESS
EEPROM ADRESS
0 EEPROM ADRESS
EEPROM ADRESS
EEPROM ADRESS
EEPROM ADRESS
EEPROM ADRESS
EEPROM ADRESS
EEPROM DATA
EEPROM DATA
EEPROM DATA
IC 506
Description H
NOT USED
VCC
GND
OFF ON
OFF ON
OFF
OFF
OFF ON
OFF
OFF ON
NOT USED
S — P122/RTP 2
Ï D - P1 21/RTP1
3 ] — P1 2 0/R TP0
2 ] - — P9 6
ID —— P 95
1 0 — ► P93
M l— - P92
S I — - P91
a — - P9o
S I — - P37
S ] — ► P35 /P C L
S I— ► P 34/T12
ID — P 3 3 /T11
M l - P 31/T01
I D - P 30/T00
E l — P103
sa-— pi o2
S ] — P66/W A IT
L HiZ
ON OFF
ON
ON
ON
Pull UP
5
No. Name Pin Name
32 P43/AD3 DD3
33
34
35 P46/AD6 DD6 I/O
36
37 P50/A8 A8
38 P51/A9 A9
39 P52/A10 A10 O
40 P53/A11 A11
41
42
43
44
45 P57/A15
46 P60
47 P61
48 P62
49
50 P64//RD RD I OUT ENABLE EEPROM
51
52
53 P67/ASTB OPTCT
54
55 P101/T16/T06 OPTDET I OPTION DETECT
56 P102 WIDES I
57 P103 LOCK I PLLLOCK UNLOCK
58 P30/T00 BEEP
59 P31/T01 AFS
60 P32/T02 MUTE
61
62 P34/T12 STB2
63 P35/PCL
64 P36/BUZ
65 P37 BUSLS 0 BUSY LED CONTROL
66
67
68 P92 DB6 o DATA LCD
69 P93
70
71 P95 RW/SID I/O RW/SID LCD
72 P96 RS/CS I/O
73 P120/RTP0
74 P121/RTP1
75
76 P123/RTP3
77
78 P125/RTP5
79 P126/RTP6
80
81
82 X2
83
84 VDD VDD
85 XT2
86 XT1/P07
87
88
89 P01/INTP1/T101
90
91 P03/INTP3
92 P04/INTP4 FUNK
93 P05/INTP5
94
95
96
97
98
99
100
P44/AD4 DD4
P45/AD5 DD5 I/O EEPROM DATA
P47/AD7 DD7 I/O EEPROM DATA
P54/A12 A12 O EEPROM ADRESS
P55/A13 A13 O EEPROM ADRESS
VSS GND
P56/A14
P63
P65//WR
P66/WAIT
P100/T15/T05 RDY I EEPROM STATUS
P33/T11
P90
P91 DB5 0
P94 E/SCLK 0 E/SCLK LCD
P122/RTP2 BATSV
P124/RTP4
P127/RTP7
VPP GND
X1 XTAL MAIN
/RESET
POO/INTPO/T100 LAMPK
P02/INTP2 POWK
P06/INTP6
AVDD VDD
AVREFO
P10/ANI0
P11/ANI1
P12/ANI2
P13/ANI3
A14 O EEPROM ADRESS
/RES O EEPROM LCD RESET
STB4 O
SHIFT
OECNT O OUT CONTROL IC500
/CE
/WE I
OPTSTB 0 STB FOR OPTION
STB3
STB1
LE 0 STB FOR IC101
DB4
DB7
DATA
CLK 0
RFL 0 FILTER CONTROL
RFM
RFH
BARS
IFS 0
/RST I RESET CPU
BRDET
MONK I MONITOR KEY
A I ROTARY ENCORDER
B I
VCC
SQD I
SM I
JRDET
BATTDET I
I/O
I/O
I/O
O EEPROM ADRESS
O
O EEPROM ADRESS
O NOT USED
0
0 CONTROL FOR OPTION ON OFF
0 BEEP
0
0
0 STB FOR IC300
0 STB FOR IC306
0 STB FOR IC103
0 DATA LCD
0
0
0
0 FILTER CONTROL
0 FILTER CONTROL
0
I LAMP KEY
I
I POWER KEY
I
I
Description H
EEPROM DATA
EEPROM DATA
EEPROM DATA
EEPROM ADRESS
EEPROM ADRESS
GND
STB FOR IC500
CHIP ENABLE EEPROM
WRITE ENABLE EEPROM
ENABLE BAND
AMP CONTROL
MUTE ON OFF
DATA LCD
DATA LCD
RS/CS LCD
DATA FOR 4094
CLK FOR 4094
BATT SAV CONTROL
NOT USED
IF SWITCH
XTAL MAIN
XTAL SUB
XTAL SUB
BAT DETECT
FUNCTION KEY
ROTARY ENCORDER
VDD
VCC
SO
S-METER
NOT USED
LOW BAT DETECT
ON OFF
ON OFF
ON OFF
ON OFF
OFF ON
OFF’ ON
OFF ON
OFF
OFF ON
OFF
OFF
OFF ON
L
ON
ON p
ON 0
HiZ
Pull UP
0
0
0
0
0
S E M I C O N D U C T O R D A T A
1) LC75366M (XA0345)
Pin Assignment
LIOdBIN [ 7
LIOdBOUT [T 17] RIOdBOUT
L2dBIN [5 16] R2dBIN
L2dBOUT [ T
0
LCT1 [2
LCT2 [ ? Tß] RCT2
LVref |T Ü ] RVrel
VDO [¥
CL ( J 32] S
DI [To TT] c e
20] RIOdBIN
19] RCT1
Ü R2dBOUT
13] VSS
2) NJU4066BM (XA0095)
SIQ.A
SIQ.B
ÏÏ] IN/OUT 'I
TÖ] OUT/IN J
9] OUT/IN 'j
T ] IN/OUT
Block Diagram
r
LIOdBIN Q
NO
LCT1 O
LC T 2 0
LVref Q
^•SJG.D
j-SIG.C
- o > o -
S O
C E O
C L Q
l NC
K
8
■o
0
<) -
CONTROL
z
GO
T3
1-
D
s
-0 -
1-
z
0
CO
T3
8
CM
CM
Œ
cr
- O--0-
LEVEL SHIFT
z z n
0L LATCH
~ T F
. SHIFT REGISTER
1-
■>
0
§
0
1r
- O
NC >
NO
-o-fo -
RIOdBIN
ÖHCT 1
QRCT2
QRVref
QVDD
QVSS
3) MB1511 (XA0173)
Pin Assignment
OSCIN [T
o s c o u t |T
O
NC [?
v p | T
vc c|T Tê] Bisw
d o [ F
g n d |T
l d [ 7
n c [ ?
tin [To
20] 0 R
19] NC
ïj[] 0 P
17] fout
T5] FC
14] LE
13] Data
12] NC
ÏT| Clock
Block Diagram
VCC
GNO
LE
OSCiN
OSCouT
: Data Signal
; Control Signai
4) NJM207 0 M T (X A 0 2 10 )
5) TA7806F (XA0267)
Pin Assignment Block Diagram
6) S-80733SLAXT2 (XA0357)
Pin Assignment Block Diagram
7) TA31136FN (XA0404)
detected RSSI output
8) HN58V 2 5 7A (X A 04 62 )
Pin Assignment
OE ü
A11 GE
A13 SI
WE E
RES IX
VCC QT
RDY/Busy tH
A14 QS
A12 QI
O
A9 DE
A8 EE
A7 Q2 52 i/oo
A6 Q3
A5 IS
A4 QI
A3 (31
Block Diagram
m aio
in ce
30] NC
m i/o7
55] 1/06
57] 1/05
m 1/04
IS 1/03
Sä VSS
53] 1/02
52] 1/01
5Ü] NC
T51 AO
551 A1
T7] A2
9) TA7792F (XA0464)
9
10) TC75S 5 1F (XA 0 4 6 5)
+IN 1
VSS 2
-IN 3
5 VDD
4 OUT
11) TK11235AM (XA0467)
Pin Assignment Block Diagram
12) TK11819M (XA0468)
Pin Assignment
VIN 1
OSC 2
DK 3
6 T1
5 GND
4 VOUT
13) BU4094BCFV (XA0506)
Pin Assignment
VDD
STROBE
DATA
CLOCK
Q1
Q2
Q3
o
16
15
14
13
12
11
OUTPUT
ENABLE
Q5
Q6
Q7
Q8
Block Diagram
VIN
Block Diagram
DATA (2)
CLOCK ©
STROBE ©
OUTPUT ©
ENABLE
-----
-----
-----
-----
8-STAGE
SHIFT REGISTER
8-BIT LATCHES
3-STATE
OUTPUTS
Q1
-----
©Q 'S "I SERIAL
-----
d)QS J OUTPUT
Q4
VSS 8
10
9 QS
Q S
PARALLEL OUTPUT
14) S-80725SN-2 (XA0528)
Pin Assignment
OUT 1
VDD 2
VSS 3
o
5 NC
4 NC
15) TA75W01FU-2 (XA0349)
OUT
-IN
Block Diagram
16) TC4W53FU (XA0348)
Pin Assignment
COMMON [T
INH
VEE
VSS
o
2 7
3
4 5
VDD
8
chO
6
ch1
A
17) S-812XXSG (XA0358)
Pin Assignment
GND
VIN 2
o
NC
Block Diagram
Block Diagram
VOUT 3
4 NC
18) Transistor, Diode, and LED Outline Drawings
DA204U
XD0130
DAN202U
XD0230
"d d
1SV231 1SS356
XD0260
XD0272
-
TA
■ff
DTB123YK
XU0155
XP1501TX
XU0172
MA742TX
XD0250
MA111
XD0290
A
1 B
UN9112
XU0182
MA741WK
XD0252
U f f
MA729
XD0291
A
2 B
u
UN5212
XU0184
1SS295
XD0306
U2FWJ44N
XD0294
A
2 F
f f
DTA143ZE
XU0185
1SS312
XD0307
d d
HVU350
XD0313
A
4
n
DTC143ZE
XU0186
□ OUT
2SC4649
XT0108
m .
J N
" E l i E f i
BRPG1201W
XL0028
2SA1213-Y
XT0088
d d d
2SC4181
XT0149
m .
L 1 7
f f i
SML:310MT
XL0036
2SC4738 2SC5006
XT0151
ne
LY
U b f f i
PG1101F
XL0045
m
2 4
dB B i
2SK425
XE0033
_ ff
X 1 3
X 1 4
H4-
f f f f
2SC5007
XT0152
m
3 4
Ü B Ü E
2SC5008
XT0153XT0150
m
4 4
L J B S i
UMC5N
XU0152
B C E
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