Alinco DJ-S47 E, DJ-S17 TFH, DJ-S17 E Service Manual

DJ-S17 E/TFH DJ-S47 E

S er vi ce M an u a l

CONTENTS

SPECIFICATIONS (DJ-S17)

General (DJ-S17)...................................................2

Transmitter (DJ-S17).............................................2

Receiver (DJ-S17).................................................2

General (DJ-S47)...................................................3

Transmitter (DJ-S47).............................................3

Receiver (DJ-S47).................................................3

CIRCUIT DESCRIPTION

1) Receiver System............................................4~6

2) Transmitter System

3) PLL Synthesizer Circuit

4) CPU & Peripheral Ciruits...............................7,8

5) M38268MCA-076GP(XA1121)

SEM ICONDUCTO R DATA

1) NMJ2070MT1 (XA0210)

2) S24CS64A01-J8T1 G(XA1117)

3) M62429FP/CF0J(XA1118).............................12

4) LM2902PWR(XA1106)

5) TA31136FN(EL)(XA0404).............................. 13

6) S80845CLNB-B66-T2G(XA1120)

7) MB15E07SR(XA1107)

8) XC6202P502M R(XA1119).............................15

9) Transistor, Diode and LED Outline Drawing

10) LCD Connection(EL0059)........................... 16

EXPLODED VIEW

1) Front View.

2) Rear View........................................................18

.......................................................17

..........................................

.................................6,7

..................

..................................11

......................

...................................

..................

....................................

8-10

....

13 14

PARTS LIST

MAIN Unit (DJ-S17)......................................19-24

Mechanical Unit (DJ-S17)..............................24,25

Packing Unit (DJ-S17) MAIN Unit (DJ-S47)

Mechanical Unit (DJ-S47)..............................31,32

Packing Unit (DJ-S47)

........................................

......................................

........................................

26-31

ADJUSTMENT

1) Required Test Equipment

2) Preparation

3) Adjustment Mode......................................35-41

4) Re-assembly....................................................42

......................................................34

.......................

33,34

PC BOARD VIEW

MAIN SIDE A (DJ-S17).......................................43

MAIN SIDE B (DJ-S17).......................................44

MAIN SIDE A (DJ-S47).......................................45

MAIN SIDE B (DJ-S47).......................................46

SCHEMATIC DIAGRAM (DJ-S17)............47

SCHEMATIC DIAGRAM (DJ-S47)............48

BLOCK DIAGRAM (DJ-S17) BLOCK DIAGRAM (DJ-S47)

.....................

AUNCO, inc

SPECIFICATIONS (DJ-S17)

General

Frequency range:

E : TX144~145.995MHz *144~145.995MHz

RX144-145.995MHz *144~145.995MHz

TFH: TX136-173.995MHz *150-173.995MHz

RX130-173.995MHz *150~173.995MHz

* Guaranteed range per specifications

Modulation: Frequency step: Memory channel:

Ant. impedance:

Frequency stability: Mic impedance:

Supply voltage: Current consumption:

Temperature range:

Ground: Dimension:

Weight:

Sub audible Tone (CTCSS): Sub audible Tone (DCS):

Transmitter

Power output:

Modulation: Spurious emission: Max. deviation: Mic. impedance:

F3E (FM) 5, 10, 12.5, 15, 20, 25, 30kHz step 200 channels + 1 call channel + 1 Repeater-Access function memory 50 £2 unbalanced

±5ppm 2k £2 DC 7.0-16.0V (EXT DC-IN)

1,4A (typical) Transmit high at 5W 250mA (typical) Receive at 500mW 70mA (typical) Standby 25mA (typical) Battery save on External DC: -10°C~+60°C (+14°F~+140°F) Battery packs: -10°C~+45°C (+14°F~+113°F) Negative ground 58(W)x 110(H) x36.4(D)mm (2.28"(W) x 4.33"(H) x 1,43"(D)) (with EBP-65) Approx. 280g (9.9oz) (with EBP-65) encoder/decoder installed (39 tones) encoder/decoder installed (104codes)

Approx. 5W (with EBP-65) Approx. 5W (with DC 13.8V) Approx. 0.8W (LOW output) Variable reactance

-60dB or less ±5kHz 2k £2

Receiver

System: Sensitivity: Intermediate frequency: Selectivity:

AF output:

Double-conversion super heterodyne

-14.0dB/<(0.2/<V) or less

1st IF 21.7MHz 2nd IF 450kHz

-6dB: 12kHz or more

-60dB: 26kHz or less 500mW (MAX) 400mW (8 £2, 10% distortion)

SPECIFICATIONS (DJ-S47)

General

Frequency range:

E: TX430~439.995MHz

RX430~439.995MHz

Modulation: Frequency step: Memory channel:

Ant. impedance:

Frequency stability: Mic impedance: Supply voltage: Current consumption:

Temperature range:

Ground: Dimension:

Weight:

Sub audible Tone (CTCSS): Sub audible Tone (DCS):

Transmitter

Power output:

Modulation: Spurious emission: Max deviation: Mic. impedance:

F3E (FM) 5, 10, 12.5, 15, 20, 25, 30kHz step 200 channels + 1 call channel + 1 Repeater-Access function memory 50 £2 unbalanced ±2.5ppm 2k £2 DC 7.0-16.0V (EXT DC-IN)

1,7A (typical) Transmit high at 5W 250mA (typical) Receive at 500mW 80mA (typical) Standby 27mA (typical) Battery save on External DC: -10°C~+60°C (+14°F~+140°F) Battery packs: -10°C~+45°C (+14°F~+113°F) Negative ground 58(W)x 110(H) x36.4(D)mm (2.28"(W) x 4.33"(H) x 1,43"(D)) (with EBP-65) Approx. 280g (9.9oz) (with EBP-65) encoder/decoder installed (39 tones) encoder/decoder installed (104 codes)

Approx. 4.5W (with EBP-65) Approx. 5W (with DC 13.8V) Approx. 0.8W (LOW output) Variable reactance

-60dB or less ±5kHz 2k £2

Receiver

System: Sensitivity: Intermediate frequency: Selectivity:

AF output:

Double-conversion super heterodyne

-12.0dB /x (0.25 /x V) or less

1st IF 38.85MHz 2nd IF 450kHz

-6dB: 12kHz or more

-60dB: 26kHz or less 500mW (MAX) 400mW (8 £2, 10% distortion)

CIRCUIT DESCRIPTION

1) Receiver System

DJ-S17 :The receiver system is a double superheterodyne system with a 21.7 MHz first IF and a 450 kHz

second IF.

DJ-S47 The receiver system is a double superheterodyne system with a 38.85 MHz first IF and a 450 kHz

second IF.

1. Front End

DJ-S17 The received signal at any frequency in the 130.000- to 173.995-MHz

(E version : 144.000- to 145.995-MHz) range is passed through the low-pass filter (L101, L102, L103, L113, C108, C120, C121, C124, C125, C126, C127 and C176) and ATT (Attenuator) circuit (Q120, R161, R187 and D112), and tuning circuit (C192, C193, C215, C216, D115, D116, L125 and L126), then amplified by the RF amplifier (Q114). The signal from Q114 is then passed through the tuning circuit (C200, C201, C219, C220, D117, D118, L128 and L129) and converted into 21.7 MHz by the mixer (Q116). The tuning circuit, which consists of C192, C193, C215, C216, L125, L126, variable capacitance diodes D115 and D116 and C200, C201, C219, C220, L128, L129, variable capacitance diodes D117 and D118, is controlled by the tracking voltage from the CPU so that it is optimized for the reception frequency. The local signal from the VCO is passed through the buffer (Q113), and supplied to the source of the mixer (Q116). The radio uses the lower side of the superheterodyne system.

DJ-S47 The received signal at any frequency in the 430.000- to 439.995-MHz

range is passed through the low-pass filter (L101, L102, L103, L113, C108, C120, C121, C124, C125, C126, C127 and C176) and ATT (Attenuator) circuit (Q120, R161, R187 and D112), and tuning circuit (C192, C193, C215, C216, D115, D116, L125 and L126), then amplified by the RF amplifier (Q114). The signal from Q114 is then passed through the tuning circuit (C200, C201, C219, C220, D117, D118, L128 and L129) and converted into 38.85 MHz by the mixer (Q116). The tuning circuit, which consists of C192, C193, C215, C216, L125, L126, variable capacitance diodes D115 and D116 and C200, C201, C219, C220, L128, L129, variable capacitance diodes D117 and D118, is controlled by the tracking voltage from the CPU so that it is optimized for the reception frequency. The local signal from the VCO is passed through the buffer (Q113), and supplied to the source of the mixer (Q116). The radio uses the lower side of the superheterodyne system.

2. ATT (Attenuator) Circuit

3. IF Circuit

DJ-S17 The mixer(Q116) mixes the received signal with the local signal to

This circuit is used in case the receiving signal is disturbed by interfering signai(s), attenuating the receiving signal(s) to reduce the interference. CPU (IC109)’s pin 10 outputs a DC current to drive Q120, controlling D112’s resistance to adjust the attenuation value.

obtain the sum of and difference between them. The crystal filter (FL101 , FL102) selects 21.7 MHz frequency from the results and eliminates the signals of the unwanted frequencies. The first IF amplifier (Q119) then amplifies the signal of the selected frequency. After the signal is amplified by the first IF amplifier (Q119), it is input to pin 16 of the demodulator IC (IC103). The second local signal of

21.25 MHz (shared with PLL IC reference oscillation), which is oscillated by the internal oscillation circuit in IC103 and crystal (X101), is input through pin 1 of IC103. Then these two signals are mixed by the internal mixer in IC103 and the result is converted into the second IF signal with a frequency of 450kHz. The second IF signal is output from pin 3 of IC103 tothe ceramic filter (FL103), where the unwanted frequency band of that signal is eliminated, and the resulting signal is sent back to the IC103 through 5 pins.

4. Demodulator Circuit

5. Audio Circuit

DJ-S47 The mixer(Q116) mixes the received signal with the local signal to

obtain the sum of and difference between them. The crystal filter (FL101) selects 38.85 MHz frequency from the results and eliminates the signals of the unwanted frequencies. The first IF amplifier (Q119) then amplifies the signal of the selected frequency. After the signal is amplified by the first IF amplifier (Q119), it is input to pin 16 of the demodulator IC (IC103). The second local signal of 38.4 MHz, which is oscillated by the internal oscillation circuit in IC103 and output of tripler circuit (L123, C202, C191, L122, Q115), is input through pin 1 of IC103. Then these two signals are mixed by the internal mixer in IC103 and the result is converted into the second IF signal with a frequency of 450kHz. The second IF signal is output from pin 3 of IC103 tothe ceramic filter (FL103), where the unwanted frequency band of that signal is eliminated, and the resulting signal is sent back to the IC103 through 5 pins.

The second IF signal input via pin 5 is demodulated by the internal limiter amplifier and Quadrature detection circuit in IC103, and output as an audio signal through pin 9.

The audio signal from pin 9 of IC103 is compensated to the audio frequency characteristics in the de-emphasis circuit (R223, R224, C241, C242) and amplified by the AF amplifier (Q196). The signal is then input to pin 1 of the electronic volume (IC107) for volume adjustment, and output from pin 2. The adjusted signal is sent to the audio power amplifier (IC106) through pin 2 to drive the speaker.

6. Squelch Circuit

2) Transmitter System

1. Modulator Circuit

2. Power Amplifier Circuit

3. APC Circuit

Part of the audio signal from pin 9 of IC103 is amplified by the noise filter amplifier and the internal noise amplifier in IC103. The desired noise of the signal is output through pin 14 of IC103 and input to pin 2 of CPU (IC109).

The audio signal is converted to an electric signal in either the internal or external microphone, and input to the microphone amplifier (IC102).

IC102 consists of four operational amplifiers; 1st amplifier (pins 1, 2,

and 3) is composed of high-pass filter, 2nd amplifier (pins 12, 13, and

14) is composed of pre-emphasis and IDC circuits, 3rd amplifier (pins

8, 9, and 10) is composed of a splatter filter and 4th amplifier (pins 7, 6, and 5) is composed of a splatter filter. The maximum frequency deviation is determined to its optimal value by VR104 and input to the cathode of the variable capacitance diode of the VCO, to change the electric capacity in the oscillation circuit.

The transmitted signal is oscillated by the VCO, amplified by the pre drive amplifier (Q104) and drive amplifier (Q103), and input to the power amplifier (Q102). The signal is then amplified by the power amplifier (Q102) and led to the antenna switch (D101 and D103) and low-pass filter (L104, L103, L102, L101, C107, C108, C109, C110, C111, C120, C121, C124, C125, C126, and C127 ), where unwanted high harmonic signals are reduced as needed, and the resulting signal is supplied to the antenna.

Part of the transmission power from the low-pass filter is detected by D105, converted to DC, and then amplified by a differential amplifier ( Q111 ). The output voltage controls the bias voltage from the gate of Q102 and Q103 to maintain the transmission power constant.

3) PLL Synthesizer Circuit

1.CPU control

2. Reference Frequency Circuit

DJ-S17 The reference frequency appropriate for the channel steps is obtained

The dividing ratio is obtained by sending data from the CPU (IC109) to pin 10, and sending clock pulses to pin 9 of the PLL IC (IC101). The oscillated signal from the VCO is amplified by the buffer (Q118), then input to pin 8 of IC101. Each programmable divider in IC101 divides the frequency of the input signal by N-value according to the frequency data, to generate a comparison frequency of 5 or 6.25 kHz.

by dividing the 21.25MHz reference oscillation (X101) by 4250 or 3400, according to the data from the CPU (IC109). When the resulting frequency is 5 kHz, channel steps of 5, 10, 15, 20, and 30 kHz are used. When it is 6.25 kHz, steps of 12.5, 25, and 50 kHz are used.

DJ-S47 :The reference frequency appropriate for the channel steps is obtained

3. Phase Comparator Circuit

4. PLL Loop Fitter Circuit

5. VCO Circuit

DJ-S17 :A Colpitts oscillation circuit driven by Q108 directly oscillates the

by dividing the 12.8MHz reference oscillation (X102) by 2048 or 2560, according to the data from the CPU (IC109). When the resulting frequency is 5 kHz, channel steps of 5, 10, 15, 20, and 30 kHz are used. When it is 6.25 kHz, steps of 12.5, 25, and 50 kHz are used.

The PLL (IC101) uses the reference frequency, 5 or 6.25 kHz. The phase comparator in the IC101 compares the phase of the frequency from the VCO with that of the comparison frequency, 5 or 6.25 kHz, which is obtained by the internal divider in IC101.

If a phase difference is found in the phase comparison between the reference frequency and VCO output frequency, the charge pump output (pin 5) of IC101 generates a pulse signal, which is converted to DC voltage by the PLL loop filter and input to the variable capacitance diode of the VCO unit for oscillation frequency control.

desired frequency. The frequency control voltage determined in the CPU (IC109) and PLL circuit is input to the variable capacitance diodes (D107 and D109). This changes the oscillation frequency, which is amplified by the VCO buffer (Q110) and output from the VCO unit.

DJ-S47 :A Colpitts oscillation circuit driven by Q108 directly oscillates the

desired frequency. The frequency control voltage determined in the CPU (IC109) and PLL circuit is input to the variable capacitance diodes (D109 and D110). This changes the oscillation frequency, which is amplified by the VCO buffer (Q110) and output from the VCO unit.

4) CPU and Peripheral Circuits

1. LCD Display Circuit

The CPU turns ON the LCD via segment and common terminals with

1/3 the duty and 1/3 the bias, at the frame frequency of 112.5Hz.

2. Display Lamp Circuit

When the LAMP key is pressed, "L" is output from pin 42 of CPU (IC109) to the bases of Q152 then turns to ON and "H" is output from emitter of Q152 to the bases of Q146 to light LEDs (D131, D132).

3. Reset and Backup Circuits

TWhen the Output Voltage from pin 3 of IC110 drops to 4.5 V or below, the output signal from the reset IC (IC104), which has been input to pin 33 of the CPU (IC109), changes from "H" to "L" level. The CPU will then be in the backup state.

4. S(Signal)Meter Circuit

The DC potential of pin 12 of IC103 is input to pin 1 of the CPU (IC109), converted from an analog to a digital signal, and displayed as the S-meter signal on the LCD.

5. Tone Encoder

6. DCS Encoder

7. CTCSS, DCS Decoder

8.Clock Shift

DJ-S17 :The CPU (IC109) is equipped with an internal tone encoder. The tone

signal (67.0 to 250.3Hz) is output from pin 9 of the CPU to the variable capacitance diode of the VCO and 21.25MHz reference oscillation (X101) of the PLL IC (IC101) for modulation.

DJ-S47 :The CPU (IC109) is equipped with an internal tone encoder. The tone

signal (67.0 to 250.3Hz) is output from pin 9 of the CPU to the variable capacitance diode of the VCO and 12.8MHz reference oscillation (X102) of the PLL IC (IC101) for modulation.

DJ-S17 :The CPU (IC109) is equipped with an internal DCS code encoder.

The DCS code ( 023 to 754 ) is output from pin 7 of the CPU to 21.25 MHz reference oscillation (X101) of the PLL IC (IC101) for modulation.

DJ-S47 :The CPU (IC109) is equipped with an internal DCS code encoder.

The DCS code ( 023 to 754 ) is output from pin 7 of the CPU to 12.8 MHz reference oscillation (X102) of the PLL IC (IC101) for modulation.

The AF signal from the pin 9 of IC103 is filtered by an active filter (IC108) to eliminate the voice range of the signal then amplified and input to the pin 4 of the CPU (IC109). The signal is compared in the CPU with the pre-selected CTCSS and DCS values and the squelch opens in case the value matches.

In case the selected frequency is disturbed by a CPU clock-noise, it may be eliminated by changing the CPU clock frequency. When the clock-shift is set, the pin 31 of the CPU (IC109) becomes Low turning ON the Q124. When Q124 becomes ON, X104’s oscillation frequency shifts approximately by 200ppm.

5) M38268MCA-076GP ( XA1121 )

CPU Terminal Connection

(TOP VIEW)

SEG12 - 4 — gâ j

SEG ii ^ 4 — 1771

SEG10 — [781

SEC*) - 4 — (79 j

SEGs — [bo] se g t - * — SEGe - 4 — (jttj SEGs -4 — (Mj SEG* — |B4~j SEGî - 4 — \K \

SEG2 - 4 — (w j

SEGi - 4 — (87 j SEGo - * — (œj

Vcc

Vref — [9Ôj

AVss — ►- [81] COM3 - 4 — (œj COM2 - 4

COM1 -4

COMo - 4 — (« j

Vl3

Vl2

Ca —►- ® ci —►- («r j

V li — ►

oooooooooooooooooooo

n 1 *, - LU LU LU LU LU LU LU LU LU LU LU LU LU LU LU LU LU LU LU LU

BâB8BSISigSSISI5i§SSiS«*I

COCO (/2 (/2 COQ-Q_Q_Q_Q_Q_Q_Q_Q_Q_Q_Q_Q_Q_Q_Q_Q_Q-Q_Q-

ttttttttttttm wm tm

----

------

►- (« [i

----

►- (97]

i l l i l

«-►- P14/SEGM

P1VSEG38 P1B P17 P2û

P2i I K P22 « * - P2s «-►- P24

P25 « * - P2a « * - P27

Vas —► Xout

•— Xn — XCOUT

•--- XCN

«— RESET

•— P7o/lNTo « ►- P7i «-►- P72 *-► P7j

P74 « ►- P7s « ►- P7a

No. Terminal Signal I/O

Description

1 P67/AN7 SMT I S-meter input 2 P66/AN6 SQL I Noise level input for squelch 3 P65/AN5 BAT I

Low battery detection input 4 P64/AN4 TIN I CTCSS tone input / DCS code input 5 P63/SCLK22/AN3 BP1 I Band plan 1 6 P62/SCLK21/AN2 BP2 I Band plan 2 7 P61/SOUT2/AN1 DCSW O DCS signal mute 8 P60/SIN2/AN0 FKEY I Function / Monitor Kev input 9 P57/ADT/DA2 CTOUT O CTCSS tone output / DCS tone output

10 P56/DA1 DTOUT O DTMF output 11 P55/CNTR1 SCL O Serial clock for EEPROM 12 P54/CNTR0 TBST I/O Tone burst output 13 P53/RTP1 BP4 I Band plan 4 14 P52/RTP0 MUTE I/O Microphone mute / Bank change input while trunking 15 P51/PWM3 CLK 0 Serial clock output for PLL, and trunking board

Serial data output for PLL, CTCSS / PLL unlock signal input /

16 P50/PWM0 DATA I/O

EVR control output

Trunking board detection ( when the unit is turned ON ) /

17 P47/SROY1 TRST I/O

Strobe signal to trunking board

18 P46/SCLK1 STBP 0 Strobe for PLL IC 19

P45/TXD

UTX 0 UART data transmission output 20 P44/RXD URX I UART data reception input 21 P43/OTOUT BEEP I/O Beep tone/Band plan 3 ( when the unit is turned on ) 22 P42/INT2 RE2 I 23 P41/INT1 RE1 I

Rotary encoder input

24 P40 CLO 0 CLONE ON/OFF output 25 P77 PTTK I PTT input 26 P76 CHG I

Battery charge ON/OFF output 27 P75 P5C 0 PLL power ON/OFF output 28 P74 T5C 0 TX power ON/OFF output 29 P73 R5C 0 RX power ON/OFF output 30 P72 AFP 0 AF AMP power ON/OFF output 31 P71 CLSFT 0

CLOCK frequency shift 32 P70/INTO BU I Backup siqnal detection input 33 RESET RESET I Reset input

34 Xcin 35 Xcout 36 Xin XIN 37 Xout XOUT 38 Vss GND

- -

Main clock input

Main clock output

CPU GND 39 P27 PSW I Power switch input 40 P26 SDA 0 Serial data for EEPROM 41 P25 C5C 0 C5V power ON/OFF output 42 P24 LAMP 0 Lamp ON/OFF 43 P23 KI0 I 44 P22 KI1 I 45 P21 KI2 I

Key matrix input 46 P20 KI3 I

47 P17 K03 0 48 P16 K02 0 49 P15/SEG39 KOI 0

Key matrix output 50 P14/SEG38 KOO 0

51 P13/SEG37 DA3 0 DA converter forTx output power 52 P12/SEG36 DA2 0 DA converter forTx output power 53 P11/SEG35 DA1 0 DA converter forTx output power 54 P10/SEG34 AFC/DA0 0 DA converter for Tx output power

Trunking TXDT control / Voice Scrambler Board detection 55 P07/SEG33 EXP I/O

(when the unit is turned on ) 56 P06/SEG32 SD/PO 0 Siqnal detection output / Tx power Hiqht or Low

No-

57 58 59 60 61 62 63 64 65

69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85

87 88 89 90 91 92 93 94 95 96 97 98 99

100

Terminal Signal I/O

Description

P05/SEG31 SEG31 P04/SEG30 SEG30 P03/SEG29 SEG29 P02/SEG28 SEG28 P01/SEG27 SEG27 P00/SEG26 SEG26 P37/SEG25 SEG25 P36/SEG24 SEG24 P35/SEG23 SEG23 P34/SEG22 SEG22 P33/SEG21 SEG21 P32/SEG20 SEG20 P31/SEG19 SEG19 P30/SEG18 SEG18

SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10

SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEGO

SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEGO

LCD segment signal

Vcc VDD CPU power terminal

Vref Vref AD converter power supply

Avss Avss AD converter GND COM3 COM3 LCD COM3 output COM2 COM2 LCD COM2 output COM1 COM1 LCD COM1 output COMO COMO

VL3 VL2

VL3 VL2 C2

LCD COMO output LCD power supply

C1 C1

VL1 VL1

LCD power supply

SEMICONDUCTOR DATA

1) NMJ2070MT1 ( XA0210 )

Low Voltage Power Amplifier Equivalent Circuit

Parameter Condition Symbol Min. Typ.

Supply voltage Idle current RL= Output voltage Input bias current IB

Output power

Distortion Voltage gain Input impedance

Equivalent input noise voltage

Power supply voltage rejection ratio

Power gain band width (-3dB)

THD=10%, f=1kHz

Po=0.4W, RL=4 , f=1kHz f=1kHz f=1kHz Rs=10k

f=100Hz, Cx=100 ¡i F

RL=8 , Po=250mW PB

V+=6V, RL=4 V+=4.5V, RL=4 V+=3V, RL=4 V+=2V, RL=4 V+=6V, RL=4 V+=4.5V, RL=4

A curve Vn1

B=22Hz to 22kHz Vn2

V+

THD -

ZlN

SVR 24 30

1.8

2.7

- 200

0.5 0.6

0.32

- 120

- 500

- 250

0.25

41 44

100

2.5

200

Max.

15 V

Unit

W mW mW mW mW

kHz

2) S24CS64A01 -J 8T1G ( XA1117 )

16K bits CMOS Serial EEPROM

Number

Remark See Dimensions for details of the package drawings.

AO Œ A1 Œ A2 □=

GND Œ

4 5

ID VCC ID WP

=□ SCL ID SDA

Name

1 2 A1 3 A2 Slave address input 4 5 SDA Serial data input / output 6 SCL Serial clock input

7 WP

A0 Slave address input

Slave address input

GND

VCC Power supply

Groudd

Write protection input

Connected to Vcc: Protection valid Connected to GND: Protection invalid

Function

3) M62429FP/CF0J ( XA1118 )

Electronic Volume

Vin1[T

Vout1 |~2~

g n d QT

DATA [4

o> ro

3 T1

8 ] V in 2

~7\ Vo ut2

6]Vcc1

J} CLOCK

V in2 Vout2 Vcc

4) LM2902PWR ( XA1106 )

Quad Operational Amplifiers

CLOCK

—®

------

LOGIC

CONTROL

DATA

14 13 12 11 10 9 8

L2902

* * *

* * * *

1 2 3 4 5 6 7

1. Output A

2. Inverting Input A

3. Non-inverting Input A

4. Vcc

5. Non-inverting Input B

5. Inverting Input B

7. Output B

8. Output C

9. Inverting Input C

10. Non-inverting Input C

11.GND

12. Non-inverting Input D

13. Inverting Input D

14. Output D

5) TA31136FN(EL) ( XA0404 )

Low Power FM IC

16 15 14 13 12 11 10 9

31136

* * *

1 2 3 4 5 6 7 8

1.0SC IN

2. OSC OUT

3. MIX OUT

4. Vcc

5. IF IN

6. DEC

7. FIL OUT

8. FIL IN

9.AF OUT

10. QUAD

11. IF OUT

12. RSSI

13. N-DET

14. N-REC

15. GND

16. MIC IN

6) S80845CLNB-B66-T2G ( XA1120 )

C-MOS Voltage Detector

4 3

____

1 2

Pin No. Pin name Pin description

1 OUT Voltage détection output pin 2 VDD Voltage input pin 3 4 VSS GND pin

*1. The NC pin is electrically open.

The NC pin can be connected to VDD orVSS.

NC*1 No connection

7) MB15E07SR ( XA1107 )

PLL Synthesizer

OSCIN

Data

Clock

16 15 14 13 12 11 10 9

E07SR

* * * *

* * *

1 2 3 4 5 6 7 8

Reference

Oscillator

Intermittent

mode control (power save)

1-bit

control latch

reference counter

Binary 14-bit

14-bit latch

19-bit shift register

7-bit latch 14-bit latch

Blnaly 7-bit

swallow counter

1.0SC IN

2. N. C.

3. Vp

4. Vcc

5. Do

6. GND

7. Xfin

8. fin

FC LDS CS

4-bit latch

Blnaly 11-bit

programmable

counter

9. CLOCK

10. Data 11 .LE

12. PS

13. N. C.

14. LD/fout

15. N. C.

16. N. C.

Phase

comparator

Lock

detector

LD/fr/fp

selector

Charge pump

LD/fout

Xfin

fin

VCC

GND

Prescaler

32/33 64/65

-SW

Parameter Symbol Condition Min. Typ. Max. Unit

Power supply voltage Vcc Power supply current Icc LPF supply voltage Local oscillator input level Local oscillator input frequency

Xin input level

Vfin

fin

Vxin

Xin input frequency Fxin

2500MHz

Vcc=Vp=3.75V

100MHz to 300MHz

300MHz to 2500MHz

(Vcc=2.7 to 5.0V, Ta=-40°C to +85oC)

2.7

Vcc

-6

-15 100 2500

3.75 5.0 V

8.0

5.5 V +2 +2

dBm MHz

0.5 Vcc Vp-p 3 40

MHz

8) XC6202P502MR ( XA1119 )

Voltage Regulator

Pin No.

1 2 VIN Supply Voltage Input 3

Pin name

VOUT Regulated Voltage Output

VSS Ground

1 2

Absolute Maximum Ratings

Parameter Symbol Rating Units

Input Voltage VIN 22 V

Output Current IOUT 500

Output Voltage

Power Dissipation Pd 150 mW

Operating Ambient Temperature Topr -40-+85 °C

Storage Temperature Tstg -55-+125 °C

VOUT

VSS-0.3-VIN+0.3

Function

9) Transistor, Diode and LED outline Drawings

Top View

10) LCD Connection ( EL0059 )

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