SERVICE MANUAL
PSR-740
PSR-640
001627
PK
PSR-740 19990901-160000
PSR-640 19990901-120000
CONTENTS
SPECIFICATIONS .............................................. 3/4
PANEL LAYOUT ...................................... 5
PSR-740 BLOCK DIAGRAM
PSR-640 BLOCK DIAGRAM
.... 6
.... 7
CIRCUIT BOARD LAYOUT ................. 8
DISASSEMBLY PROCEDURE ............................. 10
LSI PIN DESCRIPTION ............................... 14
IC BLOCK DIAGRAM .................................. 19
CIRCUIT BOARDS ........................................ 20
TEST PROGRAM ............................. 25/27
DATA INITIALIZATION .......................................... 29
ALERT MESSAGE LIST ................... 30/32
MIDI DATA FORMAT ................. 34
PSR-740 MIDI IMPLEMENTATION CHART ......................... 49
PSR-640 MIDI IMPLEMENTATION CHART ......................... 50
PARTS LIST
OVERALL CIRCUIT DIAGRAM
1.82K-9201 Printed in Japan ‘99.08
HAMAMATSU, JAPAN
PSR-640 BLOCK DIAGRAM
PSR-740/PSR-640
IC190
108
194
196
122
IC100
43
48
53
114
TR501-505 IC530
IC510
(1)
11 13 32
IC500
IC420
19 6
IC430
11
11
IC410
IC400
17
10 13 14 37 1 3 5 7 20 21 40
IC800
IC1
439
IRQFD
PC1
IC350
4
15
14
13
12
11
IC360
(2)
11 13 32
IC330IC300IC320IC310
13 14 31 3022 24 29
28CA1-8813472
IC
IC210 12 74,73
220
IC260
11 6 10
43,44,101
IC200
150
151
152
158
159
163
164
IC360
IC370
9
IC290
IC600
IC610
IC410
IC900
IC310
IC210,220
25
IC610
IC320
IC510
IC610
IC710
7
PSR-740/PSR-640
LSI PIN DESCRIPTION
SH-7043A (XW485100) CPU
SH-7043 (XW180100) CPU
PIN
NO.
NAME I/O FUNCTION
1 /WRHH/PA23 O HH write/Port A 73 D15 I/O
2 DACK0/PE14 O DMA transfer strobe/Port E 74 D14 I/O Data bus
3 /WRHL/PA22 O HL write/Port A 75 D13 I/O
4 /CASHH/PA21 I/O HH Column address strobe/Port A 76 D12 I/O
5 DACK1/PE15 O DMA transfer strobe/Port E 77 VCC I Power supply
6 VSS I Ground 78 D11 I/O Data bus
7 A0 O 79 VSS I Ground
8 A1 O 80 D10 I/O
9 A2 O Address bus 81 D9 I/O
10 A3 O 82 D8 I/O Data bus
11 A4 O 83 D7 I/O
12 VCC I Power supply 84 D6 I/O
13 A5 O Address bus 85 VCC I Power supply
14 VSS I Ground 86 D5 I/O Data bus
15 A6 O 87 VSS I Ground
16 A7 O 88 D4 I/O
17 A8 O 89 D3 I/O
18 A9 O 90 D2 I/O Data bus
19 A10 O 91 D1 I/O
20 A11 O Address bus 92 D0 I/O
21 A12 O 93 VSS I Ground
22 A13 O 94 XTAL I Crystal oscillator
23 A14 O 95 MD3 I Mode select
24 A15 O 96 EXTAL I Crystal oscillator
25 A16 O 97 MD2 I Mode select
26 VCC I Power supply 98 NMI - Non-maskable interrupt
27 A17 O Address bus 99 VCC/FW I Power supply
28 VSS I Ground 100 PA16 I/O Port A
29 /CASHL/PA20 I/O HL Column address strobe/Port A 101 PA17 I/O Port A
30 PA19 I/O Port A 102 MD1 I Mode select
31 /RAS/PB2 O Row address strobe/Port B 103 MD0 I Mode select
32 /CASL/PB3 O Column address strobe (low) /Port B 104 PLLVCC I PLL Power supply
33 PA18 I/O Port A 105 PLLCAP I PLL capacitor
34 /CASH/PB4 O Column address strobe (high) /Port B 106 PLLVSS I PLL Ground
35 VSS I Ground 107 CK/PA15 I/O Clock/Port A
36 RDWR/PB5 O DRAM read/write /Port B 108 /RES I Reset
37 A18 O 109 DREQ0/PE0 I/O DMA transfer request/Port E
38 A19 O Address bus 110 TIOC0B/PE1 I/O MTU input capture/output compare (ch 0)/Port E
39 A20 O 111 /DREQ1/PE2 I/O DMA transfer request/Port E
40 VCC I Power supply 112 VCC I Power supply
41 A21 O Address bus 113 PE3 I/O
42 VSS I Ground 114 PE4 I/O Port E
43 /RD O Read 115 PE5 I/O
44 /WDTOVF O Watch dog timer overflow 116 PE6 I/O
45 D31 I/O Data bus 117 VSS I Ground
46 D30 I/O Data bus 118 AN0 /PF0 I
47 /WRH O High write 119 AN1/ PF1 I
48 /WRL O Low write 120 AN2 /PF2 I
49 /CS1 O Chip select 121 AN3 /PF3 I Analog input/Port F
50 /CS0 O Chip select 122 AN4 /PF4 I
51 /IRQ3/PA9/TCLKD I/O Interrupt request/Port A/clock 123 AN5/PF5 I
52 /IRQ2/PA8/TCKLC I/O Interrupt request/Port A/clock 124 AVSS I Analog ground
53 /CS3 O Chip select 125 AN6/PF6 I Analog input/ Port F
54 /CS2 O Chip select 126 AN7/PF7 I Analog input /Port F
55 VSS I Ground 127 AVREF I Analog reference voltage
56 D29 I/O 128 AVCC I Analog power supply
57 D28 I/O 129 VSS I Ground
58 D27 I/O Data bus 130 RxDO I Receive data
59 D26 I/O 131 TxDO O Transmit data
60 D25 I/O 132 /IRQ0/SCK0 I Interrupt request/Serial clock
61 VSS I Ground 133 RxD1 I Receive data
62 D24 I/O Data bus 134 TxD1/PA4 I/O SCI/Port A
63 VCC I Power supply 135 VCC I Power supply
64 D23 I/O 136 /IRQ1/SCK1 I Interrupt request/Serial clock
65 D22 I/O 137 PE7 I/O
66 D21 I/O 138 PE8 I/O Port E
67 D20 I/O Data bus 139 PE9 I/O
68 D19 I/O 140 PE10 I/O
69 D18 I/O 141 VSS I Ground
70 D17 I/O 142 PE11 I/O
71 VSS I Ground 143 PE12 I/O Port E
72 D16 I/O Data bus 144 PE13 I/O
PIN
NO.
NAME I/O FUNCTION
14
HG73C205AFD (XU947C00) SWX00B TONE GENERATOR
1 ICN I Initial clear 85 CMA3 O Program address bus
2 RFCLKI I PLL Clock 86 CMA8 O Program address bus
3 TM2 I PLL Control 87 CMA2 O Program address bus
4 AVDD_PLL Power supply 88 CRD O read signal
5 AVSS_PLL Ground 89 CMA1 O Program address bus
6 MODE0 I SWX dual mode 90 CUB O high byte effective signal
7 VCC7 Power supply 91 VCC91 Power supply
8 GND8 Ground 92 GHND92 Ground
9 XIN I crystal oscillator 93 CS1 O CS signal
10 XOUT O crystal oscillator 94 CMA0 O Program address bus
11 MODE1 I SWX separate mode 95 CLB O low byte effective signal
12 TEST0 I TEST pin 96 CMA12 O
13 TESTON I TEST pin 97 CMA11 O
Program address bus
14 AN0-P40 I A/D converter 98 CMA10 O
15 AN1-P41 I A/D converter 99 CMA9 O
16 AN2-P42 I A/D converter 100 GND100 Ground
17 AN3-P43 I A/D converter 101 CWE O write signal
18 AVDD_AN Power supply 102 CMA16 O Program address bus
19 AVSS_AN Ground 103 CMA15 O Program address bus
20 TXD0 O for MIDI or TO-HOST 104 CMA14 O Program address bus
21 TXD1 O for MIDI 105 CMA13 O Program address bus
22 EXCLK I Crystal oscillator 106 CMD8 I/O Program memory Data bus
23 SMD11 I/O Wave memory data bus 107 CMD7 I/O Program memory Data bus
24 SMD4 I/O Wave memory data bus 108 CMD9 I/O Program memory Data bus
25 SMD3 I/O Wave memory data bus 109 CMD6 I/O Program memory Data bus
26 SMD12 I/O Wave memory data bus 110 CMD10 I/O Program memory Data bus
27 SMD10 I/O Wave memory data bus 111 CMD5 I/O Program memory Data bus
28 SMD5 I/O Wave memory data bus 112 CMD11 I/O Program memory Data bus
29 SMD2 I/O Wave memory data bus 113 CMD4 I/O Program memory Data bus
30 SMD13 I/O Wave memory data bus 114 CMD12 I/O Program memory Data bus
31 SMD9 I/O Wave memory data bus 115 CMD3 I/O Program memory Data bus
32 SMD6 I/O Wave memory data bus 116 CMD13 I/O Program memory Data bus
33 SMD1 I/O Wave memory data bus 117 CMD2 I/O Program memory Data bus
34 SMD14 I/O Wave memory data bus 118 CMD14 I/O Program memory Data bus
35 VCC35 Power supply 119 VCC119 Power supply
36 GND36 Ground 120 GND115 Ground
37 SMD8 I/O Wave memory data bus 121 CMD1 I/O Program memory Data bus
38 SMD7 I/O Wave memory data bus 122 CMD15 I/O Program memory Data bus
39 SMD0 I/O Wave memory data bus 123 CMD0 I/O Program memory Data bus
40 SMD15 I/O Wave memory data bus 124 CMA21 O Program address bus
41 SOE O read signal 125 PDT15 I/O
42 SWE O write signal 126 PDT14 I/O
43 SRAS O RAS signal 127 PDT13 I/O
44 SCAS O CAS signal 128 PDT12 I/O
45 REFRESH O REFRESH signal 129 PDT11 I/O
SWX access data bus
46 CS0 O CS signal 130 PDT10 I/O
47 SMA0 O Memory address bus 131 PDT9 I/O
48 SMA16 O Memory address bus 132 PDT8 I/O
49 VCC49 Power supply 133 VCC133 Power supply
50 GND50 Ground 134 GND134 Ground
51 SMA1 O Memory address bus 135 PDT7 I/O
52 SMA15 O Memory address bus 136 PDT6 I/O
53 SMA2 O Memory address bus 137 PDT5 I/O
54 SMA14 O Memory address bus 138 PDT4 I/O
SWX access data bus
55 SMA3 O Memory address bus 139 PDT3 I/O
56 SMA13 O Memory address bus 140 PDT2 I/O
57 SMA4 O Memory address bus 141 PDT1 I/O
58 SMA12 O Memory address bus 142 PDT0 I/O
59 SMA5 O Memory address bus 143 VCA143 Power supply
60 GND60 Ground 144 GND144 Ground
61 VCC61 Power supply 145 PAD2 I
62 SMA11 O Memory address bus 146 PAD1 I SWX access address bus
63 SMA6 O Memory address bus 147 PAD0 I
64 SMA10 O Memory address bus 148 VCC148 Power supply
65 SMA7 O Memory address bus 149 GND149 Ground
66 SMA9 O Memory address bus 150 PCS I Chip select
67 SMA17 O Memory address bus 151 PWR I write enable
68 SMA8 O Memory address bus 152 PRD I read enable
69 SMA18 O Memory address bus 153 RXD0 I for Midi or TO-HOST
70 SMA19 O Memory address bus 154 RXD1 I for Midi or Key scan
71 SMA20 O Memory address bus 155 SCLKI I EXT Clock
72 SMA21 O Memory address bus 156 ADIN I A/D converter
73 SMA22 O Memory address bus 157 ADLR O A/D converter LR clock
74 SMA23 O Memory address bus 158 DO0 O DAC
75 CMA20 O Program address bus 159 DO1 O DAC
76 CMA19 O Program address bus 160 SYSCLK O 1/2 clock
77 VCC77 Power supply 161 VCC161 Power supply
78 GND78 O Ground 162 GND162 Ground
79 CMA18 O Program address bus 163 WCLK O for DAC LR clock
80 CMA17 O Program address bus 164 QCLK O 1/12 clock
81 CMA5 O Program address bus 165 BCLK O IIS-DAC clock
82 CMA6 O Program address bus 166 SYI I Synch signal
83 CMA4 O Program address bus 167 IRQ0 I Interrupt request
84 CMA7 O Program address bus 168 NMI I Interrupt request
PIN
NAME I/O FUNCTION
NO.
PIN
NAME I/O FUNCTION
NO.
PSR-740/PSR-640
15
PSR-740/PSR-640
TC203C760HF-002 (XS725A00)
SWP30B (AWM Tone Generator coped with MEG) Standard Wave Processor
PIN
NAME
NO.
1
CA0
2
CA1
3
CA2
4
CA3
5
CA4
6
CA5
7
CA6
8
CA7
9
CA8
10
CA9
11
CA10
12
CA11
13
VSS
14
CD0
15
CD1
16
CD2
17
CD3
18
CD4
19
CD5
20
CD6
21
CD7
22
CD8
23
CD9
24
CD10
25
CD11
26
CD12
27
CD13
28
CD14
29
VDD
30
VSS
31
CD15
32
33
/WR
34
/RD
35
VDDS
36
SYSH0
37
SYSH1
38
SYSH2
39
SYSH3
40
SYSH4
41
SYSH5
42
SYSH6
43
SYSH7
44
KONO0
45
KONO1
46
KONO2
47
KONO3
48
VSS
49
SYSL0
50
SYSL1
51
SYSL2
52
SYSL3
53
SYSL4
54
SYSL5
55
SYSL6
56
SYSL7
57
KONI0
58
KONI1
59
VDDS
60
VSS
61
KONI2
62
KONI3
63
DAC0
64
DAC1
65
WCLK
66
MELO0
67
MELO1
68
MELO2
69
MELO3
70
MELO4
71
MELO5
72
MELO6
73
MELO7
74
VDDS
75
ADLR
76
MELI0
77
MELI1
78
MELI2
79
MELI3
80
MELI4
81
MELI5
82
MELI6
83
MELI7
84
VSS
85
/RCAS
86
RA8
87
RA7
88
RA6
89
VDD
90
VSS
91
RA5
92
RA4
93
RA3
94
RA2
95
RA1
96
RA0
97
/RRAS
98
/RWE
99
VSS
100
RD7
101
RD6
102
RD5
103
RD4
104
RD3
105
RD2
106
RD1
107
RD0
108
VSS
109
RD17
110
RD16
111
RD15
112
113
RD14
114
RD13
115
RD12
116
RD11
117
RD10
118
RD9
119
RD8
120
VDDS
Vss
/CS
I/O
I
I
I
I
I
I
I
I
I
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
O
O
O
O
O
O
O
O
O
O
O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
O
O
O
O
O
O
O
O
O
O
O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Address bus internal register
Data bus of internal register
Chip select
Write strobe
Read strobe
NSYS/LNSYS upper 16 bits
Key on data
NSYS input/LNSYS output lower 8 bits
Key on data (Power supply)
DAC output
DAC0/DAC1 word clock
MEL wave data output
ADC word clock
MEL wave data input
DRAM column address strobe
DRAM address bus
DRAM row address strobe
DARM write enable
DRAM data bus
FUNCTION
(Ground)
(Ground)
(Power supply)
(Ground)
(Power supply)
(Ground)
(Ground)
(Power supply)
(Ground)
(Power supply)
(Ground)
(Ground)
(Ground)
(Power supply)
PIN
NO.
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
NAME
VSS
HMD0
HMD1
HMD2
HMD3
HMD4
HMD5
HMD6
HMD7
HMD8
HMD9
HMD10
HMD11
HMD12
HMD13
HMD14
HMD15
VSS
HMA0
HMA1
HMA2
HMA3
HMA4
HMA5
HMA6
HMA7
HMA8
HMA9
HMA10
VSS
VDD
HMA11
HMA12
HMA13
HMA14
HMA15
HMA16
HMA17
HMA18
HMA19
HMA20
HMA21
HMA22
HMA23
HMA24
VSS
/MRAS
/MCAS
/MOE
/MWE
VSS
LMD0
LMD1
LMD2
LMD3
LMD4
LMD5
LMD6
LMD7
VDDS
VSS
LMD8
LMD9
LMD10
LMD11
LMD12
LMD13
LMD14
LMD15
VSS
LMA0
LMA1
LMA2
LMA3
LMA4
LMA5
LMA6
LMA7
LMA8
LMA9
LMA10
LMA11
VSS
LMA12
LMA13
LMA14
LMA15
LMA16
LMA17
VDD
VSS
LMA18
LMA19
LMA20
LMA21
LMA22
LMA23
LMA24
VSS
SYO
SYOD
QCLK
HCLK
CK256
SYSCLK
VDDS
SYI
MCLKI
MCLKO
VDD
XIN
XOUT
VSS
/IC
CHIP2
SLAVE
/TESTO
/ACI
DCTEST
VDDS
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
O
I
O
I
I
I
I
I
I
FUNCTION
(Ground)
Wave memory data bus (Upper data memory)
(Ground)
(Ground)
Wave memory address bus (Upper 16 bits)
RAS when DRAM(s) is connected to wave memory
CAS when DRAM(s) is connected to wave memory
Wave memory output enable
Wave memory write enable
Wave memory data bus (Lower data memory)
Wave memory address bus (Lower data memory)
Sync. signal for master clock
Sync. signal for HCLK/QCLK
1/12 master clock (64 Fs)
1/6 master clock (128 Fs)
1/3 master clock (256 Fs)
1/2 master clock (384 Fs)
Sync. clock
Master clock input
Master clock output
Crystal osc. input
Crystal osc. output
Initial clear
2 chips mode enable
Master/Slave select when 2 chips mode
Test pin
(Power supply)
(Ground)
(Ground)
(Power supply)
(Ground)
(Ground)
(Ground)
(Power supply)
(Ground)
(Ground)
(Power supply)
(Power supply)
(Ground)
(Power supply)
16