•One-time programmable (OTP) read-only memory
designed to store configuration bitstreams of Xilinx
FPGA devices
•Simple interface to the FPGA; requires only one user
I/O pin
•Cascadable for storing longer or multiple bitstreams
•Programmable reset polarity (active High or active
Low) for compatibility with different FPGA solutions
•XC17128E/EL, XC17256E/EL, XC1701, and XC1700L
series support fast configuration
•Low-power CMOS floating-gate process
Description
The XC1700 family of configuration PROMs provides an
easy-to-use, cost-effective method for storing large Xilinx
FPGA configuration bitstreams. See Figure 1 for a
simplified block diagram.
When the FPGA is in Master Serial mode, it generates a
configuration clock that drives the PROM. A short access
time after the rising clock edge, data appears on the PROM
DATA output pin that is connected to the FPGA D
FPGA generates the appropriate number of clock pulses to
complete the configuration. After configured, it disables the
pin. The
IN
Product Specification
•XC1700E series are available in 5V and 3.3V versions
•XC1700L series are available in 3.3V only
•Available in compact plastic packages: 8-pin SOIC,
•Programming support by leading programmer
manufacturers
•Design support using the Xilinx Alliance and
Foundation™ series software packages
•Guaranteed 20 year life data retention
•Lead-free (Pb-free) packaging available
PROM. When the FPGA is in Slave Serial mode, the PROM
and the FPGA must both be clocked by an incoming signal.
Multiple devices can be concatenated by using the CEO
output to drive the CE
input of the following device. The
clock inputs and the DATA outputs of all PROMs in this
chain are interconnected. All devices are compatible and
can be cascaded with other members of the family.
For device programming, either the Xilinx Alliance or
Foundation series development system compiles the FPGA
design file into a standard Hex format, which is then
transferred to most commercial PROM programmers.
PowerPC is a trademark of IBM, Inc. All other trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS027 (v3.4) July 9, 2007www.xilinx.comProduct Specification1
Figure 1: Simplified Block Diagram (Does not Show Programming Circuit)
XC1700E, XC1700EL, and XC1700L Series Configuration PROMs
R
Pin Description
DATA
Data output is in a high-impedance state when either CE or
OE
are inactive. During programming, the DATA pin is I/O.
Note that OE
active Low.
CLK
Each rising edge on the CLK input increments the internal
address counter, if both CE
RESET/OE
When High, this input holds the address counter reset and
puts the DATA output in a high-impedance state. The
polarity of this input pin is programmable as either
RESET/OE
document describes the pin as RESET/OE
opposite polarity is possible on all devices. When RESET is
active, the address counter is held at "0", and puts the DATA
output in a high-impedance state. The polarity of this input
is programmable. The default is active High RESET, but the
preferred option is active Low RESET
driven by the FPGAs INIT
The polarity of this pin is controlled in the programmer
interface. This input pin is easily inverted using the Xilinx
HW-130 Programmer. Third-party programmers have
different methods to invert this pin.
CE
When High, this pin disables the internal address counter,
puts the DATA output in a high-impedance state, and forces
the device into low-I
can be programmed to be either active High or
and OE are active.
or OE/RESET. To avoid confusion, this
, although the
, because it can be
pin.
standby mode.
CC
V
PP
Programming voltage. No overshoot above the specified
max voltage is permitted on this pin. For normal read
operation, this pin must be connected to V
. Failure to do
CC
so may lead to unpredictable, temperature-dependent
operation and severe problems in circuit debugging. Do not
leave V
floating!
PP
VCC and GND
Positive supply and ground pins.
PROM Pinouts
Pins not listed are "no connects."
"
8-pin
PDIP
(PD8/
)
PDG8
Pin Name
DATA112402
CLK234435
RESET/OE
(OE/RESET)
CE41081521
GND5111018, 4124, 3
CEO613142127
V
PP
V
CC
SOIC
(SO8/
SOG8)
VOIC
(VO8/
VOG8)
20-pin
SOIC
(SO20)
3861319
718173541
820203844
20-pin
PLCC
(PC20/
PCG20)
44-pin
VQFP
(VQ44)
44-pin
PLCC
(PC44)
Capacity
CEO
Chip Enable output, to be connected to the CE input of the next
PROM in the daisy chain. This output is Low when the CE
OE
inputs are both active AND the internal address counter
has been incremented beyond its Terminal Count (TC) value.
In other words: when the PROM has been read, CEO
CE
as long as OE is active. When OE goes inactive, CEO
stays High until the PROM is reset. Note that OE
can be
programmed to be either active High or active Low.
DS027 (v3.4) July 9, 2007www.xilinx.comProduct Specification2
and
follows
DevicesConfiguration Bits
XC1704L4,194,304
XC1702L2,097,152
XC1701/L1,048,576
XC17512L524,288
XC1736E36,288
XC1765E/EL65,536
XC17128E/EL131,072
XC17256E/EL262,144
R
Pinout Diagrams
6 5 4 3 2 14443424140
39
38
37
36
35
34
33
32
31
30
29
1819202122232425262728
7
8
9
10
11
12
13
14
15
16
17
PC44
Top View
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
RESET/OE
NCCENC
NC
GND
NC
NC
CEO
NC
NC
CLKNCGND
DATA(D0)NCVCC
NC
NC
VPP
NC
DS027_05_090602
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VQ44
Top View
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
RESET/OE
NCCENC
NC
GND
NC
NC
CEO
NC
NC
CLKNCGND
DATA(D0)NCVCC
NC
NC
VPP
NC
DS027_07_090602
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
4443424140393837363534
33
32
31
30
29
28
27
26
25
24
23
1213141516171819202122
DS027_08_110102
SO20
Top
View
VCC
NC
VPP
NC
NC
NC
NC
CEO
NC
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
DATA(D0)
NC
CLK
NC
NC
NC
NC
OE/RESET
NC
CE
XC1700E, XC1700EL, and XC1700L Series Configuration PROMs
DATA(D0)
CLK
OE/RESET
CE
1
PD8/PDG8
2
VO8/VOG8
SO8/SOG8
3
Top View
4
8
VCC
7
VPP
6
CEO
5
GND
DS027_06_060705
DS027 (v3.4) July 9, 2007www.xilinx.comProduct Specification3
CLK
NC
OE/RESET
NC
CE
NC
DATA(D0)NCVCC
321
4
5
PC20/PCG20
6
Top View
7
8
910111213
NC
GND
20
NCNCNC
NC
19
18
NC
17
VPP
16
NC
15
NC
14
CEO
DS027_09_060705
R
Xilinx FPGAs and Compatible PROMs
XC1700E, XC1700EL, and XC1700L Series Configuration PROMs
Device
XC4003E53,984XC17128E
XC4005E95,008XC17128E
XC4006E119,840XC17128E
XC4008E147,552XC17256E
XC4010E178,144 XC17256E
XC4013E247,968 XC17256E
XC4020E329,312XC1701
XC4025E422,176XC1701
XC4002XL61,100XC17128EL
XC4005XL151,960XC17256EL
XC4010XL283,424XC17512L
XC4013XL/XLA393,632XC17512L
XC4020XL/XLA521,880XC17512L
XC4028XL/XLA668,184XC1701L
XC4028EX668,184XC1701
XC4036EX/XL/XLA832,528XC1701L
XC4036EX832,528XC1701
XC4044XL/XLA1,014,928XC1701L
XC4052XL/XLA1,215,368XC1702L
XC4062XL/XLA1,433,864XC1702L
XC4085XL/XLA1,924,992XC1702L
XC40110XV2,686,136XC1704L
XC40150XV3,373,448XC1704L
XC40200XV4,551,056
XC40250XV5,433,888
XC520242,416XC1765E
XC520470,704XC17128E
XC5206106,288XC17128E
XC5210165,488XC17256E
XC5215237,744XC17256E
XCV50559,200XC1701L
XCV100781,216XC1701L
XCV1501,040,096XC1701L
XCV2001,335,840XC1702L
XCV3001,751,808XC1702L
XCV4002,546,048XC1704L
XCV6003,607,968XC1704L
XCV8004,715,616
XCV10006,127,744
XCV50E630,048XC1701L
Configuration
Bits
PROM
XC1704L +
XC17512L
XC1704L+
XC1702L
XC1704L +
XC1701L
XC1704L +
XC1702L
(1)
(1)
Device
XCV100E863,840XC1701L
XCV200E1,442,016XC1702L
XCV300E1,875,648XC1702L
XCV400E2,693,440XC1704L
XCV405E3,340,400XC1704L
XCV600E3,961,632XC1704L
XCV812E6,519,6482 of XC1704L
XCV1000E6,587,5202 of XC1704L
XCV1600E8,308,9922 of XC1704L
XCV2000E10,159,6483 of XC1704L
XCV2600E12,922,3364 of XC1704L
XCV3200E16,283,7124 of XC1704L
Notes:
1.The suggested PROM is determined by compatibility with the
higher configuration frequency of the Xilinx FPGA CCLK.
Designers using the default slow configuration frequency (CCLK)
can use the XC1765E or XC1765EL for the noted FPGA devices.
Configuration
Bits
PROM
Controlling PROMs
Connecting the FPGA device with the PROM:
•The DATA output(s) of the of the PROM(s) drives the
D
input of the lead FPGA device.
IN
•The Master FPGA CCLK output drives the CLK input(s)
of the PROM(s).
•The CEO
next PROM in a daisy chain (if any).
•The RESET
the INIT
connection assures that the PROM address counter is
reset before the start of any (re)configuration, even
when a reconfiguration is initiated by a V
Other methods—such as driving RESET
or system reset—assume the PROM internal
power-on-reset is always in step with the FPGA’s
internal power-on-reset. This may not be a safe
assumption.
•The PROM CE
or DONE pins. Using LDC
on the D
•The CE
the DONE output of the lead FPGA device, provided
that DONE is not permanently grounded. Otherwise,
LDC
unconditionally High during user operation. CE
also be permanently tied Low, but this keeps the DATA
output active and causes an unnecessary supply
current of 10 mA maximum.
output of a PROM drives the CE input of the
/OE input of all PROMs is best driven by
output of the lead FPGA device. This
glitch.
CC
/OE from LDC
input can be driven from either the LDC
avoids potential contention
pin.
IN
input of the lead (or only) PROM is driven by
can be used to drive CE, but must then be
can
DS027 (v3.4) July 9, 2007www.xilinx.com
Product Specification4
XC1700E, XC1700EL, and XC1700L Series Configuration PROMs
R
FPGA Master Serial Mode Summary
The I/O and logic functions of the Configurable Logic Block
(CLB) and their associated interconnections are established
by a configuration program. The program is loaded either
automatically upon power up, or on command, depending on
the state of the three FPGA mode pins. In Master Serial
mode, the FPGA automatically loads the configuration
program from an external memory. The Xilinx PROMs have
been designed for compatibility with the Master Serial mode.
Upon power-up or reconfiguration, an FPGA enters the Master
Serial mode whenever all three of the FPGA mode-select pins
are Low (M0=0, M1=0, M2=0). Data is read from the PROM
sequentially on a single data line. Synchronization is provided
by the rising edge of the temporary signal CCLK, which is
generated during configuration.
Master Serial Mode provides a simple configuration interface.
Only a serial data line and two control lines are required to
configure an FPGA. Data from the PROM is read sequentially,
accessed via the internal address and bit counters which are
incremented on every valid rising edge of CCLK.
If the user-programmable, dual-function D
FPGA is used only for configuration, it must still be held at a
defined level during normal operation. The Xilinx FPGA
families take care of this automatically with an on-chip
default pull-up resistor.
pin on the
IN
PROM does not reset its address counter, since it never
saw a High level on its OE
input. The new configuration,
therefore, reads the remaining data in the PROM and
interprets it as preamble, length count etc. Since the FPGA
is the master, it issues the necessary number of CCLK
pulses, up to 16 million (2
24
) and DONE goes High.
However, the FPGA configuration is then completely wrong,
with potential contentions inside the FPGA and on its output
pins. This method must, therefore, never be used when
there is any chance of external reset during configuration.
Cascading Configuration PROMs
For multiple FPGAs configured as a daisy-chain, or for
future FPGAs requiring larger configuration memories,
cascaded PROMs provide additional memory. After the last
bit from the first PROM is read, the next clock signal to the
PROM asserts its CEO
line. The second PROM recognizes the Low level on its CE
input and enables its DATA output. See Figure 2, page 6.
After configuration is complete, the address counters of all
cascaded PROMs are reset if the FPGA RESET
assuming the PROM reset polarity option has been inverted.
To reprogram the FPGA with another program, the DONE
line goes Low and configuration begins where the address
counters had stopped. In this case, avoid contention
between DATA and the configured I/O use of D
output Low and disables its DATA
pin goes Low,
.
IN
Programming the FPGA With Counters
Unchanged Upon Completion
When multiple FPGA-configurations for a single FPGA are
stored in a PROM, the OE
power-up, the internal address counters are reset and
configuration begins with the first program stored in
memory. Since the OE
counters are left unchanged after configuration is complete.
Therefore, to reprogram the FPGA with another program,
the DONE line is pulled Low and configuration begins at the
last value of the address counters.
This method fails if a user applies RESET
configuration process. The FPGA aborts the configuration
and then restarts a new configuration, as intended, but the
Tab l e 1 : Truth Table for XC1700 Control Inputs
Control Inputs
RESETCEDATACEOI
InactiveLow
ActiveLowHeld resetHigh-ZHighActive
InactiveHighNot changingHigh-Z
ActiveHighHeld reset High-Z
pin should be tied Low. Upon
pin is held Low, the address
during the FPGA
Internal Address
If address < TC
If address > TC
Standby Mode
The PROM enters a low-power standby mode whenever CE
is asserted High. The output remains in a high-impedance
state regardless of the state of the OE
Programming
The devices can be programmed on programmers supplied
by Xilinx or qualified third-party vendors. The user must
ensure that the appropriate programming algorithm and the
latest version of the programmer software are used. The
wrong choice can permanently damage the device.
Outputs
(1)
: increment
(2)
: don’t change
Active
High-Z
(3)
(3)
input.
CC
High
Low
HighStandby
HighStandby
Active
Reduced
Notes:
1.The XC1700 RESET input has programmable polarity.
DS027 (v3.4) July 9, 2007www.xilinx.comProduct Specification5
to meet I
CC
standby current.
CCS
XC1700E, XC1700EL, and XC1700L Series Configuration PROMs
R
D
IN
D
OUT
CCLK
INIT
DONE
PROM
DATA
CLK
CECE
FPGA
(Low Resets the Address Pointer)
V
CC
V
CC
V
CC
OPTIONAL
Daisy-chained
FPGAs with
Different
configurations
OPTIONAL
Slave FPGAs
with Identical
Configurations
RESETRESET
DS027_02_111606
CCLK
(Output)
D
IN
D
OUT
(Output)
OE/RESET
MODES
(1)
V
PP
Cascaded
Serial
Memory
DATA
CLK
CEO
OE/RESET
3.3V
4.7KΩ
Notes:
1. For mode pin connections, refer to the appropriate FPGA data sheet.
2. The one-time-programmable PROM supports automatic loading of configuration programs.
3. Multiple devices can be cascaded to support additional FPGAs.
4. An early DONE inhibits the PROM data output one CCLK cycle before the FPGA I/Osbecome active.
Figure 2: Master Serial Mode.
DS027 (v3.4) July 9, 2007www.xilinx.com
Product Specification6
XC1700E, XC1700EL, and XC1700L Series Configuration PROMs
R
XC1701, XC1736E, XC1765E, XC17128E and XC17256E
Absolute Maximum Ratings
SymbolDescriptionConditionsUnits
V
CC
V
PP
V
IN
V
TS
T
STG
Notes:
1.Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied.
Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
Operating Conditions (5V Supply)
SymbolDescriptionMinMaxUnits
(1)
V
CC
Supply voltage relative to GND–0.5 to +7.0V
Supply voltage relative to GND–0.5 to +12.5V
Input voltage relative to GND–0.5 to VCC +0.5V
Voltage applied to High-Z output–0.5 to VCC +0.5V
Storage temperature (ambient)–65 to +150° C
Supply voltage relative to GND (TA = 0° C to +70° C)Commercial4.7505.25V
Supply voltage relative to GND (TA = –40° C to +85° C)Industrial4.505.50V
Notes:
1.During normal read operation VPP must be connect to V
CC.
DC Characteristics Over Operating Condition
SymbolDescriptionMinMaxUnits
C
Notes:
1.I
CCS
V
IH
V
IL
V
OH
V
OL
V
OH
V
OL
I
CCA
I
CCA
I
CCS
I
CCS
I
L
C
IN
OUT
standby current is specified for DATA pin that is pulled to VCC or GND.
High-level input voltage2V
CC
Low-level input voltage00.8V
High-level output voltage (IOH = –4 mA)Commercial3.86–V
Low-level output voltage (IOL = +4 mA)–0.32V
High-level output voltage (IOH = –4 mA)Industrial3.76–V
Low-level output voltage (IOL = +4 mA)–0.37V
Supply current, active mode at maximum frequency
–10mA
(XC1736E, XC1765E, XC17128E, and XC17256E)
Supply current, active mode at maximum frequency
–20mA
(XC1701)
Supply current, standby mode
–50
(1)
(XC1736E, XC1765E, XC17128E, and XC17256E)
Supply current, standby mode
–100
(1)
(XC1701)
Input or output leakage current–1010μA
Input capacitance (VIN = GND, f = 1.0 MHz)–10pF
Output capacitance (VIN = GND, f = 1.0 MHz)–10pF
V
μA
μA
DS027 (v3.4) July 9, 2007www.xilinx.com
Product Specification7
XC1700E, XC1700EL, and XC1700L Series Configuration PROMs
R
XC1704L, XC1702L, XC1701L, XC17512L, XC1765EL, XC17128EL and XC17256EL
Absolute Maximum Ratings
SymbolDescriptionConditionsUnits
V
CC
V
PP
V
IN
V
TS
T
STG
Notes:
1.Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied.
Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
Operating Conditions (3V Supply)
SymbolDescriptionMinMaxUnits
(1)
V
CC
Supply voltage relative to GND–0.5 to +7.0V
Supply voltage relative to GND–0.5 to +12.5V
Input voltage relative to GND–0.5 to VCC +0.5V
Voltage applied to High-Z output–0.5 to VCC +0.5V
Storage temperature (ambient)–65 to +150° C
Supply voltage relative to GND (TA = 0° C to +70° C)Commercial3.03.6V
Supply voltage relative to GND (TA = –40° C to +85° C)Industrial3.03.6V
Notes:
1.During normal read operation VPP must be connect to V
CC.
DC Characteristics Over Operating Condition
SymbolDescriptionMinMaxUnits
C
Notes:
1.I
CCS
V
IH
V
IL
V
OH
V
OL
I
CCA
I
CCA
I
CCS
I
CCS
I
L
C
IN
OUT
standby current is specified for DATA pin that is pulled to VCC or GND.
High-level input voltage2V
CC
Low-level input voltage00.8V
High-level output voltage (IOH = –3 mA)2.4–V
Low-level output voltage (IOL = +3 mA)–0.4V
Supply current, active mode (at maximum frequency) (XC1700L)–10mA
Supply current, active mode (at maximum frequency)
(XC1765EL, XC17128EL, XC17256EL)
Due to the small size of the commercial serial PROM packages, the complete ordering part number cannot be marked on
the package. The XC prefix is deleted and the package code is simplified. Device marking is as follows:
Revision History
The following table shows the revision history for this document.
.
DateVersionRevision
7/14/981.1Major revisions to include the XC1704L, XC1702L, and the XQ1701L devices, packages and operating
9/8/982.0Revised the marking information for the VQ44. Updated "DC Characteristics Over Operating Condition,"
12/18/982.1Added Virtex FPGAs to "Xilinx FPGAs and Compatible PROMs," page 4. Added the PC44 package for
1/27/992.2Changed Military I
7/8/992.3Changed I
3/30/003.0Combined data sheets XC1700E and XC1700L. Added DS027, removed Military Specs. Added Virtex-E
07/05/003.1Added 4.7K resistor to Figure 2, updated format.
09/07/043.2• Updated "Xilinx FPGAs and Compatible PROMs," page 4 and "Absolute Maximum Ratings," page 7.
conditions. Also revised the timing specifications under "AC Characteristics Over Operating Condition,"
page 9.
page 7. Added references to the XC4000XLA and XC4000XV families in "Xilinx FPGAs and Compatible
PROMs," page 4 and Figure 2, page 6.
the XC1702L and XC1704L products.
.
CCS
standby on XC1702/XC1704 from 50 μA to 300 μA.
CCS
and EM references.
Added "Pinout Diagrams," page 3.
• Added footnote to table in "AC Characteristics Over Operating Condition When Cascading," page 10,
defining T
when cascading, and redrew associated timing diagram.
CCE
DS027 (v3.4) July 9, 2007www.xilinx.com
Product Specification12
XC1700E, XC1700EL, and XC1700L Series Configuration PROMs
R
06/13/053.3• Changed pinout diagrams to include Pb-free packages on "Pinout Diagrams," page 3.
• Deleted T
• Added VOG8 and PCG20 to "Ordering Information," page 11. Added XC1765ELVOG8C and
XC17256EPCG20 to "Valid Ordering Combinations," page 11. Added new packages types under
"Marking Information," page 12.
07/09/073.4• Added Pb-free packages to "PROM Pinouts," page 2.
• Note added to Table 1, page 5.
• Under "XC1701, XC1736E, XC1765E, XC17128E and XC17256E", note added to "DC
Characteristics Over Operating Condition," page 7 and corrected XC1701 I
• Under "XC1704L, XC1702L, XC1701L, XC17512L, XC1765EL, XC17128EL and XC17256EL", note
added to "DC Characteristics Over Operating Condition," page 8.
• Added SOG package to "Ordering Information," page 11.
• Added Pb-free order codes to "Valid Ordering Combinations," page 11.
• Added package type E to "Marking Information," page 12.
from the under "Absolute Maximum Ratings," page 7.
SOL
CCA
value.
DS027 (v3.4) July 9, 2007www.xilinx.com
Product Specification13
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