Xilinx AC701 Evaluation Board for the Artix-7 FPGA User Manual

AC701 Evaluation Board
for the Artix-7 FPGA

User Guide

UG952 (v1.4) August 6, 2019

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AUTOMOTIVE PRODUCTS (IDENTIFIED AS “XA” IN THE PART NUMBER) ARE NOT WARRANTED FOR USE IN THE DEPLOYMENT OF AIRBAGS
OR FOR USE IN APPLICATIONS THAT AFFECT CONTROL OF A VEHICLE (“SAFETY APPLICATION”) UNLESS THERE IS A SAFETY CONCEPT OR
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TO USING OR DISTRIBUTING ANY SYSTEMS THAT INCORPORATE PRODUCTS, THOROUGHLY TEST SUCH SYSTEMS FOR SAFETY PURPOSES.
USE OF PRODUCTS IN A SAFETY APPLICATION WITHOUT A SAFETY DESIGN IS FULLY AT THE RISK OF CUSTOMER, SUBJECT ONLY TO
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included herein are trademarks of Xilinx in the United States and other countries. PCI, PCI Express, PCIe, and PCI-X are trademarks of
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Revision History

The following table shows the revision history for this document.

Date Version Revision

10/23/2012 1.0 Initial Xilinx release.

01/30/2013 1.1 Updated photograph in Figure 1-2, page 11 to revision 1.0 of the AC701 board. Revised Figure 1-3.

Revised last paragraph under DDR3 Memory Module, page 15, fourth paragraph under USB JTAG

Module, page 23, third paragraph under GTP Transceivers, page 35, first paragraph under U3 IN0: 125
MHz Clock Generator, page 33, first, second and third paragraphs under U3/U4 IN2: FMC HPC GBT
Clocks, page 35, fourth paragraph under PCI Express Edge Connector, page 38, and the first paragraph

under SFP/SFP+ Connector, page 39. Revised third and fourth rows in Table 1-13, page 40 and the fifth
row in Table 1-14, page 40. Revised second paragraph and added fourth paragraph under LCD Character

Display, page 47. Revised first paragraph under I2C Bus Switch, page 49. Added Figure 1-32, page 53,
Figure 1-34, page 53 and Figure 1-35, page 54. Revised Figure 1-41, page 57. Added section AC701
Board Power System, page 67 and section XADC Power System Measurement, page 72. Added third

paragraph under Power Management, page 62. Revised Figure 1-49, page 78. Revised Figure A-2,

page 82. Updated the Xilinx Design Constraints in Appendix C. Added Appendix F, Regulatory and
Compliance Information.

08/28/2013 1.2 Added Figure 1-10. Revised Figure 1-2, Figure 1-49, and Figure 1-50.

AC701 Evaluation Board www.xilinx.com UG952 (v1.4) August 6, 2019

Date Version Revision

04/07/2015 1.3 Replaced the board photo in Figure 1-2 with the Rev 2.0 board. Added callout row to GTP transceiver

clock multiplexers in Table 1-1. Replaced Table 1-4, Table 1-5, Table 1-7, and Table 1-8. Replaced I/O
banks 32, 33, and 34 with banks 33, 34, and 35 in DDR3 Memory Module, page 15. Updated

Figure 1-10. Major revision of GTP Transceiver Clock Multiplexer section, starting on page 28. Added

note to Table 1-13. Replaced Ta bl e 1-16, Table 1-19, Table 1-21, Table 1-23, and Table 1-26. Updated

Figure 1-42. Voltage regulators changed in section AC701 Board Power System, page 67. Updated

device types and footnotes in Table 1-27 to reflect device changes. Updated Figure 1-44 and Figure 1-45.
Changed Texas Instruments parts numbers to LMZ31710 and LMZ31704 in [Ref 22]. Changed
XADC_GPIO_3, 2, 1, 0 description in Table 1-35. Added Figure A-3 to show board components called
out in Table A-3. Updated the Artix-7 FPGA AC701 Declaration of Conformity link in Appendix F,

Regulatory and Compliance Information.

08/06/2019 1.4 Updated DDR3 Memory Module section. Changed Appendix C, Xilinx Design Constraints. Updated the

Appendix F, Regulatory and Compliance Information.

UG952 (v1.4) August 6, 2019 www.xilinx.com AC701 Evaluation Board

AC701 Evaluation Board www.xilinx.com UG952 (v1.4) August 6, 2019

Table of Contents

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Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Chapter 1: AC701 Evaluation Board Features

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Additional Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

AC701 Board Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Electrostatic Discharge Caution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Feature Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Artix-7 FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

DDR3 Memory Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Quad SPI Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

SPI Flash Memory External Programming Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

SD Card Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

USB JTAG Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

GTP Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

PCI Express Edge Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

SFP/SFP+ Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

10/100/1000 Mb/s Tri-Speed Ethernet PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Ethernet PHY User LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

USB-to-UART Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

HDMI Video Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

LCD Character Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

I2C Bus Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

AC701 Board LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

User I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

FPGA Mezzanine Card Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

AC701 Board Power System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

XADC Power System Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

XADC Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

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Appendix A: Default Switch and Jumper Settings

User GPIO DIP Switch SW2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Configuration DIP Switch SW1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Default Jumper Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Appendix B: VITA 57.1 FMC Connector Pinouts

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Appendix C: Xilinx Design Constraints

Appendix D: Board Setup

Installing the AC701 Board in a PC Chassis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Appendix E: Board Specifications

Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Environmental . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Humidity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Operating Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Appendix F: Regulatory and Compliance Information

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

CE Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

CE Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Electromagnetic Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Appendix G: Additional Resources

Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Solution Centers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

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AC701 Evaluation Board Features

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Overview

The AC701 evaluation board for the Artix®-7 FPGA provides a hardware environment for
developing and evaluating designs targeting the Artix-7 XC7A200T-2FBG676C FPGA. The AC701
board provides features common to many embedded processing systems, including a DDR3
SODIMM memory, an 4-lane PCI Express® interface, a tri-mode Ethernet PHY, general purpose I/
O, and a UART interface. Other features can be added by using an FPGA mezzanine card (FMC)
attached to the VITA-57 FPGA mezzanine connector provided on the board. A high pin count
(HPC) FMC connector is provided. See
details for each feature are described in Feature Descriptions.

Additional Information

See Appendix G, Additional Resources for references to documents, files and resources relevant to
the AC701 board.

AC701 Board Features for a complete list of features. The

Chapter 1

AC701 Board Features

• Artix-7 XC7A200T-2FBG676C FPGA

•1 GB DDR3 memory SODIMM

• 256 Mb quad serial peripheral interface (quad SPI) flash memory

• Secure Digital (SD) connector

• USB JTAG through Digilent module

• Clock generation

• Fixed 200 MHz LVDS oscillator

• I2C programmable LVDS oscillator

• SMA connectors

• SMA connectors for GTP transceiver clocking

• GTP transceivers

• FMC HPC connector (two GTP transceivers)

• SMA connectors (one pair each for TX, RX and REFCLK)

• PCI Express (four lanes)

• Small form-factor pluggable plus (SFP+) connector

• Ethernet PHY RGMII interface (RJ-45 connector)

• PCI Express endpoint connectivity

• Gen1 4-lane (x4)

AC701 Evaluation Board www.xilinx.com 7

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Chapter 1: AC701 Evaluation Board Features

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• Gen2 4-lane (x4)

• SFP+ connector

• 10/100/1,000 tri-speed Ethernet PHY

• USB-to-UART bridge

• High-Definition Multimedia Interface (HDMI™) technology codec

• I2C bus

•I2C MUX

• I2C EEPROM (1 KB)

• User I2C programmable LVDS oscillator

• DDR3 SODIMM socket

• HDMI codec

• FMC HPC connector

• SFP+ connector

• I2C programmable jitter-attenuating precision clock multiplier

•Status LEDs

• Ethernet status

• Power good

•FPGA INIT

• FPGA DONE

• User I/O

• User LEDs (four GPIO)

• User pushbuttons (five directional)

• CPU reset pushbutton

• User DIP switch (4-pole GPIO)

• User SMA GPIO connectors (one pair)

• LCD character display (16 characters x 2 lines)

• • Switches

• Power on/off slide switch

• FPGA_PROG_B pushbutton switch

• Configuration mode DIP switch

• VITA 57.1 FMC HPC connector

• Power management

• PMBus voltage and current monitoring through TI power controller

• XADC header

• Configuration options

• Quad SPI flash memory

• USB JTAG configuration port

• Platform cable header JTAG configuration port

8 www.xilinx.com AC701 Evaluation Board

UG952 (v1.4) August 6, 2019

The AC701 board block diagram is shown in Figure 1-1. The AC701 board schematics are

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available for download from the AC701 Evaluation Kit product page.

Electrostatic Discharge Caution

Caution! ESD can damage electronic components when they are improperly handled, and can

result in total or intermittent failures. Always follow ESD-prevention procedures when removing
and replacing components.

To prevent ESD damage:

• Use an ESD wrist or ankle strap and ensure that it makes skin contact. Connect the equipment
end of the strap to an unpainted metal surface on the chassis.

• Avoid touching the adapter against your clothing. The wrist strap protects components from
ESD on the body only.

• Handle the adapter by its bracket or edges only. Avoid touching the printed circuit board or the
connectors.

• Put the adapter down only on an antistatic surface such as the bag supplied in your kit.

• If you are returning the adapter to Xilinx Product Support, place it back in its antistatic bag
immediately.

• If a wrist strap is not available, ground yourself by touching the metal chassis before handling
the adapter or any other part of the computer/server.

Electrostatic Discharge Caution

AC701 Evaluation Board www.xilinx.com 9

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Chapter 1: AC701 Evaluation Board Features

UG952_c1_01_101512

Artix-7 FPGA

XC7A200T-2FBG676C

128 Mb Quad SPI

Flash Memory

SD Card
Interface

4-lane PCI Express

Edge Connector

LCD Display

(2 line x 16 characters)

1 KB EEPROM (I2C)

I2C Bus Switch

XADC Header

User Switches,

Buttons, and LEDs

HDMI Video

Interface

Differential Clock

GTP SMA Clock

1 GB DDR3 Memory

(SODIMM)

FMC Connector

(HPC)

10/100/1000 Ethernet

Interface

DIP Switch SW1

Config

USB-to-UART Bridge

JTAG Interface

micro-B USB Connector

SFP+ Single Cage

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X-Ref Target - Figure 1-1

Figure 1-1: AC701 Board Block Diagram

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Feature Descriptions

UG952_c1_02_022715

18

29

30

31

13

5

14

1

6

7

30

11

11

8

9

32

10

3

16

17

12

15

2

25

00

Square callout references a component
on the back side of the board

Round callout references a component
on the front side of the board

00

4

26

23

21

28

22

24

19

27

33

34

35

20

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Figure 1-2 shows the AC701 board. Each numbered feature that is referenced in Figure 1-2 is

described in the sections that follow.

Note: The image in Figure 1-2 is for reference only and might not reflect the current revision of the

board.

X-Ref Target - Figure 1-2

Feature Descriptions

Table 1-1: AC701 Board Component Descriptions

Callout

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Figure 1-2: AC701 Board Components (Rev. 2.0)

Reference

Designator

1 U1 Artix-7 FPGA Xilinx XC7A200T-2FBG676C

2 J1 DDR3 SODIMM socket with memory Micron MT8JT12864HZ-1G6G1 10

3 U7 Quad SPI flash memory Micron N25Q256A13ESF40G 4

Component Description Notes

Schematic

0381502

Page Number

4 U29 SD card interface connector Molex 67840-8001 14

5 U26 USB-JTAG module

6 U51 System clock source (back side of board) SiTime SIT9102AI-243N25E200.0000 3

7 U34

8 J31, J32 SMA user clock input Rosenberger 32K10K-400L5 3

Programmable user clock source

MHz-810 MHz (back side of board)

10

Digilent USB JTAG module (with
micro-B receptacle)

Silicon Labs SI570BAB000544DG
(default 156.250

MHz)

4

3

Chapter 1: AC701 Evaluation Board Features

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Table 1-1: AC701 Board Component Descriptions (Cont’d)

Callout

10 U24 Jitter attenuated clock (back side of board) Silicon Labs SI5324-C-GM 16

12 P1 PCI Express® edge connector 4-lane card edge connector 28

13 P3 SFP/SFP+ connector Molex 74441-0010 20

14 U12 10/100/1000 tri-speed Ethernet PHY Marvell 88E1116RA0-NNC1C000 15

15 U2 GTP transceiver clock generator 125 MHz ICS ICS84402IAGI-01LF 3

16 J17, U44

17 P2, U48 HDMI video connector and device

18 J23 LCD character display connector 2 x 7 0.1 in male pin header 14

19 U52 I2C bus switch (back side of board) TI PCA9548ARGER 6

20 DS11–DS13 Ethernet PHY status LEDs, green Lumex SML-LX0603GW 15

21 DS2–DS5 User GPIO LEDs, green Lumex SML-LX0603GW 21

Reference

Designator

9 J25, J26 SMA GTP reference clock input Rosenberger 32K10K-400L5 3

11 U1 GTP transceivers Embedded within FPGA U1 30

USB-to-UART bridge (back side of board)
and mini-B receptacle (front side of board)

Component Description Notes

Page Number

Silicon Labs CP2103GM 5

Molex 500254-1927, Analog Devices
ADV7511KSTZ-P

Schematic

0381502

19, 18

22 SW3 – SW7 User pushbuttons E-switch E-Switch TL3301EF100QG 21

23 SW2 GPIO DIP switch, 4-pole C&K SDA04H1SBD 21

24 SW10 User rotary switch Panasonic EVQ-WK4001 21

25 J33, J34 SMA user GPIO Rosenberger 32K10K-400L5 3

26 SW15 Power on/off slide switch C&K 1201M2S3AQE2 38

27 SW9

28 SW1 Configuration mode DIP switch, 3-pole C&K SDA03H1SBD 7

29 J30 FMC HPC connector Samtec ASP_134486_01 24–27

U8, U9,

30

31 J19 XADC header 2X10 0.1 inch male header 31

32

33 J2 PMBus connector Assmann AWHW10G-0202-T-R 38

34 J49 6 pin Molex mini-fit Jr. connector for 12V Molex 39-30-1060 38

U49,

U53-U60

J44, J45,

J46, J47

FPGA_PROG_B pushbutton switch
(active-Low)

Power management (voltage regulators front
side of board, controllers back side of board)

MGT transmit, receive SMA pairs Rosenberger 32K10K-400L5 3

E-Switch TL3301EF100QG 7

TI UCD90120ARGC controllers in
conjunction with various regulators

39–50

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Table 1-1: AC701 Board Component Descriptions (Cont’d)

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Feature Descriptions

Callout

Reference

Designator

Component Description Notes

Page Number

35 U3, U4 GTP transceiver clock multiplexers Micrel SY89544UMG 30

Notes:

1. Jumper header locations are identified in Default Jumper Settings in Appendix A.

Artix-7 FPGA

[Figure 1-2, callout 1]

The AC701 board is populated with the Artix-7 XC7A200T-2FBG676C FPGA.

For further information on Artix-7 FPGAs, see 7 Series FPGAs Overview (DS180) [Ref 2].

FPGA Configuration

The AC701 board supports two of the five 7 series FPGA configuration modes:

• Master SPI flash memory using the onboard Quad SPI flash memory

• JTAG using a standard-A to micro-B USB cable for connecting the host PC to the AC701
board configuration port or by J4 Platform Cable USB/Parallel Cable IV flat cable connector

Each configuration interface corresponds to one or more configuration modes and bus widths as
listed in
respectively, as shown in Figure 1-3.

X-Ref Target - Figure 1-3

Table 1-2. The mode switches M2, M1, and M0 are on SW1 positions 1, 2, and 3

FPGA_3V3

FPGA_M2
FPGA_M1
FPGA_M0

R339

1.21K 1%
1/10W

R338

1.21K 1%
1/10W

R337

1.21K 1%
1/10W

SW1

1

NC

2
3

SDA03H1SBD

6
5
4

Schematic

0381502

AC701 Evaluation Board www.xilinx.com 13

UG952 (v1.4) August 6, 2019

UG952_c1_03_011713

Figure 1-3: SW1 Default Settings

The default mode setting is M[2:0] = 001, which selects Master SPI flash memory at board
power-on. See

Configuration Options for more information about the mode switch SW1.

Table 1-2: AC701 Board FPGA Configuration Modes

Configuration

Mode

SW1 DIP switch

Settings (M[2:0])

Bus

Width

CCLK

Direction

Master SPI flash memory 001 x1, x2, x4 Output

JTAG 101 x1 Not applicable

Chapter 1: AC701 Evaluation Board Features

UG952_c1_04_092812

GND

2

2

1

1

B1

1.5V
Seiko
TS518SE_FL35E

2

1

3

BAS40-04

D6

40V

200 mW

NC

FPGA_VBATT

+

VCC1V8 (1.8V)

R83

4.70K 5%
1/10W

Send Feedback

For full details on configuring the FPGA, see 7 Series FPGAs Configuration User Guide (UG470)

[Ref 6].

Encryption Key Backup Circuit

FPGA U1 implements bitstream encryption key technology. The AC701 board provides the
encryption key backup battery circuit shown in
button-type battery B1 is soldered to the board with the positive output connected to FPGA U1
VCCBATT pin G14. The battery supply current I
board power is off. B1 is charged from the VCC1V8 1.8V rail through a series diode with a typical
forward voltage drop of 0.38V and 4.7 kΩ current limit resistor. The nominal charging voltage is

1.62V.

X-Ref Target - Figure 1-4

Figure 1-4. The rechargeable 1.5V lithium

specification is 150 nA maximum when

BATT

14 www.xilinx.com AC701 Evaluation Board

I/O Voltage Rails

Figure 1-4: Encryption Key Backup Circuit

In addition to Bank 0, there are eight I/O banks available on the Artix-7 device. The voltages applied
to the FPGA I/O banks used by the AC701 board are listed in

Table 1-3.

Table 1-3: FPGA Bank Voltage Rails

U1 FPGA Bank

Power Supply Rail

Net Name

Vol tage

Bank 0 FPGA_3V3 3.3V

Bank 12 VCCO_VADJ 2.5V

Bank 13 FPGA_1V8 1.8V

Bank 14 FPGA_3V3 3.3V

Bank 15 VCCO_VADJ 2.5V

Bank 16 VCCO_VADJ 2.5V

Bank 33 FPGA_1V5 1.5V

UG952 (v1.4) August 6, 2019

Table 1-3: FPGA Bank Voltage Rails (Cont’d)

Send Feedback

Feature Descriptions

U1 FPGA Bank

Bank 34 FPGA_1V5 1.5V

Bank 35 FPGA_1V5 1.5V

DDR3 Memory Module

[Figure 1-2, callout 2]

The memory module at J1 is a 1 GB DDR3 small outline dual-inline memory module (SODIMM).
It provides volatile synchronous dynamic random access memory (SDRAM) for storing user code
and data. The SODIMM socket has a perforated EMI shield surrounding it as seen in

• Part number: MT8JTF12864HZ-1G6G1 (Micron Technology)

• Configuration: 1GB (128 Mb x 64)

• Supply voltage: 1.5V

• Datapath width: 64 bits

• Data rate: up to 1,600 MT/s

The AC701 XC7A200T FPGA memory interface performance is documented in the Artix-7 FPGAs
Data Sheet: DC and AC Switching Characteristics (DS181)

The DDR3 interface is implemented across I/O banks 33, 34, and 35. An external 0.75V reference
VTTREF is provided for these banks. Any interface connected to these banks that requires a
reference voltage must use this FPGA voltage reference. The connections between the DDR3
memory and the FPGA are listed in

Power Supply Rail

Net Name

Table 1-4.

Vol tage

Figure 1-2.

[Ref 4].

Table 1-4: DDR3 Memory Connections to the FPGA

FPGA Pin (U1)

M4 DDR3_A0 SSTL15 98 A0

J3 DDR3_A1 SSTL15 97 A1

J1 DDR3_A2 SSTL15 96 A2

L4 DDR3_A3 SSTL15 95 A3

K5 DDR3_A4 SSTL15 92 A4

M7 DDR3_A5 SSTL15 91 A5

K1 DDR3_A6 SSTL15 90 A6

M6 DDR3_A7 SSTL15 86 A7

H1 DDR3_A8 SSTL15 89 A8

K3 DDR3_A9 SSTL15 85 A9

N7 DDR3_A10 SSTL15 107 A10/AP

L5 DDR3_A11 SSTL15 84 A11

L7 DDR3_A12 SSTL15 83 A12_BC_N

Schematic Net

Name

I/O Standard

J1 DDR3 Memory

Pin Number Pin Name

AC701 Evaluation Board www.xilinx.com 15

UG952 (v1.4) August 6, 2019

Chapter 1: AC701 Evaluation Board Features

Send Feedback

Table 1-4: DDR3 Memory Connections to the FPGA (Cont’d)

FPGA Pin (U1)

N6 DDR3_A13 SSTL15 119 A13

L3 DDR3_A14 SSTL15 80 A14

K2 DDR3_A15 SSTL15 78 A15

N1 DDR3_BA0 SSTL15 109 BA0

M1 DDR3_BA1 SSTL15 108 BA1

H2 DDR3_BA2 SSTL15 79 BA2

AB6 DDR3_D0 SSTL15 5 DQ0

AA8 DDR3_D1 SSTL15 7 DQ1

Y8 DDR3_D2 SSTL15 15 DQ2

AB5 DDR3_D3 SSTL15 17 DQ3

AA5 DDR3_D4 SSTL15 4 DQ4

Y5 DDR3_D5 SSTL15 6 DQ5

Y6 DDR3_D6 SSTL15 16 DQ6

Y7 DDR3_D7 SSTL15 18 DQ7

Schematic Net

Name

I/O Standard

J1 DDR3 Memory

Pin Number Pin Name

AF4 DDR3_D8 SSTL15 21 DQ8

AF5 DDR3_D9 SSTL15 23 DQ9

AF3 DDR3_D10 SSTL15 33 DQ10

AE3 DDR3_D11 SSTL15 35 DQ11

AD3 DDR3_D12 SSTL15 22 DQ12

AC3 DDR3_D13 SSTL15 24 DQ13

AB4 DDR3_D14 SSTL15 34 DQ14

AA4 DDR3_D15 SSTL15 36 DQ15

AC2 DDR3_D16 SSTL15 39 DQ16

AB2 DDR3_D17 SSTL15 41 DQ17

AF2 DDR3_D18 SSTL15 51 DQ18

AE2 DDR3_D19 SSTL15 53 DQ19

Y1 DDR3_D20 SSTL15 40 DQ20

Y2 DDR3_D21 SSTL15 42 DQ21

AC1 DDR3_D22 SSTL15 50 DQ22

AB1 DDR3_D23 SSTL15 52 DQ23

16 www.xilinx.com AC701 Evaluation Board

Y3 DDR3_D24 SSTL15 57 DQ24

W3 DDR3_D25 SSTL15 59 DQ25

UG952 (v1.4) August 6, 2019

Table 1-4: DDR3 Memory Connections to the FPGA (Cont’d)

Send Feedback

Feature Descriptions

FPGA Pin (U1)

W6 DDR3_D26 SSTL15 67 DQ26

V6 DDR3_D27 SSTL15 69 DQ27

W4 DDR3_D28 SSTL15 56 DQ28

W5 DDR3_D29 SSTL15 58 DQ29

W1 DDR3_D30 SSTL15 68 DQ30

V1 DDR3_D31 SSTL15 70 DQ31

G2 DDR3_D32 SSTL15 129 DQ32

D1 DDR3_D33 SSTL15 131 DQ33

E1 DDR3_D34 SSTL15 141 DQ34

E2 DDR3_D35 SSTL15 143 DQ35

F2 DDR3_D36 SSTL15 130 DQ36

A2 DDR3_D37 SSTL15 132 DQ37

A3 DDR3_D38 SSTL15 140 DQ38

C2 DDR3_D39 SSTL15 142 DQ39

Schematic Net

Name

I/O Standard

J1 DDR3 Memory

Pin Number Pin Name

C3 DDR3_D40 SSTL15 147 DQ40

D3 DDR3_D41 SSTL15 149 DQ41

A4 DDR3_D42 SSTL15 157 DQ42

B4 DDR3_D43 SSTL15 159 DQ43

C4 DDR3_D44 SSTL15 146 DQ44

D4 DDR3_D45 SSTL15 148 DQ45

D5 DDR3_D46 SSTL15 158 DQ46

E5 DDR3_D47 SSTL15 160 DQ47

F4 DDR3_D48 SSTL15 163 DQ48

G4 DDR3_D49 SSTL15 165 DQ49

K6 DDR3_D50 SSTL15 175 DQ50

K7 DDR3_D51 SSTL15 177 DQ51

K8 DDR3_D52 SSTL15 164 DQ52

L8 DDR3_D53 SSTL15 166 DQ53

J5 DDR3_D54 SSTL15 174 DQ54

J6 DDR3_D55 SSTL15 176 DQ55

AC701 Evaluation Board www.xilinx.com 17

UG952 (v1.4) August 6, 2019

G6 DDR3_D56 SSTL15 181 DQ56

H6 DDR3_D57 SSTL15 183 DQ57

Chapter 1: AC701 Evaluation Board Features

Send Feedback

Table 1-4: DDR3 Memory Connections to the FPGA (Cont’d)

FPGA Pin (U1)

F7 DDR3_D58 SSTL15 191 DQ58

F8 DDR3_D59 SSTL15 193 DQ59

G8 DDR3_D60 SSTL15 180 DQ60

H8 DDR3_D61 SSTL15 182 DQ61

D6 DDR3_D62 SSTL15 192 DQ62

E6 DDR3_D63 SSTL15 194 DQ63

AC6 DDR3_DM0 SSTL15 11 DM0

AC4 DDR3_DM1 SSTL15 28 DM1

AA3 DDR3_DM2 SSTL15 46 DM2

U7 DDR3_DM3 SSTL15 63 DM3

G1 DDR3_DM4 SSTL15 136 DM4

F3 DDR3_DM5 SSTL15 153 DM5

G5 DDR3_DM6 SSTL15 170 DM6

H9 DDR3_DM7 SSTL15 187 DM7

Schematic Net

Name

I/O Standard

J1 DDR3 Memory

Pin Number Pin Name

W8 DDR3_DQS0_N SSTL15 10 DQS0_N

V8 DDR3_DQS0_P SSTL15 12 DQS0_P

AE5 DDR3_DQS1_N SSTL15 27 DQS1_N

AD5 DDR3_DQS1_P SSTL15 29 DQS1_P

AE1 DDR3_DQS2_N SSTL15 45 DQS2_N

AD1 DDR3_DQS2_P SSTL15 47 DQS2_P

V2 DDR3_DQS3_N SSTL15 62 DQS3_N

V3 DDR3_DQS3_P SSTL15 64 DQS3_P

B1 DDR3_DQS4_N SSTL15 135 DQS4_N

C1 DDR3_DQS4_P SSTL15 137 DQS4_P

A5 DDR3_DQS5_N SSTL15 152 DQS5_N

B5 DDR3_DQS5_P SSTL15 154 DQS5_P

H4 DDR3_DQS6_N SSTL15 169 DQS6_N

J4 DDR3_DQS6_P SSTL15 171 DQS6_P

G7 DDR3_DQS7_N SSTL15 186 DQS7_N

H7 DDR3_DQS7_P SSTL15 188 DQS7_P

18 www.xilinx.com AC701 Evaluation Board

R2 DDR3_ODT0 SSTL15 116 ODT0

U2 DDR3_ODT1 SSTL15 120 ODT1

UG952 (v1.4) August 6, 2019

Table 1-4: DDR3 Memory Connections to the FPGA (Cont’d)

Send Feedback

Feature Descriptions

FPGA Pin (U1)

N8 DDR3_RESET_B LV CM OS 15 30 RESET_B

T3 DDR3_S0_B SSTL15 114 S0_B

T2 DDR3_S1_B SSTL15 121 S1_B

U1

R1 DDR3_WE_B SSTL15 113 WE_B

T4 DDR3_CAS_B SSTL15 115 CAS_B

P1 DDR3_RAS_B SSTL15 110 RAS_B

P4 DDR3_CKE0 SSTL15 73 CKE0

N4 DDR3_CKE1 SSTL15 74 CKE1

L2 DDR3_CLK0_N DIFF_SSTL15 103 CK0_N

M2 DDR3_CLK0_P DIFF_SSTL15 101 CK0_P

N2 DDR3_CLK1_N DIFF_SSTL15 104 CK1_N

N3 DDR3_CLK1_P DIFF_SSTL15 102 CK1_P

Schematic Net

Name

DDR3_TEMP_

EVENT

I/O Standard

LV CM OS 15 198 EVENT_B

J1 DDR3 Memory

Pin Number Pin Name

The AC701 board DDR3 memory interface adheres to the constraints guidelines documented in the
DDR3 Design Guidelines section of the 7
(UG586)

[Ref 4]. The AC701 board DDR3 memory interface is a 40 Ω impedance implementation.

Series FPGAs Memory Interface Solutions User Guide

Other memory interface details are available in the 7 Series FPGAs Memory Interface Solutions

User

Guide (UG586) and the 7 Series FPGAs Memory Resources User Guide (UG473) [Ref 5]. For

more DDR3 SODIMM details, see the Micron MT8JTF12864HZ-1G6G1 data sheet [Ref 15].

AC701 Evaluation Board www.xilinx.com 19

UG952 (v1.4) August 6, 2019

Chapter 1: AC701 Evaluation Board Features

UG952_c1_05_060514

VCC3V3

N25Q256
256 Mb Serial
Flash Memory

GND

1

2

3

5

7

6

U7

4

8

VCC3V3

C18

0.1μF 25V
X5R

FLASH_D2

DQ1

16

15

14

12

10

11

13

9

SB

NC3

NC2

NC1

NC0

VCC

HOLD_B/DQ3

WB/VPP/DQ2

VSS

NC4

NC5

NC6

NC7

DQ0

C

R17

DNP

R18

4.7kΩ 5%

R431

15Ω 1%

R432

15Ω 1%

FLASH_D0

FPGA_CCLK

FLASH_D2_R

FLASH_D0_R

GND

VCC3V3

R20

DNP

R19

4.7kΩ 5%

R21

4.7kΩ 5%

R430

15Ω 1%

R429

15Ω 1%

FLASH_D2_R

FLASH_D3_R

FLASH_D3

FLASH_D1

QSPI_IC_CS_B

Send Feedback

Quad SPI Flash Memory

[Figure 1-2, callout 3]

The Quad SPI flash memory U7 provides 256 Mb of nonvolatile storage that can be used for
configuration and data storage.

• Part number: N25Q256A13ESF40G (Micron)

• Supply voltage: 3.3V

• Datapath width: 4 bits

• Data rate: various depending on Single/Dual/Quad mode and CCLK rate

Four data lines and the FPGA CCLK pin are wired to the Quad SPI flash memory. The connections
between the SPI flash memory and the FPGA are listed in

Table 1-5: Quad SPI Flash Memory Connections to the FPGA

Table 1-5.

X-Ref Target - Figure 1-5

FPGA Pin (U1)

Schematic Net

Name

I/O Standard

U7 Quad SPI Flash Memory

Pin Number Pin Name

R14 FLASH_D0 LV CM OS 33 15 DQ0

R15 FLASH_D1 LV CM OS 33 8 DQ1

P14 FLASH_D2 LV CM OS 33 9 DQ2

N14 FLASH_D3 LV CM O S3 3 1 DQ3

H13 FPGA_CCLK LVC MO S3 3 16 C

P18 QSPI_IC_CS_B LV CM OS 33 7 S_B

The configuration section of the 7 Series FPGAs Configuration User Guide (UG470) [Ref 6] provides
details on using the Quad SPI flash memory. Figure 1-5 shows the connections of the Quad SPI flash
memory on the AC701 board. For more details, see the Micron N25Q256A13ESF40G data sheet

[Ref 15].

20 www.xilinx.com AC701 Evaluation Board

Figure 1-5: 256 Mb Quad SPI Flash Memory

UG952 (v1.4) August 6, 2019

SPI Flash Memory External Programming Header

UG952_c1_06_092812

VCC3V3

GND

2

3

4

6

8

7

5

9

FLASH_D3

FLASH_D2

QSPI_CS_B

FLASH_D0

FLASH_D1

FPGA_CCLK

1

FPGA_PROG_B

J7

HDR

1X9

Send Feedback

In addition to the Quad SPI device FPGA U1 connections shown in Table 1-5, the FPGA U1 SPI
flash memory interface is connected to an external programming header J7.

Table 1-6 shows the SPI flash memory J7 connections to FPGA U1.

Table 1-6: SPI Flash Memory J7 Connections to the FPGA

U1 FPGA Pin Schematic Net Name J7 Pin

AE16 FPGA_PROG_B 1

N14 FLASH_D3 2

P14 FLASH_D2 3

J3.2 QSPI_CS_B 4

R14 FLASH_D0 5

R15 FLASH_D1 6

H13 FPGA_CCLK 7

NA GND 8

Feature Descriptions

NA VCC3V3 9

Figure 1-6 shows the J7 SPI flash memory external programming connector.

X-Ref Target - Figure 1-6

Figure 1-6: SPI Flash Memory J7 External Programming Connector

AC701 Evaluation Board www.xilinx.com 21

UG952 (v1.4) August 6, 2019

Chapter 1: AC701 Evaluation Board Features

UG952_c1_07_100212

SDIO Card

Connector

U29

DETECT

DAT2

DAT1

DAT0

CLK

CMD

CD_DAT3

VDD

PROTECT

GNDTAB2VSS1

GNDTAB1

VSS2

GND

GND

SDIO_SDWP

11

SDIO_SDDET

10

SDIO_DAT2

9

SDIO_DAT1

8

SDIO_DAT0 7

SDIO_CLK

5

SDIO_CMD

1SDIO_CD_DAT3

VCC3V3

C52

0.1μF 25V
X5R

GND

4

6

3

D_P

12

GNDTAB3

GNDTAB4

IOGND1

IOGND2

15

16

17

18

13

14

51.1K 1% Eight Places

VCC3V3

R319

R325

R324

R318

R322

R323

R317

R321

2

To

FPGA

Bank 14

(U1)

Send Feedback

SD Card Interface

[Figure 1-2, callout 4]

The AC701 board includes a secure digital input/output (SDIO) interface to provide user-logic
access to general purpose nonvolatile SDIO memory cards and peripherals. The SD card slot is
designed to support 50

The SDIO signals are connected to I/O bank 14, which has its VCCO set to 3.3V. Figure 1-7 shows
the connections of the SD card interface on the AC701 board.

X-Ref Target - Figure 1-7

MHz high speed SD cards.

Figure 1-7: SD Card Interface

Table 1-7 lists the SD card interface connections to the FPGA.

22 www.xilinx.com AC701 Evaluation Board

Table 1-7: SDIO Connections to the FPGA

FPGA Pin (U1)

R20 SDIO_SDWP LV CM OS 33 11 SDWP

P24 SDIO_SDDET LV CM OS 33 10 SDDET

N23 SDIO_CMD LV CM OS 33 2 CMD

N24 SDIO_CLK LV CM OS 33 5 CLK

P23 SDIO_DAT2 LV CM OS 33 9 DAT2

N19 SDIO_DAT1 LV CM OS 3 3 8 DAT1

P19 SDIO_DAT0 LV CM OS 33 7 DAT0

P21 SDIO_CD_DAT3 LV CM OS 33 1 CD_DAT3

Schematic Net

Name

I/O Standard

U29 SDIO Connector

Pin Number Pin Name

UG952 (v1.4) August 6, 2019

X-Ref Target - Figure 1-8

UG952_c1_08_012913

Part of U19

BUFFER

USB

Module

(U26)

or

JTAG

Connector

(J4)

TDO

TDI

U1

FPGA

TDI

TDO

FMC HPC

Connector

TDI

TDO

J30

N.C.

SPST Bus Switch
U27

Part of U19

BUFFER

Send Feedback

Feature Descriptions

USB JTAG Module

[Figure 1-2, callout 5]

JTAG configuration is provided through a Digilent onboard USB-to-JTAG configuration logic
module (U26) where a host computer accesses the AC701 board JTAG chain through a standard-A
plug (host side) to micro-B plug (AC701 board side) USB cable.

A 2-mm JTAG header (J4) is also provided in parallel for access by Xilinx download cables such as
the Platform Cable USB II and the Parallel Cable IV.

The JTAG chain of the AC701 board is illustrated in Figure 1-8. JTAG configuration is allowed at
any time regardless of FPGA mode pin settings. JTAG initiated configuration takes priority over the
configuration method selected through the FPGA mode pin settings at SW1.

AC701 Evaluation Board www.xilinx.com 23

UG952 (v1.4) August 6, 2019

Figure 1-8: JTAG Chain Block Diagram

When an FMC card is attached to the AC701 board, it is automatically added to the JTAG chain
through electronically controlled single-pole single-throw (SPST) switch U27. The SPST switch is
in a normally closed state and transitions to an open state when an FMC card is attached. Switch
U27 adds an attached FMC HPC mezzanine card to the FPGAs JTAG chain as determined by the
FMC_HPC_PRSNT_M2C_B signal. The attached FMC card must implement a TDI-to-TDO
connection through a device or bypass jumper in order for the JTAG chain to be completed to the
FPGA U1.

Chapter 1: AC701 Evaluation Board Features

UG952_c1_09_101512

JTAG_TDI

FMC_TDI_BUF

FPGA_TDO

FPGA_TMS_BUF

FPGA_TCK_BUF

FPGA_TDI_BUF

FMC1_TDO_FPGA_TDI

FMC1_HPC_TMS_BUF

FMC1_HPC_PRSNT_M2C_B

JTAG_TMS

JTAG_TCK

JTAG_TDO

FMC1_HPC_TCK_BUF

FMC1 HPC

Connector

TDI

TDO

J30

TMS

TCK

PRSNT_L

VCC3V3

Artix-7

FPGA

TDI

N16

TDO

U1

TMS

TCK

Digilent

USB-JTAG

Module

TMS

TDI

SN74LV541A

Buffer

U19

R95 15Ω

U26

R96 15Ω

R94 15Ω

TCK

TDO

TMS

TDI

J4

TCK

TDO

JTAG

Header

VCC3V3

VCC3V3

U27

Bank 0

Bank 14

Send Feedback

The JTAG connectivity on the AC701 board allows a host computer to download bitstreams to the
FPGA using Xilinx software tools. In addition, the JTAG connector allows debug tools or a software
debugger to access the FPGA. Xilinx software tools can also indirectly program the Quad SPI flash
memory. To accomplish this, Xilinx software configures the FPGA with a temporary design to
access and program the Quad SPI flash memory device. The JTAG circuit is shown in

X-Ref Target - Figure 1-9

Figure 1-9.

Figure 1-9: JTAG Circuit

Clock Generation

There are three clock sources available for the FPGA logic on the AC701 board (see Table 1-8).

Table 1-8: AC701 Board Clock Sources

FPGA

Pin (U1)

Schematic Net

Name

I/O Standard

Clock

Reference

R3 SYSCLK_P LVDS_25

U51

P3 SYSCLK_N LVDS_25 5

24 www.xilinx.com AC701 Evaluation Board

Pin Description

4 SiT9102 2.5V LVDS 200 MHz Fixed Frequency Oscillator

(SiTime). See

System Clock Source.

UG952 (v1.4) August 6, 2019

Table 1-8: AC701 Board Clock Sources (Cont’d)

UG952_c1_110_012015

U1

Artix-7 FPGA

XC7A200T-2FBG676C

Bank 16
Bank 15
Bank 14
Bank 13
Bank 12

Bank 36
Bank 35
Bank 34
Bank 33
Bank 32

GTP Quad

216

GTP Quad

213

PCI Express

Connector

P1

User SMA

J31(P)/J32(N)

Si5324

Jitter Attenuator

CLK Multiplier

U24

GTP SMA

J25(P)/J26(N)

FMC Connector

(HPC)

J30

SI570

Programmable

Oscillator

U34

Default 156.25 MHz

ICS844021

125 Mhz Clock

U2

X6

Crystal

Oscillator

114.285 MHz

3

2

1

0

U3

0

1

2

3

U4

PCIE_CLK_Q0_P/N

SYSCLK_P/N

Pins R3,P3

System CLK

200 MHz

U51

EMCCLK

90 MHz

U40

Rec_Clock_C_P/N Pins D23,D24

SEP_MGT_CLK_SEL[1:0] Pins C24:B26

PCIE_MGT_CLK_SEL[1:0] Pins C26:A24

USER_CLOCK_N

FPGA_EMCCLK

USER_CLOCK_N/P

EPHYCLK_Q0_C_P/N Pins 7,6

SI5324_Out0_C_N/P Pins 29,28

Pins D4,D5

Pins B20,B21

SI532_Out1_C_P/N Pins 35,34

SMA_MGT_REFCLK_P Pin 1,1

SFP_MGT_CLK0_N/P Pins AA13,AB13

SFP_MGT_CLK1_N/P Pins AA13,AB13

Pins J23,H23

Pins 3

Pins M21,M22

NC

NC

I2C

I2C or SPI

Send Feedback

Feature Descriptions

FPGA

Pin (U1)

Schematic Net

Name

I/O Standard

Clock

Reference

M21 USER_CLOCK_P LVDS_25

U34

M22 USER_CLOCK_N LVDS_25 5

P16 FPGA_EMCCLK LV CM OS 3 3 U40 3

The AC701 clocking diagram is shown in Figure 1-10. The FPGA logic clock source circuits are
detailed first after Figure 1-10, followed by the GTP clock sources circuitry descriptions in the GTP

Transceivers section.

X-Ref Target - Figure 1-10

Pin Description

4 Si570 3.3V LVDS I2C Programmable Oscillator (Silicon

Labs). Default power-on frequency 156.250

MHz. See

Programmable User Clock Source.

SiT8103 3.3V Single-Ended LVCMOS 90 MHz Fixed
Frequency Oscillator (SiTime). See

System Clock Source.

AC701 Evaluation Board www.xilinx.com 25

Figure 1-10: AC701 Board Clocking Diagram

UG952 (v1.4) August 6, 2019

Chapter 1: AC701 Evaluation Board Features

UG952_c1_10_100212

GND

VCC2V5

SIT9102
200 MHz
Oscillator

OE
NC
GND

VCC

OUT_B

OUT

1
2
3

6
5
4

U51

R166
100Ω 1%

SYSCLK_P

SYSCLK_N

C30

0.1 μF 10V
X5R

Send Feedback

System Clock Source

[Figure 1-2, callout 6]

The AC701 board has a 2.5V LVDS differential 200 MHz oscillator (U51) soldered onto the back
side of the board and wired to an FPGA MRCC clock input on bank 34. This 200
is named SYSCLK_P and SYSCLK_N, which are connected to FPGA U1 pins R3 and P3
respectively.

• Oscillator: Si Time SiT9102AI-243N25E200.00000 (200 MHz)

• PPM frequency tolerance: 50 ppm

• Differential output

For more details, see the Si Time SiT9102 data sheet [Ref 20]. The system clock circuit is shown in

Figure 1-11.

X-Ref Target - Figure 1-11

MHz signal pair

26 www.xilinx.com AC701 Evaluation Board

Programmable User Clock Source

[Figure 1-2, callout 7]

The AC701 board has a programmable low-jitter 3.3V differential oscillator (U34) driving the
FPGA MRCC inputs of bank 14. This USER_CLOCK_P and USER_CLOCK_N clock signal pair
are connected to FPGA U1 pins M21 and M22 respectively. On power-up, the user clock defaults to
an output frequency of 156.250
range of 10
user clock to its default frequency of 156.250

• Programmable oscillator: Silicon Labs Si570BAB000544DG (10 MHz–810 MHz)

• Differential output

MHz to 810 MHz through an I2C interface. Power cycling the AC701 board reverts the

Figure 1-11: System Clock Source

MHz. User applications can change the output frequency within the

MHz.

UG952 (v1.4) August 6, 2019

The user clock circuit is shown in Figure 1-12.

Send Feedback

X-Ref Target - Figure 1-12

VCC3V3

Feature Descriptions

VCC3V3

To

I2C

Bus Switch

(U49)

R15

4.7KΩ 5%

USER CLOCK SDA

USER CLOCK SCL

GND

U34

Si570

Programmable

Oscillator

1

NC

2

OE

7

SDA

8

SCL

3

GND

VDD

CLK-

CLK+

6

USER CLOCK N

5

USER CLOCK P

4

C192

0.01 μF 25V
X7R

GND

10 MHz - 810 MHz

UG952_c1_11_101512

Figure 1-12: User Clock Source

The Silicon Labs Si570 data sheet is available from their website [Ref 21].

User SMA Clock Input

[Figure 1-2, callout 8]

An external high-precision clock signal can be provided to the FPGA bank 15 by connecting
differential clock signals through the onboard 50Ω SMA connectors J31 (P) and J32 (N). The
differential clock signal names are USER_SMA_CLOCK_P and USER_SMA_CLOCK_N, which
are connected to FPGA U1 pins J23 and H23 respectively. The user-provided differential clock
circuit is shown in

Figure 1-13.

Note: This user clock is input to FPGA bank 15 which is powered by VCCO_VADJ. The

VCCO_VADJ rail is typically 2.5V, but can be reprogrammed to be either 1.8V or 3.3V. The
USER_SMA_CLOCK_P/N signals should not exceed the VCCO_VADJ voltage (1.8V, 2.5V or 3.3V)
in use.

X-Ref Target - Figure 1-13

J31

SMA

Connector

J32

SMA

Connector

USER_SMA_CLOCK_P

GND

USER_SMA_CLOCK_N

GND

UG952_c1_12_100212

Figure 1-13: User SMA Clock Source

AC701 Evaluation Board www.xilinx.com 27

UG952 (v1.4) August 6, 2019

Chapter 1: AC701 Evaluation Board Features

Send Feedback

GTP Transceiver Clock Multiplexer

[Figure 1-2, callout 35]

The AC701 board provides flexible GTP Quad 213 MGTREFCLK options through the use of
external multiplexer (MUX) components U3 and U4 to service the GTP Quad 213 SFP, FMC, and
SMA MGT interfaces.

FPGA U1 MGT Bank 213 has two clock inputs, MGTREFCLK0 and MGTREFCLK1. Each clock
input is driven by a series capacitor coupled clock sourced from a SY89544UMG 4-to-1
multiplexer.

Each multiplexer has a clock source at three of its four inputs; the fourth input is not connected.

The diagram for the GTP Quad 213 clock multiplexer circuit is shown in Figure 1-14.

X-Ref Target - Figure 1-14

U2

ICS844021

125 Mhz Clock

U24

Si5324

Jitter Attenuator

CLK Multiplier

X6

Crystal

Oscillator

114.285 MHz

J25(P)/J26(N)

I2C or SPI

J30

FMC Connector

GTP SMA

EPHYCLK_Q0_C_P/N Pins 7,6

SI5324_Out0_C_N/P Pins 29,28

Pins D4,D5

(HPC)

Pins B20,B21

SI5324_Out1_C_P/N Pins 35,34

SMA_MGT_REFCLK_P Pin 1,1

NC

NC

Rec_Clock_C_P/N Pins D23,D24

SEP_MGT_CLK_SEL[1:0] Pins C24:B26

PCIE_MGT_CLK_SEL[1:0] Pins C26:A24

0
1

U3

2
3

3
2

U4

1
0

SFP_MGT_CLK0_N/P Pins AA13,AB13

SFP_MGT_CLK1_N/P Pins AA13,AB13

SFP TX/RX

FMC DPO

FMC DP1

SMA MGT TX/RX

U1

Artix-7 FPGA

XC7A200T­2FBG676C

Bank 16

GTP Quad

213

UG952_c1_114_012115

Table 1-9: MGT Clock Multiplexer U3 and U4 Clock Sources

Jitter attenuated clock U24

FMC HPC GBT CLK0

GTP SMA REFCLK

28 www.xilinx.com AC701 Evaluation Board

Figure 1-14: AC701 Board GTP 213 U3 and U4 MUX Inputs

Table 1-9 lists the MGT sources for U3 and U4. See Table 1-10 and Table 1-11 for details.

Clock Name Reference Description

125 MHz clock

generator

U2

ICS844021 Crystal-to-LVDS Clock Generator (ICS). See U3 IN0: 125 MHz Clock

Generator.

Si5324C LVDS precision clock multiplier/jitter attenuator (Silicon Labs). See U3/U4

IN1: Jitter Attenuated Clock.

FMC_HPC_GBTCLK0_M2C_C_P/N at U3; FMC_HPC_GBTCLK1_M2C_C_P/N at
U4; See

U3/U4 IN2: FMC HPC GBT Clocks.

and CLK1

J30

J25 SMA_MGT_REFCLK_P (net name). See U4 IN0: GTP Transceiver SMA Clock Input.

(differential pair)

J26 SMA_MGT_REFCLK_N (net name). See U4 IN0: GTP Transceiver SMA Clock Input.

UG952 (v1.4) August 6, 2019

Clock Multiplexer U3 SY89544UMG drives Bank 213 MGTREFCLK0 pins AA13 (P) and AB13

Send Feedback

(N).

See Table 1-10 for clock MUX U3 connections.

Table 1-10: Multiplexer U3 SY89544UMG MGT Clock Inputs

Clock Source

Device Ref Pin Input

ICS84402I U2

SI5324C-GM U24

FMC HPC J30

Schematic Net Name

7 EPHYCLK_Q0_P

6 EPHYCLK_Q0_N 2

29 SI5324_OUT0_C_N

28 SI5324_OUT0_C_P 30

D4

D5

FMC1_HPC_

GBTCLK0_M2C_P

FMC1_HPC_

GBTCLK0_M2C_N

SY89544UMG U3

SEL

[1:0](2)

IN0 00

IN1 01

IN2 10

Pin Output Pin Pin Name

4

32

27

25

10(Q)

11(QB)

Schematic Net Name

(1)

SFP_MGT_CLK0_P
SFP_MGT_CLK0_N

Feature Descriptions

FPGA U1 Bank 213

AA13
AB13

MGTREFCLK0P

MGTREFCLK0N

ADJ

23

21

of 2.5V)

Not connected IN3 11

Notes:

1. U3 output clock nets SFP_MGT_CLK0_P/N implement a series 0.1μF capacitor

2. SEL[1:0] nets SFP_MGT_CLK_SEL1 FPGA U1 pin C24 and SFP_MGT_CLK_SEL0 FPGA U1 pin B26.
The I/O standard is LVCMOS25 (IOSTANDARD assumes a default V

The multiplexer U3 clock input channel select nets are SFP_MGT_CLK_SEL[1:0].

Net SFP_MGT_CLK_SEL1 is wired to FPGA U1 pin C24 and net SFP_MGT_CLK_SEL0 is wired
to FPGA U1 pin B26 on FPGA U1 Bank 16.

The U3 multiplexer circuit is shown in Figure 1-15.

AC701 Evaluation Board www.xilinx.com 29

UG952 (v1.4) August 6, 2019