Winbond Electronics W78C51DP-40, W78C51DP-24, W78C51DF-40, W78C51DF-24, W78C51D-40 Datasheet

Preliminary W78C51D

INT2

INT2

8-BIT MICROCONTROLLER

GENERAL DESCRIPTION

The W78C51D microcontroller supplies a wider frequency and supply voltage range than most 8-bit
microcontrollers on the market. It is compatible with the industry standard 80C51 microcontroller
series.

The W78C51D contains four 8-bit bidirectional parallel ports, one extra 4-bit bit-addressable I/O port
(Port 4) and two additional external interrupts (

timer and a serial port. These peripherals are supported by a seven-source, two-level interrupt
capability. There are 128 bytes of RAM and an 4K byte mask ROM for application programs.

The W78C51D microcontroller has two power reduction modes, idle mode and power-down mode,
both of which are software selectable. The idle mode turns off the processor clock but allows for
continued peripheral operation. The power-down mode stops the crystal oscillator for minimum power
consumption. The external clock can be stopped at any time and in any state without affecting the
processor.

FEATURES

• Fully static design

• Supply voltage of 4.5V to 5.5V

• DC-40 MHz operation

• 128 bytes of on-chip scratchpad RAM

• 4K bytes of on-chip mask ROM

• 64K bytes program memory address space

• 64K bytes data memory address space

• Four 8-bit bidirectional ports

• Two 16-bit timer/counters

• One full duplex serial port

• Seven-source, two-level interrupt capability

• One extra 4-bit bit-addressable I/O port

, INT3 ), two 16-bit timer/counters, one watchdog

• Two additional external interrupts

• Watchdog timer

• EMI reduction mode

• Built-in power management

• Code protection

• Packages:

− DIP 40: W78C51D-24/40

− PLCC 44: W78C51DP-24/40

− QFP 44: W78C51DF-24/40

/ INT3

Publication Release Date: January 1999

- 1 - Revision A1

PIN CONFIGURATIONS

40-Pin DIP (W78C51D)

Preliminary W78C51D

44-Pin PLCC (W78C51DP)

/
I
N
T
3
,

P

P

P

P

P1.5
P1.6
P1.7

RST

RXD, P3.0
INT2, P4.3

TXD, P3.1
INT0, P3.2
INT1, P3.3

T0, P3.4
T1, P3.5

P

1

1

.

.

3

4

6 5 4 3

7
8
9
10
11
12
13
14
15
16

17

P

P

3

3

.

.

7

6

,

,

/

/

R

W

D

R

1

1
.

.

2

1

X

X

T

T

A

A

L

L

1

2

P

1

4

.

.

0

2

2 1 44 43 42

V

P

S

4

S

.
0

P1.0
P1.1

P1.2
P1.3
P1.4
P1.5
P1.6
P1.7

RST
RXD, P3.0
TXD, P3.1

INT0, P3.2
INT1, P3.3

T0, P3.4
T1, P3.5

WR, P3.6

RD, P3.7

XTAL2
XTAL1

VSS

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

VDD1

40
39

P0.0, AD0

38

P0.1, AD1

37

P0.2, AD2

36

P0.3, AD3

35

P0.4, AD4
P0.5, AD5

34
33

P0.6, AD6

32

P0.7, AD7

31

EA

30

ALE

29

PSEN

28

P2.7, A15
P2.6, A14

27
26

P2.5, A13

25

P2.4, A12
P2.3, A11

24
23

P2.2, A10

22

P2.1, A9

21

P2.0, A8

44-Pin QFP (W78C51DF)

/
I

P

P

P

1

1

1

.

.

.

0

2

1

4039 38 37 36 35

V

X

X

T

S

T

S

A

A

L

L

1

2

N
T
3
,
P

V

4

D

.

D

2

P

P

2

4

.

.

0

0

,
A
8

A

A

A

A

D

D

D

D

3

2

1

0

,

,

,

,

P

P

P

P
V
D
D

P
2
.
0
,
A
8

0

0

0

0

.

.

.

.

3

2

1

0

40

41

39

P0.4, AD4

38

P0.5, AD5

37

P0.6, AD6

36

P0.7, AD7

35

EA

34

P4.1

33

ALE

32

PSEN

31

P2.7, A15

30

P2.6, A14

29

P2.5, A13

2827262524232221201918

P

P

P

P

2

2

2

2

.

.

.

.

3

4

2

1

,

,

,

,

A

A

A

A

1

1

1

9

2

1

0

P1.5
P1.6
P1.7

RST
RXD, P3.0
INT2, P4.3

TXD, P3.1

INT0, P3.2

INT1, P3.3

T0, P3.4
T1, P3.5

1
2

3

4
5
6
7
8
9
10

11

P
1
.
4

44

12

P
3
.
6
,
/
W
R

P
1
.
3

43 42 41

P
3
.
7
,
/
R
D

A

A

A

A

D

D

D

D

3

2

1

0

,

,

,

,

P

P

P

P

0

0

0

0

.

.

.

.

3

1

2

0

34

33

P0.4, AD4

32

P0.5, AD5

31

P0.6, AD6

30

P0.7, AD7

29

EA

28

P4.1

27

ALE

26

PSEN

25

P2.7, A15

24

P2.6, A14

23

P2.5, A13

22212019181716151413

P

P

P

P

2

2

2

2

.

.

.

.

4

3

1

2

,

,

,

,

A

A

A

A

1

1

1

9

2

1

0

- 2 -

Preliminary W78C51D

INT0

INT1

WR

RD

INT2

EA

PIN DESCRIPTION

P0.0−P0.7

Port 0, Bits 0 through 7. Port 0 is a bidirectional I/O port. This port also provides a multiplexed low
order address/data bus during accesses to external memory.

P1.0−P1.7

Port 1, Bits 0 through 7. Port 1 is a bidirectional I/O port with internal pull-ups.

P2.0−P2.7

Port 2, Bits 0 through 7. Port 2 is a bidirectional I/O port with internal pull-ups. This port also provides
the upper address bits for accesses to external memory.

P3.0−P3.7

Port 3, Bits 0 through 7. Port 3 is a bidirectional I/O port with internal pull-ups. All bits have alternate
functions, which are described below:

PIN ALTERNATE FUNCTION

P3.0 RXD Serial Receive Data
P3.1 TXD Serial Transmit Data
P3.2

P3.3
P3.4 T0 Timer 0 Input

P3.5 T1 Timer 1 Input
P3.6

P3.7

External Interrupt 0

External Interrupt 1

Data Write Strobe

Data Read Strobe

P4.0−P4.3

Another bit-addressable bidirectional I/O port P4. P4.3 and P4.2 are alternative function pins. It can
be used as general I/O pins or external interrupt input sources (

External Address Input, active low. This pin forces the processor to execute out of external ROM.
This pin should be kept low for all W78C31 operations.

RST

Reset Input, active high. This pin resets the processor. It must be kept high for at least two machine
cycles in order to be recognized by the processor.

ALE

Address Latch Enable Output, active high. ALE is used to enable the address latch that separates the
address from the data on Port 0. ALE runs at 1/6th of the oscillator frequency. A single ALE pulse is
skipped during external data memory accesses. ALE goes to a high impedance state during reset with
a weak pull-up.

- 3 - Revision A1

/ INT3 ).

Publication Release Date: January 1999

Preliminary W78C51D

PSEN

PSEN

PSEN

Program Store Enable Output, active low.
address/data bus during fetch and MOVC operations.

enables the external ROM onto the Port 0

goes to a high impedance state during

reset with a weak pull-up.

XTAL1

Crystal 1. This is the crystal oscillator input. This pin may be driven by an external clock.

XTAL2

Crystal 2. This is the crystal oscillator output. It is the inversion of XTAL1.

VSS, VDD

Power Supplies. These are the chip ground and positive supplies.

BLOCK DIAGRAM

P1.0

~

P1.7

P3.0
~
P3.7

P4.0
~
P4.3

INT2

INT3

Port

1

Port

Port

3

4

Interrupt

UART

Port 1

Latch

Timer

0

Timer

1

Port 3

Latch

Port 4

Latch

Oscillator

ACC

PSW

Instruction

Decoder

&

Sequencer

Bus & Clock

Controller

ALU

SFR RAM

Address

128bytes

RAM & SFR

4KB

ROM

Watchdog

Timer

Reset Block

T2T1

B

Stack

Pointer

Power control

Port 0
Latch

DPTR

Temp Reg.

PC

Incrementor

Addr. Reg.

Port 2

Latch

Port
0

Port
2

P0.0
~
P0.7

P2.0
~
P2.7

XTAL1 PSENALE GNDVDDRSTXTAL2

- 4 -

Preliminary W78C51D

FUNCTIONAL DESCRIPTION

The W78C51D architecture consists of a core controller surrounded by various registers, five general
purpose I/O ports, 128 bytes of RAM, two timer/counters, one watchdog timer and a serial port. The
processor supports 111 different opcodes and references both a 64K program address space and a
64 K data storage space.

Timers 0, 1

Timers 0, 1 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer 0, TL1
and TH1 for Timer 1. The TCON and TMOD registers provide control functions for timers 0, 1.

Clock

The W78C51D is designed to be used with either a crystal oscillator or an external clock. Internally,
the clock is divided by two before it is used. This makes the W78C51D relatively insensitive to duty
cycle variations in the clock.

Crystal Oscillator

The W78C51D incorporates a built-in crystal oscillator. To make the oscillator work, a crystal must be
connected across pins XTAL1 and XTAL2. In addition, a load capacitor must be connected from each
pin to ground, and a resistor must also be connected from XTAL1 to XTAL2 to provide a DC bias
when the crystal frequency is above 24 MHz.

External Clock

An external clock should be connected to pin XTAL1. Pin XTAL2 should be left unconnected. The
XTAL1 input is a CMOS-type input, as required by the crystal oscillator. As a result, the external clock
signal should have an input high level of greater than 3.5 volts when VDD = 5 volts.

Power Management

Idle Mode

The idle mode is entered by setting the IDL bit in the PCON register. In the idle mode, the internal
clock to the processor is stopped. The peripherals and the interrupt logic continue to be clocked. The
processor will exit idle mode when either an interrupt or a reset occurs.

Power-down Mode

When the PD bit of the PCON register is set, the processor enters the power-down mode. In this
mode all of the clocks, including the oscillator are stopped. The only way to exit power-down mode is
by a reset.

Reset

The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two
machine cycles while the oscillator is running.

An internal trigger circuit in the reset line is used to deglitch the reset line when the W78C51D is used
with an external RC network. The reset logic also has a special glitch removal circuit that ignores
glitches on the reset line.

During reset, the ports are initialized to FFH, the stack pointer to 07H, PCON (with the exception of
bit 4) to 00H, and all of the other SFR registers except SBUF to 00H. SBUF is not reset.

Publication Release Date: January 1999

- 5 - Revision A1

Preliminary W78C51D

INT2

INT2

INT2

New Defined Peripheral

In order to be more suitable for I/O, an extra 4-bit bit-addressable port P4 and two external interrupts

, INT3 have been added to either the PLCC or QFP package. And description follows:

1.

Two additional external interrupts,
interrupt 0 and 1 in the standard 80C52. The functions/status of these interrupts are
determined/shown by the bits in the XICON (External Interrupt Control) register. The XICON register
is bit-addressable but is not a standard register in the standard 80C52. Its address is at 0C0H. To
set/clear bits in the XICON register, one can use the "SETB (/CLR) bit" instruction. For example,
"SETB 0C2H" sets the EX2 bit of XICON.

***XICON - external interrupt control (C0H)

PX3: External interrupt 3 priority high if set
EX3: External interrupt 3 enable if set
IE3: If IT3 = 1, IE3 is set/cleared automatically by hardware when interrupt is detected/serviced
IT3: External interrupt 3 is falling-edge/low-level triggered when this bit is set/cleared by software
PX2: External interrupt 2 priority high if set
EX2: External interrupt 2 enable if set
IE2: If IT2 = 1, IE2 is set/cleared automatically by hardware when interrupt is detected/serviced
IT2: External interrupt 2 is falling-edge/low-level triggered when this bit is set/cleared by software

Eight-source interrupt informations:

/ INT3

and INT3 , whose functions are similar to those of external

PX3 EX3 IE3 IT3 PX2 EX2 IE2 IT2

INTERRUPT

SOURCE

External Interrupt 0 03H 0 (highest) IE.0 TCON.0
Timer/Counter 0 0BH 1 IE.1 ­External Interrupt 1 13H 2 IE.2 TCON.2
Timer/Counter 1 1BH 3 IE.3 ­Serial Port 23H 4 IE.4 ­Timer/Counter 2 2BH 5 IE.5 ­External Interrupt 2 33H 6 XICON.2 XICON.0
External Interrupt 3 3BH 7 (lowest) XICON.6 XICON.3

2. PORT4

Another bit-addressable port P4 is also available and only 4 bits (P4<3:0>) can be used. This port
address is located at 0D8H with the same function as that of port P1, except the P4.3 and P4.2 are

VECTOR

ADDRESS

POLLING

SEQUENCE WITHIN

PRIORITY LEVEL

- 6 -

ENABLE

REQUIRED

SETTINGS

INTERRUPT

TYPE

EDGE/LEVEL