Wavetek 95 Service manual

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MAINTENANCE MANUAL

Model 95 20 MHz Synthesized Arb/Function Waveform

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MAINTENANCE MANUAL

Model 95 20 MHz Synthesized Arb/Function Waveform

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WARRANTY

Wavetek warrants that all products manufactured by Wavetek conform to published Wavetek specifications and are free from defects in materials and workmanship for a period of one (1) year from the date of delivery when used under normal operating conditions and within the service conditions for which they were furnished.

The obligation of Wavetek arising from a Warranty claim shall be limited to repairing, or at its option, replacing without charge, any product which in Wavetek's sole opinion proves to be defective within the scope of the Warranty. In the event Wavetek is not able to modify, repair or replace non-conforming defective parts or components to a condition as warrantied within a reasonable time after receipt thereof, Buyers shall be credited for their value at the original purchase price.

Wavetek must be notified in writing of the defect or nonconformity within the Warranty period and the affected product returned to Wavetek's factory or to an authorized service center within (30) days after discovery of such defect or nonconformity.

For product warranties requiring return to Wavetek, products must be returned to a service facility designated by Wavetek. Buyer shall prepay shipping charges, taxes, duties and insurance for products returned to Wavetek for warranty service. Except for products returned to Buyer from another country. Wavetek shall pay for return of products to Buyer.

Wavetek shall have no responsibility hereunder for any defect or damage caused by improper storage, improper installation, unauthorized modification, misuse, neglect, inadequate maintenance, accident or for any product which has been repaired or altered by anyone other than Wavetek or its authorized representative and not in accordance with instructions furnished by Wavetek.

Exclusion of Other Warranties

The Warranty described above is Buyer's sole and exclusive remedy and no other warranty, whether written or oral, is expressed or implied. Wavetek specifically disclaims the implied warranties of merchantability and fitness for a particular purpose. No statement, representation, agreement, or understanding, oral or written, made by an agent, distributor, representative, or employee of Wavetek, which is not contained in the foregoing Warranty will be binding upon Wavetek, unless made in writing and executed by an authorized Wavetek employee. Under no circumstances shall Wavetek be liable for any direct, indirect, special, incidental, or consequential damages, expenses, losses or delays (including loss of profits) based on contract, tort, or any other legal theory.

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SECTION 1	HOW TO USE THIS MANUAL
	1.1. INTRODUCTION1-11.2 WHAT IS IN THIS MANUAL1-11.3 HOW TO USE THIS MANUAL1-11.4 THE OPERATOR'S MANUAL1-1
SECTION 2	ROUTINE MAINTENANCE
, ,	2.1 CALIBRATION2-12.2 FUSE REPLACEMENT2-12.3 BATTERY REPLACEMENT2-22.4 FAN MAINTENANCE2-2
SECTION 3	VERIFICATION PROCEDURE
i -	3.1 Performance Verification
SECTION 4	CALIBRATION PROCEDURE
	4.1 CALIBRATION 4-1 4.1.1 Autocal 4-1 4.1.2 Calibration Procedure 4-1 4.2 AUTOCAL PROCEDURE 4-1 4.3 CALIBRATION PROCEDURE 4-1
SECTION 5	CIRCUIT DESCRIPTION
	5.1 THE MODEL 95 5-1 5.2 FUNCTION GENERATOR 5-1 5.2.1 Introduction 5-1 5.2.2 Function Generator Loop 5-2 5.2.3 VCG Summing Amplifier 5-6 5.2.4 Symmetry Control 5-7 5.2.5 High Frequency Compensation 5-7 5.3 ARBITRARY WAVEFORM GENERATOR 5-8 5.3.1 Introduction 5-8 5.3.2 Counter and Address Arbitrator 5-8 5.3.3 Active and Storage RAM 5-8 5.3.4 DAC Register 5-8 5.3.5 ARB DAC and Filters 5-8 5.3.7 Z-Axis Driver 5-8 5.4 OUTPUT SECTION 5-9 5.4.1 General 5-9 5.4.2 Square Shaper and Function Selector 5-10 5.4.4 Output Amplifier 5-10 5.4.5 -20 dB Attenuator 5-10

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CONTENTS (Continued)

5.4.6 Balanced Drivers
5.4.7 Unbalanced Output Attenuator Network and Impedance Control
5.4.8 Balanced Output Attenuator Network and Impedance Control	0 1 ! 5_11
5.5 FREQUENCY CONTROL	0 11 5-11
5.5.1 Introduction	0 11 5_11
5.5.2 VEREQ	5 11
5.5.3 Sweep Generator	0-11 5.11
5.5.4 Phase Lock Loon/Synthesizer	5 10
5.5.4.1 Introduction	5 12
5542 Frequency Reference	5 10
5.5.4.3 Sine/Tri Z-Crossing Detector	0-12 5 10
5544 Source Selector	5 12
5.5.4.5 Phase Datactor	5-14 5 1 4
5.5.4.6 Look Loop Eiltor
	5-14
5.0 MODE CONTROL	5-14
5.0.1 Introduction	5-14
5.6.2 Mode Control	5-14
5.6.3 Trigger Control	5-15
	5-15
5.7 MICROPROCESSOR AND INTERFACES	5-15
5.7.1 Introduction	5-15
5.7.2 Microprocessor Section	5-15
5.7.3 GPIB Interface	5-18
5.7.4 Board Interfaces	5-18
5.7.4.1 Function Generator Interface	5-18
5.7.4.2 Phase Lock Loop Interface	5-18
5.7.4.3 Arb Board Interface	5-18
5.7.4.4 Output Board Interface	5-20
5.7.4.5 Front Panel (Keyboard and Display)	5-20
5.7.5 DAC Sample and Hold Network	5-20
5.7.6 Internal Calibration Network	5-21
MAINTENANCE
	0.4
	6-1
	6-1
	6-1
	6-1
	6-1
6.6 BEFORE TROUBLESHOUTING	6-1
	6-1
6.6.2 Test Point Access	6-2
	6-2
6.7 FAULT ISOLATION	6-3
6.7.1 Front Panel Not Active - Neither the Front Panel's Display,
Annunciators, or Keyboard Operate	6-3
6.7.2 Front Panel Not Active - Keyboard Does Not Work	6-3
6.7.3 Front Panel Not Active - Display Does Not Work	6-3
6.7.4 Front Panel Not Active - Annunciators Do Not Work	6-4
6.7.5 Self Test and Self Test Error Messages	6-4
6.7.6 AutoCal and AutoCal Error Messages	6-4
	6-8

SECTION 6

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CONTENTS (Continued)

		6.8.1 Function Generator	.6-8
		6.8.2 Triangle Buffer/Comparator	.6-8
		6.8.3 Symmetry Control	.6-9
		6.8.4 VCG Current Sources	.6-9
		6.8.5 Trigger Baseline Compensation	.6-9
		6.8.6 High Frequency Compensation	.6-9
1		6 8 7 Frequency Bange Switches	.6-10
		6 8 8 Canacitance Multiplier	.6-10
		6.8.9 Function Generator Auto Calibration	.6-10
		6.8.10 Sween Generator	6-10
		6.8.11 Sine Convertor Buffer and Variable Supply	6-11
		6.8.12 Mode Control and Burst Counter	6-11
		6.8.12 Mode Control and Burst Counter	6_11
ı		6.9.14 Output Section	6_11
		6.8.15 Fraguenay Synthesizer and Phase Look Loop	6.13
		6.8.16 Microprocessor Section	6.13
		6.6.10 Microprocessor Section	6.13
		6.8.17 DAC Sample and Hold Network	6 14
		6.8.18 GPIB Section	6 14
			6 14
ı		6.9 DISASSEMBLY AND REASSEMBLY	-0-14 C 14
		6.9.1 Disassembly	.0-14
		6.9.2 Board Removal/Replacement	.6-14
		6.9.3 Reassembly	.6-15
	SECTION 7	PARTS LISTS AND SCHEMATICS
		7.1 DRAWINGS	.7-1
1		7.1.1 Assembly Drawing	.7-1
		7.1.2. Schematics	.7-1
		7.1.3 Parts Lists	.7-1
		7.2 ADDENDA	.7-1
l i		7.3 ORDERING PARTS	.7-1
		PRODUCT SPECIFICATIONS
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			A-3

			A.4
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			Δ.5
			Δ.5
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	APPENDIX B	PHASE CALIBRATION
		PHASE CALIBRATION	B-1

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FIGURES

SECTION 3	VERIFICATION PROCEDURE
	Figure 3-1. Frequency/Symmetry Measurement Setup Figure 3-2. VCG/FM Setup Figure 3-3. Waveforms/Sweep Verification Figure 3-4. Trigger Measurement Setup Figure 3-5. Balanced Output Verification Figure 3-6. AM Setup Figure 3-7. Sine Purity Measurement Figure 3-8. Amplitude Accuracy Figure 3-9. External Lock Measurement	.3-2 .3-3 .3-3 .3-5 .3-6 .3-6 .3-6 .3-7
SECTION 4	CALIBRATION PROCEDURE
	Figure 4-1. Board Locator Figure 4-2. Frequency Reference Setup Figure 4-3. Frequency Reference/TCXO Locator Figure 4-4. Sine Wave Adjust Setup Figure 4-5. R33/R97 Locator Figure 4-6. SCM Null Setup Figure 4-6. SCM Null Setup Figure 4-7. R146 Locator Figure 4-8. Triangle Null Setup Figure 4-9. R25 Locator Figure 4-9. R25 Locator Figure 4-10. R146 Locator Figure 4-11. R64 Locator Figure 4-12. R158 Locator Figure 4-13. Triangle Amplitude Setup Figure 4-14. R211 Locator Figure 4-15. R208 Locator Figure 4-16. R9 Locator Figure 4-17. R67, R69, R70, R84, R86, and R87 Locator Figure 4-18. Phase Setup Figure 4-19. Confidence Check Setup	.4-2 .4-3 .4-4 .4-5 .4-5 .4-6 .4-6 .4-6 .4-7 .4-7 .4-7 .4-8 .4-8 .4-8 .4-9 .4-9 .4-9 .4-9 .4-10 .4-11
SECTION 5	CIRCUIT DESCRIPTION
	Figure 5-1 Model 95 Functional Blocks Figure 5-2 Function Generator Block Diagram Figure 5-3 Function Generator Loop Figure 5-4 Simplified Comparator Figure 5-5 Simplified Arb Waveform Generator. Figure 5-6 Output Section Block Diagram Figure 5-7 Phase Lock Loop/Synthesizer Figure 5-8 Frequency Synthesizer Figure 5-9 Microprocessor and Interfaces Figure 5-10 Microprocessor Section	.5-0 .5-2 .5-3 .5-4 .5-9 .5-13 .5-13 .5-16 .5-17

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FIGURES (Continued)

	Figure 5-11. Internal Calibration	5-21
SECTION 6	MAINTENANCE
	Figure 6-1. Board Locations	6-3
APPENDIX B
	Figure B-1. Phase Setup	B-1

TABLES

-	SECTION 3	VERIFICATION PROCEDURE
_		Table 3-1. Required Test Equipment Table 3-2. Model 95 Default Conditions	3-1 3-1
	SECTION 4	CALIBRATION PROCEDURE
		Table 4-1. Recommended Test Equipment	4-2
-	SECTION 5	CIRCUIT DESCRIPTION
		Table 5-1. Range Control and Values	5-5
		Table 5-2. Range Control and Values	5-6
		Table 5-3. Mode Control	5-15
		Table 5-4. Function Generator Decoder	5-19
		Table 5-5. Arb Decoder	5-19
		Table 5-6. Output Decoder	5-20
		Table 5-7. DVM Mux 1	5-22
		Table 5-8. DVM Mux. 2	5-22
-		Table 5-9. Function Generator Mux.	5-23
		Table 5-10. Peak Detector	5-23
	SECTION 6	MAINTENANCE
		Table 6-1. Recommended Equipment	6-3
		Table 6-2. Power Supply Test Points	6-3
		Table 6-3. Self Test Error Messages	6-4
-		Table 6-4. Frequency Range Switches	6-10
		Table 6-5. Capacitance Multiplier	6-11
		Table 6-6. Arb Test Points	6-12

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SAFETY FIRST

Protect yourself. Follow these precautions:

Don't touch the outputs of the instrument or any exposed test wire carrying the output signals. This instrument can generate hazardous voltages and currents.
Don't bypass the power cord's ground lead with two-wire extension cords or plug adapters.
Don't disconnect the green and yellow safety-earth-ground wire that connects the ground lug of the power receptacle to the chassis ground terminal (marked with $\checkmark$ or r + 1).
Don't hold your eyes extremely close to an RF output for a long time. The normally nonhazardous low-power RF energy generated by the instrument could possibly cause eye injury.
Don't plug in the power cord until directed to by the installation instructions.
Don't repair the instrument unless you are a qualified electronics technician and know how to work with hazardous voltages.
Pay attention to the WARNING statements. They point out situations that can cause injury or death.
Pay attention to the CAUTION statements. They point out situations that can cause equipment damage.

WARNING

This instrument normally contains a lithium battery. Where lithium is prohibited, such as aboard U.S. Navy ships, verify that the lithium battery has been removed.

Do not recharge, short circuit, disassemble, or apply heat to the lithium battery. Violating this rule could release potentially harmful lithium. Observe polarity when you replace the battery.

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SECTION HOW TO USE THIS MANUAL

1.1. INTRODUCTION

This manual contains information on the testing, calibration, and servicing of the Wavetek Model 95, 20 MHz Synthesized Arbitrary Function Generator.

1.2 WHAT IS IN THIS MANUAL

This manual contains the following sections:

Section 2 Routine Preventive Maintenance.
Section 3 Verification Procedure.
Section 4 Calibration Procedure.
Section 5 Circuit Description.
- Section 6 Maintenance (Troubleshooting). Section 7 The Drawing Package. Appendix A. Product Description and Specification
1.3 HOW TO USE THIS MANUAL
The purpose of the maintenance manual is to support the technician in keeping the Model 95 functioning correctly. The material in this manual is organized in such a way as to aid the service technician in identifying and isolating a problem with the unit.

Spare And Replacement Parts

Users who plan on servicing the Model 95 may choose to order spare parts from Wavetek. Each assembly contains a parts list; see the drawing package, section 7. All parts listed may be ordered directly from Wavetek. In addition, a recommend spare parts package (Wavetek part number: 1200-00-3463) can be ordered from Wavetek.

Suspected Malfunctions

If the Model 95 does not operate correctly, check the instrument setup before trying to isolate the problem; see the Model 95 Operator's Manual . Or, perform an Autocal on the unit to see if the instrument will correct the problem itself; see section 4 of this manual. If there is a problem, performing Autocal causes the unit to return an error message.

If the problem is known, turn to the appropriate section and correct the fault. Use the Calibration procedure, section 4, when the Model 95 appears out of calibration. Also, the Model 95 provides error messages which can guide the technician to circuit blocks within the instrument; see section 6. Use the maintenance section, section 6, to isolate failures. Section 6 does not isolate problems down to the component level, but only to the circuit block. In addition to the Maintenance section, the Circuit Description, schematics, and assembly drawings all support problem isolation.

1.4 THE OPERATOR'S MANUAL

This manual does not cover the operation of the Model 95. The Model 95 Operator's Manual contains that information.

Product description and specifications - Section 1. Routine Maintenance - Section 2.

Operation which includes both front panel and remote (GPIB) - Section 3.

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This section covers routine tasks the Service Technician may perform on the Model 95.

2.1 CALIBRATION

Section 4 of this manual contains both the Autocal and Calibration Procedure instructions.
Autocal (automatic calibration) provides a quick method of calibrating the Model 95 without the use of external test equipment. Autocal automatically sets up the instrument and takes internal measurements using internal standards. The Model 95 calculates correction values and stores those values in memory. The Model 95 recalls and loads these correction values at power up. Use Autocal when Model 95 accuracy is critical, after long term instrument storage, or following drastic changes in the environment. Also, perform Autocal at anytime the Service Technician believes it is necessary. Performing Autocal will not erase the Arb active RAM.

The Calibration Procedure provides a more extensive method of Model 95 calibration. The Calibration Procedure uses external test equipment and requires opening the instrument for adjustments. Use the Calibration Procedure when the Model 95 displays "CAL REQUIRED" or "FAILED AUTO CAL", after repair, Performance Verification procedure (section 3) failure, or at routine scheduled calibration. Performing the Calibration Procedure erases the contents of the Model 95's Arb active memory.

2.2 FUSE REPLACEMENT

To replace the Model 95's fuse (rear panel) use the following instructions.

1. Disconnect the power cord at the instrument. Open the fuse holder cover door. Rotate the fuse-pull to the left to remove the fuse.
2. Replace the fuse with one having the same current and voltage ratings. The following table lists fuses used with different voltage ranges. Rotate the fuse pull lever back into the normal position. Insert the correct fuse in the fuse holder. Close the fuse holder cover door.

Card Position	Input Vac	Fuse
100	90 to 105	1A, 250 Vac, Slo Blo
120	108 to 126	1A, 250 Vac,
220	198 to 231	1/2A, 250 Vac,
240	216 to 252	1/2A, 250 Vac, Slo Blo

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3. Connect the AC line cord to the mating connector at the rear of the unit and power source.

2.3 BATTERY REPLACEMENT

The Model 95 contains a Lithium battery (Panasonic BR-2/3A or equivalent) to power the unit's memory when power is off. This battery life is typically greater than three years. At power on, the Model 95 checks the battery's condition as part of the power-on Self-test. If Self-test detects a low battery, the display shows "LOW BAT X.XXXV". Replace the battery otherwise the contents of the memory could be lost when power is turned off.

To replace the battery,

1. Remove the top cover and shield. Remove the four screws in the top and the one screw at the rear of the cover. Slide the cover back.
2. With the power ON, replace the old battery, as shown in the following illustration, with a new battery. Observe the polarity of the battery when installing it. If the power is turned off while replacing the battery, all contents of the RAM will be lost.

3. Replace the top cover and shield. Secure them using the four screws in the top and the one screw in the rear of the cover.

2.4 FAN MAINTENANCE

The Model 95's fan contains a filter which should be cleaned about every month. Clean the filter more often if the unit is used in a dusty environment.

To clean the Filter,

1. Disconnect the Model 95 from the primary power source.
2. Using a screwdriver, gently pry off the Filter's grill.
3. Remove the foam filter.
4. Clean the foam filter using a mild soapy solution. Thoroughly rinse the filter, and allow it to dry.
5. Place the filter back in the unit, and snap in the Filter's grill.
6. Connect the Model 95 to the primary power source.

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3.1 PERFORMANCE VERIFICATION

Performance verification tests the operation of every selectable parameter and input/output connector. Furthermore, it verifies the correct operation within each major specification. Use this procedure after a manual calibration (section 5) to confirm the units accuracy. All data obtained during the performance verification should be permanently recorded for future reference. The Verification Form, located at the end of this section, can be used as a master to generate copies. This procedure assumes the person making the tests has a good working knowledge of the Model 95's operation. For information on Model 95 operation, refer to the Model 95 Operator's Manual.

Required Test Equipment - Table 3-1 lists the test equipment required to perform the performance verification procedure. Always keep test equipment interconnecting cables as short as possible.

Table 3-1. Required Test Equipment


-	Test Equipment	Recommended Model
	Scope	Tektronix 2465 or equivalent.
•	THD Analyzer	Hewlett Packard 8903B or equivalent.
	DMM	Wavetek Model 1062 or equiva- lent.
	Signal Source	Wavetek Model 23 or equivalent.
	Counter/Timer	Hewlett Packard 5335A or equivalent.
	Phase Meter	Hewlett Packard 3575A or equivalent.
-	Signal Source (Option 001)	Wavetek Model 178 or equivalent
-

Frequency Range

Initialize the Model 95 by pressing the SHIFT and RESET ALL key; see table 3-2 for a list of default parameters.

Table 3-2. Model 95 Default Conditions

Кеу	Condition
Frequency/Sample	1kHz (1ms)
Amplitude	5Vpp (2.5 Vp, 1.768 Vrms,
	18 dBm)
Mode	Continuous
Offset	OV
Symmetry	50%
Store	Last location stored
Recall	Last location stored
Phase	0° (0 radians)
Trigger/Lock Source	Internal
Burst Counter	5
Filter	None
Function	Sine
Sweep Mode	Continuous Sweep
Sweep Start	1kHz
Sweep Stop	10 kHz
Time	1s Sweep
Linear/Logarithmic	Linear Sweep
Trigger Frequency	100 Hz
On/Off (Func Out)	Output Off (50Ω indicator
	flashes)
Select output	50Ω, Unbalanced
Knob	Disabled (ENABLED Indica-
	tor off)
Edit	Edit Off (Arb Not Active)

Note: The following keys are not affected by the RESET ALL key:

Arb Store Calibrate Address Start Address Data Stop Address Smooth Z-Axis Man trigger Local Sync Address GPIB Address Arb Reset Cursors

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2. Connect the Model 95 and test equipment as shown in figure 3-1.

Figure 3-1. Frequency/Symmetry Measurement Setup

3. Program the frequency to the top frequency of each of the top seven decade frequency ranges (Verification Form Frequency Ranges Synthesized Setting) using the FREQ/SAMP key and knob/keypad. Check the synthesized frequency accuracy per the Specified Value, and record the data on the form.
4. Select Continuous mode (MODE key), and set the frequency using the FREQ/SAMP key and knob/keypad(Verification Form - Unlocked FM Settings). Next, change to the FM mode (MODE key) and measure the frequency. Record the results on the form. Repeat the range measurements for all seven upper frequency ranges.
5. Select Continuous mode (MODE key), and set the frequency using the FREQ/SAMP key and knob/keypad(Verification Form - Unlocked Continuous Settings). Measure the frequency, and record the results on the form. Repeat the range measurements for the three lower frequency ranges.

Frequency Resolution

1. Initialize the Model 95 by pressing the SHIFT and RESET ALL key; see table 3-2 for a list of default parameters.

2. Connect the Model 95 and test equipment as shown in figure 3-1.
3. Set the Model 95's frequency as listed in the Verification Form Frequency Resolution Setting using the FREQ/SAMP key and knob/keypad. Check the synthesized frequency accuracy per the Specified Value, and record the data on the form.

Symmetry

Initialize the Model 95 by pressing the SHIFT and RESET ALL key; see table 3-2 for a list of default parameters.
. Connect the Model 95 and test equipment as shown in figure 3-1.
3. Program the symmetry as listed in the Verification Form - Symmetry Settings using the SHIFT and SYMMETRY keys and knob/keypad. Check the symmetry accuracy per the Specified Value. The specified value represents the time in µs for the the negative half of the cycle. Record the data on the form.

VCG/FM

. Initialize the Model 95 by pressing the SHIFT and RESET ALL key; see table 3-2 for a list of default parameters.
2. Connect the Model 95 and test equipment as shown in figure 3-2.
Set the signal source for 0 Volts dc output. Set the Model 95 for FM mode (MODE key). Measure the Center Frequency (Verification Form -VCG/FM Setting Cener Frequency) as per the Specified Value (1kHz ± 3% frequency), and record the data on the form.

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Set the signal source for +5 Volts dc output. Measure the Deviation Frequency (Verification Form - VCG/FM Setting Cener Frequency) as per the Specified Value (2kHz±3%), and record the data on the form.

Waveforms

1. Initialize the Model 95 by pressing the SHIFT and RESET ALL key; see table 3-2 for a list of default parameters. Press the ON/OFF key to turn on the output.
- 2. Connect the Model 95 and test equipment as shown in figure 3-3. Connect the Model 95's SYNC OUT to the scope's trigger input.
- 3. Set the Model 95 to the sine function (FUNC-TION key). Verify the scope displays the sine wave (Verification Form - Waveform Setting Sine Wave), and record the results as per the Specified Value (Yes or No) on the form. Repeat this step for the triangle and square waves, as well as dc (Verification Form - Waveform Setting Triangle Wave, Square Wave, and DC).

Arbitrary Waveform and Z-Axis Output

1. Initialize the Model 95 by pressing the SHIFT and RESET ALL key; see table 3-2 for a list of default parameters. Press the ON/OFF key to turn on the output.
Connect the Model 95 and test equipment as shown in figure 3-3. Connect the Model 95's SYNC OUT to the scope's trigger input. Connect the Z-AXIS output, located on the rear of the Model 95, to the Z-Axis input on the scope.
3. Set the Model 95 to the ARB1 function (FUNC-TION key). Press the SHIFT and ARB RESET keys to initialize the active RAM. This will not alter the Arb waveform stored in ARB1. The Arb

reset places the start address and left cursor at 0 and the stop address and right cursor at 100.

Use the EDIT key to select "BLOCK EDIT +SINE". Select the Z-Axis (Z-AXIS key), and use the knob to step through the Z-Axis settings. Rotate the knob until the scope displays the highlighted cursors. Record the results (Record Yes or No) on the form (Verification Form - Arb Waveform and Z-Axis Output Setting Z-Axis).
5. Press EDIT key to return to the edit display. Press ENTER to place a digitized sine wave between the left and right cursors. Verify the scope displays the digitized sine wave, and record the results on the form (Verification Form - Arb Waveform and Z-Axis Output Setting Digitized Sine Wave).
6. To keep from replacing the waveform stored in ARB1 with the sine wave, select "ARB RE-STORE" using the EDIT key.and press ENTER to revert to the original ARB1 waveform.

Sweep

1. Initialize the Model 95 by pressing the SHIFT and RESET ALL key; see table 3-2 for a list of default parameters. Press the ON/OFF key to turn on the output.
2. Connect the Model 95 and test equipment as shown in figure 3-3. Connect the Model 95's SYNC OUT to the scope's trigger input.
3. Set the Model 95 to the Sweep Mode (MODE key). Set the Sweep Mode to Continuous Sweep (SWEEP MODE key). Verify the scope displays a sweep output (1kHz to 10 kHz, 1 second sweep), and record the results on the

Figure 3-3. Waveforms/Sweep Verification

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Figure 3-4. Trigger Measurement Setup

form (Verification Form - Sweep Setting Sweep Output).

Connect the Sweep Out to the scope input. Verify the scope displays a 1 second sweep ramp (600Ω impedance), and record the results on the form (Verification Form - Sweep Setting Sweep Ramp).

Continuous Mode

1. Initialize the Model 95 by pressing the SHIFT and RESET ALL key; see table 3-2 for a list of default parameters. Press the ON/OFF key to turn on the output.
2. Connect the Model 95 and test equipment as shown in figure 3-3. Connect the Model 95's SYNC OUT to the scope's trigger input.
3. Verify the scope displays a continuous 5Vpp sine wave. Record the results (Record Yes of No) on the form (Verification Form - Continuous Mode Setting Continuous 5Vpp Sine).

Triggered Mode

1. Initialize the Model 95 by pressing the SHIFT and RESET ALL key; see table 3-2 for a list of default parameters. Press the ON/OFF key to turn on the output.
Connect the Model 95 and test equipment as shown in figure 3-4. Connect the Model 95's SYNC OUT to the scope's trigger input.
3. Set the Model 95 to the (Internal) Triggered mode (MODE key). Internal trigger is the default. Verify the scope displays an internally triggered 5Vpp sine wave. Record (Record Yes or No) the results on the form (Verification Form - Triggered Mode Setting Internal Triggered Sine Wave).
4. Set the Model 95 to the External Triggered

mode (TRIG/LOCK key). Set the signal source for a 100 Hz TTL square wave. Connect the signal source to the TRIG/FREQ IN connector. Synchronize the scope off the signal source.

5. Verify the scope displays an externally triggered 5Vpp sine wave. Record (Record Yes or No) the results on the form (Verification Form -Triggered Mode Setting External Triggered Sine Wave).

Gated Mode

1. Initialize the Model 95 by pressing the SHIFT and RESET ALL key; see table 3-2 for a list of default parameters. Press the ON/OFF key to turn on the output.
2. Connect the Model 95 and test equipment as shown in figure 3-4. Connect the Model 95's SYNC OUT to the scope's trigger input.
3. Set the Model 95 to the (Internal) Gate mode (MODE key). Internal gate is the default. Verify the scope displays an internally gated 5Vpp sine wave. Record (Record Yes or No) results on the form (Verification Form - Gate Mode Setting Internal Gated Sine Wave).
4. Set the Model 95 to the external triggered gate mode (TRIG/LOCK key). Set the signal source for a 100 Hz TTL square wave. Connect the signal source to the TRIG/FREQ IN connector. Synchronize the scope off the signal source.
5. Verify the scope displays an externally gated 5Vpp sine wave. Record (Record Yes or No) the results on the form (Verification Form - Gate Mode Setting External Gated Sine Wave)..

Burst Mode

. Initialize the Model 95 by pressing the SHIFT and RESET ALL key; see table 3-2 for a list of

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default parameters. Press the ON/OFF key to turn on the output.

Connect the Model 95 and test equipment as shown in figure 3-4. Connect the Model 95's SYNC OUT to the scope's trigger input.
3. Set the Model 95 to the (Internal) Burst mode (MODE key). Internal burst is the default. Verify the scope displays an internal triggered burst of 5, 5Vpp sine waves. Record (Record Yes or No) the results on the form (Verification Form -Burst Mode Setting Internal Burst Sine Wave).
4. Set the Model 95 to the external triggered burst mode (TRIG/LOCK key). Set the signal source for a 100 Hz TTL square wave. Connect the signal source to the TRIG/FREQ IN connector. Synchronize the scope off the signal source.
- Verify the scope displays an externally triggered burst of 5, 5Vpp sine waves. Record (Record yes or No) the results on the form (Verification Form - Burst Mode Setting External Gated Sine Wave).

Square Wave/Sync Out Transition Time

1. Initialize the Model 95 by pressing the SHIFT and RESET ALL key; see table 3-2 for a list of default parameters. Press the ON/OFF key to turn on the output.
2. Connect the Model 95 and test equipment as shown in figure 3-3. The Unbalanced Output must be terminated into a 50Ω feed-thru termination.
3. Set the Model 95 for 10 MHz square wave (FREQ/SAMP key and FUNCTION key). Measure rise time, fall time, positive-going transition peak-to-peak aberration in percent and negative-going transition peak-to-peak aberration in percent. Check the transition time and aberration as per the Specified Values, and record the results on the form (Verification Form - Square Wave/Sync Out Transition Time Unbalaced Output Setting Rise Time, Fall Time, Positive Transition % aberration, and Negative Transition Time % aberation).
4. Connect the Sync Out to the scope, and measure the peak-to-peak amplitude, rise time and fall time. Check the transition time as per the Specified Values, and record the results on the

form (Verification Form - Square Wave/Sync Out Transition Time Sync Out Setting Rise Time and Fall Time).

Outputs

1. Initialize the Model 95 by pressing the SHIFT and RESET ALL key; see table 3-2 for a list of default parameters. Press the ON/OFF key to turn on the output.
2. Connect the Model 95 and test equipment as shown in figure 3-3.
Set the Model 95 for 50Ω, 75Ω and 600Ω output impedance (SHIFT and SELECT key). The Unbalanced Output must be terminated into a matching feed-thru termination. Verify the scope displays the normal waveform and amplitude into matching terminations (Verification Form - Outputs Unbalanced Output Setting 50Ω, 75Ω, and 600Ω). Record (Record Yes or No) the results on the form.
4. Connect the Model 95 and test equipment as shown in figure 3-5.

Figure 3-5. Balanced Output Setup

5. Synchronize the scope off channel 1. Place a 135Ω load resistor across the Balanced Output terminals. Select the Model 95's 135Ω Balanced Output (SHIFT and SELECT keys). Verify the scope displays on channel 1 and 2, two sine waves 180° out of phase. The amplitude of each sine wave will be one half of the Unbalanced Out sine wave (step 3). Record (Record Yes or No) the results on the form (Verification Form Outputs Balanced Output Setting 135Ω).
6. Select the Balanced 600Ω Output. Place a 600Ω load resistor across the Balanced Output. Verify the scope displays on channel 1 and 2, two sine waves 180° out of phase. The

Page 20

amplitude of each sine wave will be one half of the Unbalanced Out sine wave (step 3). Record (Record Yes or No) the results on the form (Verification Form - Outputs Balanced Output Setting 135Ω).

Amplitude Modulation

1. Initialize the Model 95 by pressing the SHIFT and RESET ALL key; see table 3-2 for a list of default parameters. Press the ON/OFF key to turn on the output.
2. Connect the Model 95 and test equipment as shown in figure 3-6.
Set the signal generator for a 1kHz, 2.7 Vpp (open circuit) sine wave. Set Model 95 for 100 kHz (FREQ/SAMP key and knob/keypad) and the AM mode (MODE key). Verify the scope displays normal amplitude modulation of approximately 100%. Record (Record Yes or No) the results on the form (Verification Form -Amplitude Modulation Setting 100% AM).

Suppressed Carrier

1. Initialize the Model 95 by pressing the SHIFT and RESET ALL key; see table 3-2 for a list of default parameters. Press the ON/OFF key to turn on the output.
2. Connect the Model 95 and test equipment as shown in figure 3-6.
3. Set Model 95 to the SCM mode (MODE key). With the MOD IN signal disconnected, verify the scope displays no output. Record the results on the form.
Set the signal source for +2Vdc. Connect the signal source output to the Model 95's MOD IN. Verify the scope displays a 4Vpp sine wave. Record (Record Yes or No) the results on the form (Verification Form Suppressed Carrier Modulation Setting 4Vpp SCM).

Sine Wave Purity

1. Initialize the Model 95 by pressing the SHIFT and RESET ALL key; see table 3-2 for a list of default parameters. Press the ON/OFF key to turn on the output.
2. Connect the Model 95 and test equipment as shown in figure 3-7.

Figure 3-7. Sine Purity Setup

3. Measure the sine total harmonic distortion in dB. Measure the sine wave purity, and Record the results on the form (Verification Form - Sine Wave Purity Setting THD at 1kHz).

Amplitude Accuracy

Initialize the Model 95 by pressing the SHIFT and RESET ALL key; see table 3-2 for a list of default parameters. Press the ON/OFF key to turn on the output.
2. Connect the Model 95 and test equipment as shown in figure 3-8.

Figure 3-8. Amplitude Accuracy Setup

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3. Set the amplitude as listed in the Verification Form - Amplitude Accuracy Sine Wave Setting using the AMPLITUDE key and knob/keypad. Measure the amplitude accuracy per the Specified Value, and record the data on the form.
4. Set the Model 95's function to Triangle wave (FUNCTION key). Set the amplitude as listed in the Verification Form - Amplitude Accuracy Triangle Wave Setting using the AMPLITUDE key and knob/keypad. Measure the amplitude accuracy per the Specified Value, and record the data on the form.
5. Set the Model 95's function to Square wave (FUNCTION key). Set the amplitude as listed in the Verification Form - Amplitude Accuracy Square Wave Setting using the AMPLITUDE key and knob/keypad. Measure the amplitude accuracy per the Specified Value, and record the data on the form.

DC Output and Attenuator Accuracy

1. Initialize the Model 95 by pressing the SHIFT and RESET ALL key; see table 3-2 for a list of default parameters. Press the ON/OFF key to turn on the output.
2. Connect the Model 95 and test equipment as shown in figure 3-8.
3. Set the Model 95 to the DC function (FUNC-TION key), and program the dc offset (OFFSET key and keypad/knob) as listed in the Verification Form - DC Output Setting. Measure the dc offset accuracy as per the Specified Value.

Record the data on the form.

External Lock

1. Initialize the Model 95 by pressing the SHIFT and RESET ALL key; see table 3-2 for a list of default parameters. Press the ON/OFF key to turn on the output.
2. Connect the Model 95 and test equipment as shown in figure 3-9, except leave the signal source disconnected.
3. Set the Model 95 to external lock (TRG/LOCK SOURCE key). Verify the Model 95 displays EXTLOC, the UNLOCK indicator flashes, and EXT indicator remains lit. Record (Record Yes or No) the results on the form (Verification Form - External Lock Setting Source Disconnected).
4. Set the signal source for a 10 kHz, 5Vpp sine wave. Connect the signal source to the Model 95's TRIG/FREQ IN connector. Verify the Model 95 displays EXTLOC 10.00 KHZ (approximate reading), UNLOCK indicator remains off, and the EXT indicator remain lit. Record (Record Yes or No) the results on the form (Verification Form External Lock Setting Source Connected). The Model 95 automatically changes its frequency to match the frequency of the external source.
5. Set the Model 95 phase shift as listed in Verification Form - External Lock Phase Shift Setting. Measure the phase angle as per the Specificed Value, and record results on the form.

Figure 3-9. External Lock Measurement

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Front Panel

Did the annunciators and the display perform correctly during the Verification Procedure. If so, record the results on the form.

Option 001 - High Frequency Stability Reference

Perform the following checks only if the Model 95 contains an Option 001.

1. Turn the Model 95s Power on.
2. Connect the Model 95's REF OUT, located on the rear panel, to a Counter/Timer.
3. Verify the REF OUT frequency (TCXO freq) measures within the Specified Value on the Verification Form. Record the results on the form.
4. Connect the Model 95's REF IN, located on the rear panel, to a signal source. Set the signal source (178 Freq) to 10.001 MHz, 1Vrms sine wave (always properly terminate the signal source). Measure the REF OUT frequency (Ref Out) as per the Specified Value, and record the results on the form.

Parameter	Low Limit	High Limit
TCXO Freq	9,999,990 Hz	10,000,010 Hz
178 Freq	10,000,000 Hz	10,002,000 Hz
Ref Out	178 Freq - 2 Hz	178 Freq + 2 Hz

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VERIFICATION FORM

	Date	Technician		Serial No
	Frequency Ranges Synthesized
	Settings	Data Becord
	20 MHz	Bala necola
	2 MHz
	200 kHz		IVII 12 kHz	100 008 to 200 002 MINZ
_	20 kHz		KHZ	199.990 to 200.002 kHz
_	2 kHz		kHz	1 9998 to 2 00002 kHz
	200 Hz		N 12 Hz	100 008 to 200 002 kl 12
	20 Hz		Hz	199.990 10 200.002 Hz
			112	19.9990 to 20.0002 Hz
	Linlockod - EM
	Sottings	Data Depart
		Dala Record	N 41 1
			MHZ	19.4 to 20.6 MHz
				1.94 to 2.06 MHz
			KHZ	194 to 206 kHz
			KHZ	19.4 to 20.6 kHz
			KHZ	1.94 to 2.06 kHz
			HZ	194 to 206 Hz
	20.00 HZ		Hz	19.4 to 20.6 Hz

	Unlocked -Continuous
	Settings	Data Record		Specified Value
	2.000 Hz		Hz	1.94 to 20.6 Hz
	200.0 mHz		Hz	194 to 206 mHz
	20.00 mHz		mHz	19.4 to 20.6 mHz

	Frequency Resolution
	Settings	Data Record		Specified Value
	1999 Hz		Hz	1998.98 to 1999.02 Hz
	1888 Hz		Hz	1887.98 to 1888.02 Hz
	1777 Hz		Hz	1776.98 to 1777.02 Hz
	1666 Hz		Hz	1665.98 to 1666.02 Hz
	1555 Hz		Hz	1554.98 to 1555.02 Hz
	1444 Hz		Hz	1443.99 to 1444.01 Hz
	1333 Hz		Hz	1332.99 to 1333.01 Hz
•	1222 Hz		Hz	1221.99 to 1222.01 Hz
	1111 Hz		Hz	1110.99 to 1111.01 Hz
	999 Hz		Hz	998.99 to 999.01 Hz
-	888 Hz		Hz	887.991 to 888.009 Hz
	777 Hz	·····	Hz	776.992 to 777.008 Hz
	666 Hz		Hz	665.993 to 666.007 Hz
	555 Hz		Hz	554.994 to 555.006 Hz
_	444 Hz		Hz	443.996 to 333.003 Hz

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_____ H7

_____ Hz

_____μs

_____Hz

_____μs

Data Record

333 Hz 222 Hz

Symmetry Settings

10% Symmetry
20% Symmetry
30% Symmetry
40% Symmetry
50% Symmetry
60% Symmetry
70% Symmetry
80% Symmetry
90% Symmetry

VCF/FM

Se	ttin	ıg
~		-

Center Frequency Deviation Frequency

waveforms
Setting	Data Becord
Sine Wave
Triangle Wave
Square Wave

Arb Waveform and Z-Axis Output Setting Data Record

Z-Axis Digitized Sine Wave

Sweep Setting Sweep Output Sweep Ramp

Data Record

Continuous Mode Setting Continuous 5Vpp Sine

Triggered Mode Setting Internal Triggered Sine Wave External Triggered Sine Wave

Gate Mode Setting Internal Gated Sine Wave External Gated Sine Wave

Data Record

-----

Data Record

332.997 to 333.003 Hz 221.998 to 222.002 Hz

Specified Value

99 to 101 μs 198 to 202 μs 297 to 303 μs 396 to 404 μs 495 to 505 μs 594 to 606 μs 693 to 707 μs 792 to 808 μs 891 to 908 μs

Specified Value

970 to 1030 Hz 1900 to 2100 Hz

Specified Value

Record: Yes or No Record: Yes or No Record: Yes or No Record: Yes or No

Specified Value

Record: Yes or No Record: Yes or No

Specified Value

Record: Yes or No Record: Yes or No

Specified Value

Record: Yes or No

Specified Value Record: Yes or No Record: Yes or No

3-10

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	Burst Mode Setting Internal Burst Sine Wave External Burst Sine Wave	Data Record		Specified Value Record: Yes or No Record: Yes or No
	Square Wave/Sync Out Trans Unbalanced Output	ition Time
,	Setting Rise Time Fall Time	Data Record	_ns	Specified Value
	Pos. Trans. % aberration Neg. Trans. % aberration		_ 113 _ % _ %	< 5.2% < 5.2%
	Setting Rise Time	Data Record	_ns	Specified Value
			_ 115
	Setting 50Ω (5Vpp Sine Wave) 75Ω (5Vpp Sine Wave)	Data Record	-	Specified Value Record: Yes or No Record: Yes or No
	600Ω (5Vpp Sine Wave			Record: Yes or No
	Setting 135Ω (180°, 5Vpp Sine Wave) 600Ω (180°, 5Vpp Sine Wave)	Data Record		Specified Value Record: Yes or No Record: Yes or No
	Amplitude Modulation Setting 100% AM	Data Record	-	Specified Value Record: Yes or No
	Suppressed Carrier Modulatic Setting 4Vpp SCM	on Data Record	-	Specified Value Record: Yes or No
	Sine Wave Purity Setting THD at 1 kHz	Data Record	_ dB	Specified Value ≤ – 48 dB (0.5%)
	Amplitude Accuracy Sine Wave
	Setting 1.11 Vpp 2.22 Vpp	Data Record	_ Vrms _ Vrms	Specified Value 0.38105 to 0.40375 Vrms 0.7657 to 0.8041 Vrms
	з.33 vpp 4.44 Vpp		_ vrms _ Vrms	1.5351 to 1.6049 Vrms

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5.55 Vpp	Vrms
6.66 Vpp	Vrms
7.77 Vpp	Vrms
8.88 Vpp	Vrms
9.99 Vpp	Vrms
15.0 Vpp	Vrms

Data Docord

Triangle Wave


1.11 Vpp	Vrms
2.22 Vpp	Vrms
3.33 Vpp	Vrms
4.44 Vpp	Vrms
5.55 Vpp	Vrms
6.66 Vpp	Vrms
7.77 Vpp	Vrms
8.88 Vpp	Vrms
9.99 Vpp	Vrms
15.0 Vpp	Vrms
• •

Square Wave

Setting	Data Record
1.11 Vpp Square	Vrms
2.22 Vpp Square	Vrms
3.33 Vpp Square	Vrms
1.44 Vpp Square	Vrms
5.55 Vpp Square
5.66 Vpp Square	Vrms
7.77 Vpp Square	Vrms
3.88 Vpp Square	Vrms
9.99 Vpp Square	Vrms
15.0 Vpp Square	Vrms

DC Output

Setting	Data Record
+7.499V
0V	Vdc
-7.499V	Vdc

External Lock

Source Disconnected Source Connected

Data Record

_____

1.91926 to 2.00474 Vrms 2.3044 to 2.4056 Vrms 2.68856 to 2.80544 Vrms 3.07370 to 3.20630 Vrms 3.45786 to 3.60614 Vrms 5.19344 to 5.41256 Vrms

Specified Value

0.31109 to 0.32971 Vrms 0.62518 to 0.65662 Vrms 0.93917 to 0.98343 Vrms 1.25346 to 1.31054 Vrms 1.56706 to 163694 Vrms 1.88164 to 1.96436 Vrms 2.19524 to 2.29076 Vrms 2.50884 to 2.61716 Vrms 2.82342 to 2.94458 Vrms 4.24050 to 4.41950 Vrms

Specified Value

0.53890 to 0.57110 Vrms 1.08280 to 1.13720 Vrms 1.62670 to 1.70330 Vrms 2.17060 to 2.26940 Vrms 2.71450 to 2.83550 Vrms 3.25840 to 3.40160 Vrms 3.80230 to 3.96770 Vrms 4.34620 to 4.53380 Vrms 4.89010 to 5.09990 Vrms 7.34500 to 7.65500 Vrms

Specified Value

+7.415 to +7.585 Vdc -0.001 to +0.001 Vdc -7.585 to -7.415 Vdc

Specified Value

Record: Yes or No Record: Yes or No

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Phase Shift
Setting	Data Record		Specified Value
0° Phase	°		-4° to +4°
+90° Phase	•		+86° to +94°
+180° Phase	°		+176° to +184°
–90° Phase	•		–94° to –86°
-180° Phase	• •		-184° to -176°
Front Panel
	Data Record		Specified Value
Display/Annunciators			Record: Yes or No
Option 001 - High Freque	ncv Stability Reference
Setting	Data Record		Specified Value
TCXO Freq	Н	z	9.999.990 to 10.000.010 Hz
178 Freq	Н	Z	10,000,000 to 10,002,000 Hz

Ref Out

3-13

178 Freq - 2 to 178 Freq + 2 Hz

Page 28

Page 29

SECTION 4 CALIBRATION PROCEDURE

4.1 CALIBRATION

Wavetek maintains a factory Customer Service department for those customers not possessing the necessary personnel or test equipment to calibrate or repair the instrument. Before returning the instrument, contact the Customer Service Department by calling or writing:

Wavetek San Diego, Inc. 9045 Balboa Ave. San Diego, CA 92123 Telephone: (619) 279-2200 TWX: (910) 335-2007 FAX (619) 565-9558

The Model 95 provides the user with two calibration methods: Autocal and Calibrate.

4.1.1 Autocal

Autocal (automatic calibration) provides a quick method of calibrating the Model 95 without using external test equipment. Autocal automatically sets up the instrument and takes internal measurements using internal standards. The Model 95 calculates correction values and stores those values in memory. These correction values are recalled from memory when the unit is powered up. Use Autocal when Model 95 accuracy is critical, after long term instrument storage, following drastic changes in the environment, or when the operator believes Autocal is necessary.

4.1.2. Calibration Procedure

The Calibration Procedure provides a more extensive method of calibration. The Calibration Procedure uses external test equipment and requires opening the instrument and making adjustments. Use the Calibration Procedure when the Model 95 displays "CAL RE-QUIRED" or "FAILED AUTOCAL", when the Model 95 has been repaired, fails the Performance Verification procedure (Section 3), or when routine calibration is scheduled. Paragraph 4.3 describes the Calibrate procedure. The adjustment values given in the calibration procedure are not necessarily the specified values. This calibration procedure will erase the contents of the Arb active memory.

4.2 AUTOCAL PROCEDURE

To Autocal the Model 95, perform the following steps. Autocal requires no external test equipment. In fact, no test equipment should be connected to the Model 95's input connectors, otherwise the Autocal circuitry could alter the calibration of the instrument. Also, disconnect all outputs from the instrument otherwise the sudden changes in the instrument's output waveforms could damage external equipment.

1. Turn on the Model 95 and allow it to warm up for 20 minutes. Pressing the CaliBRATE key during the 20 minute warm up time displays the count-down time, after the 20 minutes the Modei 95 begins Autocal. Pressing any other key during the count down aborts Autocal and returns the instrument to normal operation.

Remember to remove all input and output connections to the Model 95 before pressing Autocal.

2 After a 20 minute warm up, press the CallBRATE key (SHIFT and CALIBRATE) and allow the unit time to complete the Autocal cycle. While running AutoCal.the Model 95 displays "CALIBRATING". When completed successfully, the Model 95 displays "AUTOCALIBRATED". Then the unit returns to its last operational setup. If the Autocal fails the Model 95 displays an error message which identifies the parameter - FRR (Keyword): for example ERR VSINCAL. If this occurs occasionally, try to Calibrate the unit again. Note the error keywords and report the errors when the unit is returned for scheduled maintenance. Refer to paragraph 6.7.6 for a listing of error . messages.

4.3 CALIBRATION PROCEDURE

The Model 95 Calibration Procedure contains a series of steps which the Model 95 will guide you through. During this procedure, the Model 95 automatically sets itself to the right conditions. Some calibration steps

Page 30

may require you to make changes using front panel controls.

CAUTION

Performing the Calibrate Procedure will erase the contents of the active Arb memory. To store the Arb waveform in the Arb waveform memory, refer to paragraph 3.5.20 of the Model 95 Operator's Manual.

Table 4-1. Recommended Test Equipment

Requirements
Tektronix Model 2465 or
equivalent
Hewlett Packard 8903B or
equivalent.
Wavetek Model 1062 or
equivalent.
Wavetek Model 23 or
equivalent.
Hewlett Packard 5335A or
equivalent.
Hewlett Packard 3575A or
equivalent.

NOTE Use rear panel for all ground connections unless otherwise specified. All indications and waveforms are referenced to chassis ground unless otherwise specified.

Adjustments

Throughout this procedure are illustrations identifying the adjustments used in the steps. For a detailed view of the adjustment locations, refer to the assembly drawings located in section 7 of this manual. Figure 4-1 shows the individual board locations.

Keys

While performing the Calibration Procedure, the following keys perform the following functions.

CALIBRATE	Pressing this key during the Cali- bration Procedure will turn off the Calibration mode.
RESET	During the Calibration Procedure, this key resets all the calibration factors to their default values.
TRIG FREQ	During the Calibration Procedure, this key functions as the forward cursor. Pressing the TRIG FREQ key advances the procedure to the next calibration step.
MAN TRIG	During the Calibration Procedure, this key functions as the reverse cursor. Pressing the MAN TRIG key backs the procedure up to the previous calibration step.

MODEL 95

SW1
MOTHERBOARD
ARB BOARD
FUNCTION GENERATOR BOARD
PLL BOARD
OUTPUT BOARD


Figure 4-1. Board Locator

Page 31

KNOB During the Calibration Procedure, the KNOB is used to change and enter calibration data. It is also used to alternate between two functions in some steps.
- KEYPAD During the Calibration Procedure, the numeric keypad is used to enter calibration data.
  - ENTER Use the ENTER key to accept data entered using the numeric key-pad.

Calibration Cover

A calibration cover can be used when performing the calibration procedure. This cover replaces the Model 95s normal cover and helps maintain the unit's internal temperature while allowing access to the calibration adjustments. For more information on the calibration cover, contact Wavetek's Customer Service department

Wavetek San Diego, Inc. 9045 Balboa Ave. San Diego, CA 92123 Telephone: (619) 279-2200 TWX: (910) 335-2007 FAX (619) 565-9558

Precalibration Setup

Before beginning calibration, disconnect the Model 95 from its power source and remove five top cover screws. Slide the top cover off, and remove the inner shield. Slide the top cover back on to stabilize the unit's internal temperature.

NOTE

Keep the top cover in place during the procedures except when necessary to make an internal adjustment.

2. Perform the turn-on procedures as described in paragraph 2.4.3 of the Model 95 Operator's Manual.

WARNING

Dangerous voltages are present with the covers removed. Where maintenance can be performed without power applied, the power should be removed. Battery voltage is present even with AC power cable removed.

3. Connect the Model 95 to the power source, turn the power on, and allow the unit to warm up for 20 minutes (minimum).

Step 1 Adjust Frequency Reference

If calibrating a standard Model 95 (one without Option 001, TCXO Frequency Reference) perform items 1 through 4 of this step. If Option 001 is installed perform items 1, 5, and 6.

1. After warm up, reset the Model 95 by pressing the Model 95's SHIFT and RESET ALL keys.
2. Connect the test equipment as shown in figure 4-2.

Figure 4-2. Frequency Reference Setup

3. Set up the Model 95 for a 1MHz output by pressing the FREQ/SAMP, 1 EXP 6, and ENTER keys. Press ON/OFF to turn on the output.
Measure the frequency at the Sync Out connector. Verify the counter reads 1MHz ±5Hz. If incorrect, slide the cover back, adjust C21 (see figure 4-3) until the counter reads 1MHz ±5Hz, and then slide the cover back on.

If the Option 001, TCXO Frequency Reference is installed, perform item 1 of this step and continue on using the following steps.

5. Connect the counter/timer to the Model 95's REF OUT connector, located on the rear panel.
6. Measure the frequency at the REF OUT connector. Verify the counter reads 10 MHz ±2Hz.

Page 32

If incorrect, turn off the Model 95 and slide the cover back. Place the Arb board on an extender card. Turn the power back on. Remove the sticker from the TCXO and adjust the trimmer (see figure 4-3) until the counter reads 10 MHz ±2Hz.

When finished, turn off the power, replace the sticker on the TCXO, remove the extender card, and place the Arb board back in the unit. Slide the cover on. Then turn on the power.

Step 2 Initial Steps

1. After the unit is warmed up (20 minutes) slide the top cover back. Press and hold down the internal calibration switch SW1 (figure 4-3) while pressing the SHIFT and CALIBRATE keys.

Slide the cover back on.

2. Verify the Model 95 display shows WVTK SN XXXXXX or WVTK SNO. XXXXXXX represent the unit's serial number. If necessary, enter the unit's serial number using the keypad; the unit's serial number is located on the rear panel label. Press the front panel TRIG FREQ key to step to USER SN XXXX. To enter a user serial number, use the keypad.
3. Verify the Model 95 display flashes CALI-BRATING and then shows USER SN XXXX or USER SN 0. USER SN allows the calibrator to enter an identification number using the keypad. Press the TRIG FREQ key to advance to R33,97, VSINE XXX. Pressing the TRIG FREQ key also stores the User Number.

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Page 34

wave signal null. Slide the top cover back on.

4. Press the TRIG FREQ key to step to TRI NULL R25 2.

Step 5 Null Triangle

1. The Model 95 displays TRI NULL R25 2. Connect test equipment as shown in figure 4-8. Set the DVM to measure Vdc.
2. The DVM measures the dc offset value of the 2Vpp triangle.
3. Rotate the Knob on the Model 95 until display shows TRI NULL R25 15. The DVM measures the dc offset value of the 15 Vpp triangle.
4. Use the Knob to move between "2" and "15".

Figure 4-8. Triangle Null Setup

Slide the cover back, and adjust the Output board's R25 (see figure 4-9) until the dc offset change between 2 and 15 is less than 2mV at both amplitudes. Slide the cover back on.

5. Press the TRIG FREQ key to advance to the next step. Verify the display flashes CALI-BRATING and then shows TRI OFFSET R146.

Step 6 Adjust Triangle Offset

The Model 95 displays TRI OFFSET R146. Leave the test equipment connected as shown in figure 4-8.
2. Slide the cover back, and adjust the Output board's R146 (see figure 4-10) until the DVM reads 0Vdc ±2mVdc of triangle offset. Slide the cover back on.
3. Press the TRIG FREQ key to advance to the next step. Verify the display flashes CALI-BRATING then shows SINE NULL R64.

Step 7 Null Sine Wave

1. The Model 95 displays SINE NULL R64. Leave the test equipment connected as shown in figure 4-8.
Slide the cover back, and adjust the PLL board's R64 (see figure 4-11) until the DVM reads 0Vdc ±2mVdc of sine offset. Slide the cover back on.

Page 35

1 The Model 95 displays ARB NULL NF XX where XX represent a calibration value. Leave the test equipment connected as shown in figure 4-8
On the Model 95, adjust the Model 95s front panel Knob for 0Vdc ±2mVdc.
3 On the Model 95, press the TRIG FREQ key to advance to the next step. Pressing TRIG FREQ key stores the calibration value in internal memory. Verify the display flashes CALI-BRATING then shows ARB NULL 50K XX.

Step 9 Null Arb - 50 kHz Filter

1. The Model 95 displays ARB NULL 50K XX. Leave the test equipment connected as shown in figure 4-8.
On the Model 95, adjust the Model 95s front panel Knob for 0Vdc ±2mVdc.
3 On the Model 95, press the TRIG FREQ key to advance to the next step. Pressing TRIG FREQ

Verify the display flashes CALIBRATING then

Step 10 Null Arb - 5MHz Filter

The Model 95 displays ARB NULL 5M XX where XX represents a calibration value 1 eave the test equipment connected as shown in figure 4-8.
2 On the Model 95, adjust the Model 95s front panel Knob for OVdc +2mVdc
3. On the Model 95, press the TRIG FREQ key to advance to the next step. Pressing TRIG FREQ key stores the calibration value in internal memory. Verify the display flashes CALIBRAT-ING then shows SOLIABE 0 B158

Step 11 Null Square

1 The Model 95 displays SQUARE 0 R158. Leave the test equipment connected as shown in figure 4-8.
2 Slide the cover back, and adjust the Output board's R158 (see figure 4-12) until the DVM reads 0Vdc +2mVdc of square offset. Slide the cover back on

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Figure 4-12. R158 Locator
Press the TRIG FREQ key to advance to the next step. Verify the display flashes CALI-BRATING then shows TRI AMPL R211 1.

Step 12 Adjust Triangle Amplitude

1. The Model 95 displays TRI AMPL R211 1. Connect test equipment as shown in figure 4-13 and set the scope to measure Vdc. Note the amplitude of the triangle wave.

Figure 4-13. Triangle Amplitude Setup

2. On the Model 95, rotate the Knob until display shows TRI AMPL R211 2. Note the amplitude of the square wave.

3. Use the Knob to step between the triangle and square waves. Slide the cover back. Adjust R211 (see figure 4-14) on the PLL board until the peak to peak amplitude of the triangle matches the peak to peak amplitude of the square wave. Slide the cover back on.
4. Press the TRIG FREQ key to advance to the next step. Verify the display flashes CALI-BRATING then shows SIN AMPL R208 0.

Step 13 Adjust Sine Amplitude

1. The Model 95 displays SIN AMPL R208 0. Leave the test equipment connected as shown in figure 4-13.
2. On the Model 95, rotate the front panel Knob until display shows SIN AMPL R208 2. Note the amplitude of the square wave.
3. Use the Knob to step between the sine and square waves. Slide the cover back. Adjust R208 on the PLL board (see figure 4-15) until the peak to peak amplitude of the sine wave matches the peak to peak amplitude of the square wave. Slide the cover back on.
4. Press the TRIG FREQ key to advance to the next step. Verify the display flashes CALI-BRATING then shows HF SYM R9.

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Figure 4-18. Phase Setup

Step 16 Adjust Phase 0°

1. The Model 95 displays PHASEOY XXXXX where XXXXX represents a calibration value. Connect the test equipment as shown in figure 4-18. Appendix B contains an alternate method of calibrating phase using a scope.
2. Set the signal source controls as follows: Set Function to Sine. Frequency to 2.01 kHz. Output Level to 5Vpp.
On the Model 95, Adjust the Knob to until the phase meter read 0°. Press the TRIG FREQ key. Verify that the display flashes CALIBRATING for then displays PHASE+180Y XXXXX. Pressing TRIG FREQ key stores the calibration value in internal memory

Step 17 Adjust Phase +180°

1. The Model 95 displays PHASE+180Y XXXXX where XXXXX represents a calibration value. Leave the test equipment connected as shown in figure 4-18. Do not change the signal source. Appendix B contains an alternate method of calibrating phase using a scope.
2. On the Model 95,

Adjust the Knob to until the phase meter reads +180°.

Press the TRIG FREQ key advance to the next step. Verify the display flashes CALIBRATING and then displays PHASE–180Y XXXXX. Pressing TRIG FREQ key stores the calibration value in internal memory.

Step 18 Adjust Phase -180°

1. The Model 95 displays PHASE-180Y XXXXX where XXXXX represents a calibration value. Leave the test equipment connected as shown in figure 4-18. Do not change the signal source. Appendix B contains an alternate method of calibrating phase using a scope.

2. On the Model 95,

Adjust the Knob to until the phase meter reads -180° Press TRIG FREQ key to advance to the next step. Verify that the display flashes CALIBRATING and then displays SQ PHASE 0 XXXXX. Pressing TRIG FREQ key stores the calibration value in internal memory.

Step 19 Adjust Square Phase 0°

1. The Model 95 displays SQ PHASE 0 XXXXX where XXXXX represents a calibration value. Leave the test equipment connected as shown in figure 4-18. Do not change the signal source. Appendix B contains an alternate method of calibrating phase using a scope.
2. On the Model 95,

Adjust the Knob until the phase meter reads 0°. Press the TRIG FREQ key to advance to the next step. Verify the display flashes CALIBRATING and then displays CONFIDENCE. Pressing TRIG FREQ key stores the calibration value in internal memory.

Step 20. Confidence Check

1. The Model 95 displays CONFIDENCE which tests and verifies the accuracy of the Model

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95's voltage reference, DVM, and output amplifier. Connect test equipment as shown in figure 4-19 (no termination).

Figure 4-19. Confidence Check Setup

Measure the Model 95's unloaded output dc voltage with the DVM. Verify the output voltage measures between +9.8 and +10.2 Vdc.
On the Model 95, press the TRIG FREQ key to advance to the next step. Verify the display flashes CALIBRATING and then displays AUTOCAL ENABLE.

Step 21. Autocal Enable/Disable

1. The Model 95 displays AUTOCAL ENABLE. Use the Knob to step between AUTOCAL ENABLE and AUTOCAL DISABLE. When Autocal is enabled, the operator can Autocal the Model 95 as described in paragraph 4.2. When Autocal is disabled the operator cannot run the Autocal procedure. If Autocal is selected (SHIFT and CALIBRATE), the Model 95 displays the message AUTOCAL DIS-ABLED.
2. On the Model 95, press the CALIBRATE key. Verify the Model 95 displays END CAL. The Calibration Procedure is now complete.

CAUTION

Failing to perform Step 21 item 2 will keep the calibration parameters from being stored in memory, and the units calibration will be corrupted.

Step 22. Wrap up Calibration

1. Remove the power and disconnect the test equipment.
2. Install the shield and top cover using the five screws.

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FIGURE 5-1 Model 95 Functional Blocks.

5-0

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SECTION 5

5.1 THE MODEL 95

This section describes the the Model 95 Synthesized Arbitrary Function Generator. Section 5 is divided into two parts: the basic functional block description and the detailed block descriptions. The intent is to provide an insight into signal flow through the Model 95, as well as, what controls that signal flow.

In this description, functional blocks are organized by signal flow rather than actual assemblies. The Model 95 consists of four major functional blocks (Function Generator, Arbitrary Waveform Generator, Output, and Microprocessor Section) as shown in figure 5-1. The waveforms originate from the Function Generator and Arbitrary Waveform Generator block and are routed to the Output block. All functional blocks are contained in six separate assemblies (Motherboard, Output board, Function Generator board, Phase Lock Loop board, Arb board, and Front Panel). The motherboard links all blocks within the Model 95.

The Function Generator block produces the triangle, square and sine waves supplied by the Model 95. Also, it provides frequency and symmetry control of the waveforms. Frequency of the Function Generator is controlled by one of four inputs: Frequency Control, Sweep Generator, Phase Lock Loop, and external Modulation Input.

Frequency Control sets up the generator's fixed frequency. If a synthesizer mode is selected, the Phase Lock Loop supplies a frequency correction voltage which locks the Function Generator's frequency to an internal or external frequency. The Phase Lock Loop receives its internal frequency input from the Frequency Synthesizer which is referenced to the Freq Ref or optional reference. The phase lock loop gets its external frequency from Trig Freq In connector which allows phase shift of the output waveform relative to the source. If the sweep mode is selected, the Sweep Generator sets the stop frequency and sweep length; Frequency control input, Mod In, allows external modulation of the frequency.

The Mode Control controls the operating mode of the Function Generator. It allows the Function Generator to produce continuous waveforms, single cycled triggered waveforms, and multiple cycled gated and burst waveforms. Burst allows a user-defined number of cycles to be produced.

The Arbitrary Waveform Generator permits the user to create and edit unique waveforms and store as many of these waveforms as will fit in its four 8K blocks. The Arb Generator selects the Arb waveform and routes it to the Output block.

The Output block selects the waveform, controls the output level and offset, and drives the external devices. The output level can be fixed or modulated (Amplitude Modulated or Suppressed Carrier Modulated).

The Microprocessor Section provides the processing and interfacing for the Model 95. It supplies the analog control voltages like the frequency control voltage or amplitude control voltage. It also supplies the digital control lines that control the signal routing through out the Model 95. The Microprocessor Section interfaces with the display/keyboard and the GPIB interface.

5.2 FUNCTION GENERATOR

5.2.1 Introduction

The function generator section produces the Model 95's square and triangle waves, as well as, the sine wave. The Function Generator block includes:

VCG Summing Amplifier, Symmetry Control, Function Generator Loop (current sources, frequency range capacitors, capacitance multiplier, triangle buffer, comparator, and diode gates), High Frequency Compensation, Sine Convertor, Trigger (Mode) Control.

Figure 5-2 illustrates the Function Generator Block. The heavy line through the diagram indicates signal flow.

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The Phase Lock Loop. Frequency Control, Sweep Generator, and Mod In provide either dc or ac plus dc voltage to the VCG Summing amplifier. These inputs control the instantaneous frequency of the waveform. The VCG Summing Amplifier produces an output, VSUM, which is the summation of all four inputs. VSUM drives the Symmetry Control which produces two voltages. +FCV and -FCV, which will control the VCG (constant) Current Sources. When the waveform symmetry is 50%, the two voltages. +FCV and -FCV, will be equal but opposite polarity. However when the symmetry is anything but 50%. the voltages. +FCV and -FCV will be unequal. The VCG Current Sources controls the charge and discharge rate of the the Function Generator Loop's Frequency Range Capacitors. The Function Generator Loop produces two output signals: the square wave and the triangle wave. The square wave runs directly to the Souare Shaper (paraoraph 5.4.2). The triangle wave drives the Triangle Buffer or the Sine Convertor. The outputs from the Sine Converter and Triangle Buffer drive the Function Selector (paragraph 5.4.2). The High Frequency Compensation circuit makes allow-

ances for delays in the Function Generator Loop at the higher frequencies. Trigger Control turns on or off the Function Generator Loop based on the mode selected. 5.2.2 Function Generator Loop

The Function Generator Loop consists of the VCG Current Sources, Frequency Range Capacitors, Capacitance Multiplier, Triangle Buffer, Comparator, and Diode Gates. The Function Generator Loop produces the unit's square and triangle waves.

The following example illustrates how the function generator loop operates. See figure 5-3. First, assume the comparator's output is high. This biases diode gate CR35-CR38 to allow the current +COMP to flow into the resistor (R102) establishing the positive reference square wave voltage. The positive reference voltage is about +1.25V (V=+ICOMP x R102). Also, when the comparator output is high, the diode gate (CR27 - CR30) is biased to allow the current, ISWITCH+, to charge the Frequency Range Capacitor. Charging the capacitor with a constant current produces a linear ramp. The Triangle Buffer isolates the Frequency

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Range Capacitor from the Comparator. When the ramp voltage reaches the positive reference square voltage, the Comparator output switches low. When the comparator's output is low, diode gate (CR35 - CR38) switches and allows the current -COMP to flow from resistor (R102) establishing the negative reference square wave voltage - about -1.25V. At the same time, the comparator switches diode gate (CR27 - CR30) and

allows the current ISWITCH- to discharge the Frequency Range Capacitor. This cycle repeats producing simultaneous triangle and square waves. The timing diagram with figure 5-3 illustrates waveform timing.

The VCG Summing Amplifier and Symmetry control the magnitude of the currents ISWITCH+ and ISWTCH-. The Frequency Range Capacitor determines the waveform's frequency range. Increasing the currents increases the

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frequency. Increasing the Frequency Range Capacitor decreases the frequency. The opposite of each is also true.

Normally, the current sources, ISWITCH+ and ISWITCHproduce equal butopposite polarity currents. To change the symmetry (duty cycle) of the waveform, the Model 95 changes the ratio of the current sources. For example, the ISWITCH+ source may supply more than half of the current, while the ISWITCH– source may supply less than half of the current.

Comparator

The Comparator (schematic 1104-00-3342 sheet 7 of 7) compares the output from the triangle buffer, TRIOUT, to the reference square wave level and produces an output that drives both diode gates. Figure 5-4 provides a simplified comparator circuit.

The transistors (Q14 and Q15), connected as a differential pair, compare the TRIOUT (base Q14) to the reference square wave. The level shifter (Q19, Q20, Q21, Q22. Q23) converts the input from Q14 and Q15 collector signals into a bipolar signal that can drive the diode gates and the SQWAVE output. Diode gate (CR27, CR28, CR29, CR30) switches between the compensation current sources (+COMP and -COMP) to generate the reference square wave (ICOMP x R102). The compensation current source is adjustable over a small range in order to provide high-frequency compensation (paragraph 5.2.5). The comparator also

drives the other diode gate (CR35, CR36, CR37, CR38) which switches the VCG current sources (ISWITCH+ and ISWITCH-). These currents charge and discharge the Frequency Range Capacitor. Two JFETs (Q25 and Q26) buffer the diode gate (CR27 - CR30) from the ISWITCH+ and ISWITCH- current sources.

VCG Current Sources

The VCG current sources (schematic 1104-00-3342 sheet 3 of 7) convert the two symmetry control voltages, +FCV and -FCV, into two currents ISWITCH + and ISWITCH -. Because the the current sources are mirror images, only the positive current source will be described.

The positive current source consists of two amplifiers (U13 and U14) and two transistors (Q1 and Q2). U13 and Q1 form a voltage to current converter. U13 forces the voltage across R31 to produce the the current, IR31. The current IR31 also flows through the resistor R30 producing a voltage drop equal to +FCV. The current mirror stage (U14 and Q2) forces a voltage drop across R36 equal to +FCV. The current through R36 is ISWITCH+ and drives the diode switch (CR35 - CR38). Another output from this current source, VSOURCE, drives the Trigger Baseline Compensation circuit.

The negative current source (U17, Q3, U18, Q4) is identical to the positive current source. U17 and Q3 form the voltage to current converter, and U18 and Q4 forms the current mirror.

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During symmetrical operation (50%) the two resistors (R31 and R32) connect directly to ground. But selecting variable symmetry places R131 between the junction of R31 and R32 and ground which allows the connecting node to "move". The control line SYMONS witches R131.

Frequency Range Capacitors and Ranges

The frequency range switches (schematic 1104-c0-3342 sheet 5 of 7) change the four frequency range capacitors to the TRINODE line. On the 20 MHz range, the timing capacitance is made up of a 15 pF capacitor (C67) and stray capacitance about 50 pF total; all other capacitors are switched out. For the 2 MHz through 200 Hz ranges, capacitance is added by relay or transistor switches, table 5-1 lists the capacitance for each range. Below 200 Hz, the capacitance multiplier controls the "capacitance".

When the continuous, AM, or SCM mode is selected, the Model 95 uses only the top decade of each frequency range which allows a 10:1 frequency change. But when the FM/VCG or Sweep mode is selected, the Model 95 locks the range switching to the frequency range of the programmed upper frequency and allows the frequency to be changed a full three decades or 1000:1 frequency change. Table 5-1 lists the frequency range for both types of conditions.
Capacitance for the 2MHz, 200 kHz, 20 kHz, and 2kHz ranges is controlled by relay or transistor switches which are enabled by control lines from the boards interface logic. When a control line goes low, the capacitor is switched in. Table 5-1 lists the control lines and their associated ranges and capacitors. Paragraph 5.7.4 describes the function generator interface logic. When non-symmetrical waveforms are selected, the Model 95 switches to the next higher range to compensate for a 1/10th decrease in current source output.

Capacitance Multiplier

Lower frequencies require larger capacitors that often fail to maintain the precise value over time needed for accurate frequencies. To eliminate the need for large capacitors, the Model 95 uses a Capacitance Multiplier (schematic 1104-00-3342 sheet 6 of 7) to simulate large capacitors by dividing the current at the TRINODE. When the VCG Current Source supplies current, ISWITCH+, to the Frequency Range Capacitor, the Capacitance Multiplier draws a portion of the current from TRINODE to decrease the charging time. When the VCG Current Source draws current, SWITCH-, from the Frequency Range Capacitor, the capacitance multiplier adds current to TRINODE to decrease the discharging time.

The capacitance multiplier consists of two amplifiers (U23 and U24). The amplifier (U23) acts as a noninverting amplifier that generates an amplified version of the TRINODE triangle waveform on one side of C62. A capacitor converts a constant slope voltage into a constant current, thus the capacitor (C62) converts the triangle voltage into a current "square wave" at the inverting input of the amplifier (U24). The output of U24, TP11, contains a square wave which is 180° out of phase with the function generator's triangle (figure 5-3). The signal at TP11 is a composite of the out-of -phase square wave and the in phase triangle because the triangle connects directly to the non-inverting input of U24. The output from U24 drives the resistor (R129) with the composite signal. But since both sides of R129 have a triangle signal, the differential signal will be the square wave which causes constant current in R129 in alternating directions with the square wave. When the ISWITCH+ is selected by the diode bridge, most of the charging current is drawn out of the TRINODE through R129 to the negative portion of TP11's square wave. When ISWITCH- is selected, the positive portion of

Table 5-1.	Range	Control	and	Values

Frequency Range
CW, AM, and SCM 10:1 - Top Decade	VCG/FM and Sweep 1000:1 Three Decades	Capacitance	Control Lines
20 -2 MHz	20 MHz - 20 kHz	50 pF - (15 pF + Stray) C67	None
2MHz - 200 kHz	2MHz - 2kHz	490 pF - C57, C58, C67	≤7778
200 kHz - 20 kHz	200 kHz - 200 Hz	0.00519 μF - C55,C57, C58, C67	≤ П 7, ≤ П 8
20 kHz - 2kHz	20 kHz - 20 Hz	0.05219 μF - C53,C55,C57, C58, C67	≤ \
2kHz - 200 Hz	2kHz - 2Hz	0.52219 μF - C52, C53,C55, C57, C58, C67	≤ 77 5, ≤ 77 6, ≤ 77 7 ≤ 77 8

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TP11's square wave sources current through R129 to TRINODE. The net effect is the frequency range capacitor is charged and discharged at a slower rate when the relay (K4) switches the Capacitance Multiplier to the TRINODE. Resistors R67, R68, R69, and R71 determine the square current to inverted square voltage gain of U24, and generate the bottom four frequency ranges of the function generator. Refer to table 5-2.

When the continuous, AM, or SCM mode is selected, the Model 95 uses only the top decade of each frequency range which allows a 10:1 frequency change. But when the FM/VCG or Sweep mode is selected, the Model 95 locks the range switching to the frequency range of the programmed upper frequency and allows the frequency to be changed a full three decades or 1000:1 frequency change. Table 5-2 lists the frequency range for both types of conditions.

Triangle Buffer

The triangle buffer (schematic 1104-00-3342 sheet 6 of 7) isolates the triangle node, TRINODE, from the buffer's output, TRIOUT. The triangle buffer consists of a source follower (Q11) buffered by an emitter follower (Q12). The circuit provides dc stability by monitoring the input and outputs with U25 and controlling the drain to source current in Q11 so V_CS = 0V. Q13 is the controlled current source.

The Auto cal circuit measures the triangle balance, TRIBAL, relative to the ground, TRICOM, and produces a triangle balance voltage, VTRIBAL. The Model 95 stores the VRTIBAL value in memory and applies it to the comparator as a correction voltage.

5.2.3 VCG Summing Amplifier

The VCG Summing Amplifier (U5 - schematic 1104-00-3342 sheet 2 of 7) algebraically adds the MOD IN, VFREQ. SWEEP. and VLOOP inputs. These input sionals control the frequency of the function generator's waveform. MOD IN is the FM/VGC input which can be an ac or dc signal. VEREO is a dc value representing the function generator's fixed frequency. The DAC Sample and Hold Network on the Motherboard (schematic 1104-00-3395 sheet 5 of 10) supplies the VFREQ signal. The Sweep Generator (schematic 1104-00-3342 sheet 2 of 7) produces a ramp that drives the SWEEP input. VLOOP is an analog frequency correction signal supplied by the phase lock loop. Another input, VCGZERO, is an Auto cal correction voltage supplied by the DAC Sample and Hold Network on the Motherboard. Output from the VCG Summing amplifier. VSUM. drives the Symmetry Control (paragraph 5.2.4)

Normally (Continuous, AM, and SCM modes), the VCG Summing Amplifier controls the generator's frequency over a 10:1 frequency change. But, the VCG Summing Amplifier can control the frequency range over a 1000:1 change when FM/VCG or Sweep modes are selected by locking the generator to the range of the upper frequency selected. See paragraph 5.2.2: Frequency Range Capacitors and Capacitance Multiplier.

Most inputs to the VCG Summing Amplifier are connected by analog switches (U4A - U4D). Each switch is controlled by a control line from the board's interface logic. The MOD IN signal connects to the amplifier when FM line (U4A) goes low. At the same time, the FM line goes high disconnecting (U4D) the FM/VCG input

Frequency Range
CW, AM, and SCM Modes 10:1 - Top Decade	VCG/FM and Sweep Modes 1000:1 Three Decades	Resistance	Control Lines
200 Hz - 20 Hz	200 Hz -	10 kΩ - R67	FB4
20 Hz - 2Hz	20 Hz - 20 mHz	110 kΩ - R67, R68	FB4, FB3
2Hz - 200 mHz	2Hz - 2mHz	1.11 MΩ - R67, R68, R69	FB4, FB3, FB2
200 mHz - 20 mHz 20 mHz - 2mHz	200 mHz - 2mHz 20 mHz - 2mHz	11.11 MΩ - R67, R68, R69, R71 See Note	All high See Note

Table 5-2. Range Control and Values

The Model 95 does not switch to the 20 mHz range. It actually keeps the same range capacitors as the 200 mHz range, but it decreases the input to the VCG Summing Amplifier by 1/10th effectively dropping down a decade range by switching in, SCALF, an additional input resistor (R8) in series with the VFREQ input.

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resistor (R3) from ground. When FM/VCG is not selected, switch (U4D) is closed. Control line FR7 switches in added phase lock filtering at 200 kHz and below. When the frequency is set to <20 mHz (FR0) or symme-</li>
try is not 50%, the control line SCALE inserts a resistor (R8) which divides the VFREQ input by 10 allowing the unit to operate on the middle decade of the selected frequency range. All control lines used in the VCG Summing Amplifier are supplied from the Function Generator Input Logic (paragraph 5.7.4.1).

5.2.4 Symmetry Control

Symmetry Control (schematic 1104-00-3342 sheet 3 of 7) controls the symmetry of the function generator waveform. The input, VSUM, from the VCG Summing Amplifier drives two similar circuits, one controlling the charging time (U7C) and the other controlling the discharging time (U7D). The two outputs from the circuit (+FCV and -FCV) supply equal but opposite polarity (50% symmetry) voltages. These two voltages drive the VCG Current Sources, as well as, the High Frequency Compensation circuit.

The +FCV circuit consists of the inverting amplifier (U9) with the DAC (U7C, U10) that controls the gain of the circuit. The DAC (U12B, U11A) provides an offset adjustment. The Microprocessor Section on the Motherboard loads the data values into the DACs.

The –FCV circuit consists of the non-inverting amplifier (U15) with the DAC (U7D, U16) controlling the gain. The DAC (U12A, U11B) provides an offset adjustment. The Microprocessor Section on the Motherboard loads the data values into the DACs.

At 50% symmetry (symmetrical waveform), each circuit provides equal outputs. As the symmetry setting changes away from 50% in either direction, one circuit provides greater amplification and the other less amplification. The DACs by themselves provide linear gain, but placing them in the feedback paths of U9 and U14 provides an overall circuit gain of the inverse function of the symmetry setting.

The Auto cal circuit measures the +FCV and -FCV voltage and provides correction values to the offsetDAC's data lines.
5.2.5 High Frequency Compensation

The High Frequency Compensation circuit (schematic

1104-00-3342 sheet 4 of 7) corrects for internal circuit time delays of the function generator loop on the 200 kHz to 2 MHz and 2 MHz to 20 MHz frequency ranges by decreasing the current, +COMP and -COMP, which decreases the reference square wave voltages. This causes the Comparator to switch sooner, cancelling the tendency of the triangle to grow in frequency as the frequency increases.

The High Frequency Compensation circuit consists of two DACs (U12C, U12D). The DACs use the +FCV and -FCV voltage as reference voltages. The microprocessor section provides the DACs with data which adjusts the gain of the output. Outputs from the DACs (+COMP and --COMP) will be scaled from the +FCV and --FCV. Trigger Baseline Compensation

Trigger Baseline Compensation (schematic 1104-00-3342 sheet 4 of 7) controls the quiescent baseline level during non-continuous modes of operation. A single line, RUN, from Mode control (paragraph 5.6) controls the generation of the triangle wave by either forcing the TRINODE line to "ground" (trigger, gate, and burst modes) or "open" (continuous mode). With the RUN line low, the TRINODE line is forced to ground; with RUN high, the system operates in the normal manner.

The Trigger Baseline Compensation circuit consists of amplifiers (U19 and U20) and transistors (Q5, Q6, and Q7). Amplifier (U19) and transistor (Q5) form a voltage to current converter. A voltage equal to VSOURCE appears across the resistor (R38) producing a current IR30. The current mirror (U20, Q7) reflects the current IR30 off the –VCG supply. The drop across R39 also equals +FCV. U20 forces a drop equal to +FCV across R40, but R40 is half the value of R39 which produces a current equal to 2(ISWITCH+). When RUN goes high, the current, 2(ISWITCH+), flows through the diode (CR10) reverse biasing diodes CR7 and CR8. This releases the TRINODE line and allows the function generator to run.

When the RUN line goes low, the diode (CR10) is reversed biased and the current flows through diodes CR8 and CR9. A current equal to ISWITCH+ flows through each diode. This forces the TRINODE to ground potential and stops the function generator. The Mode Control and Bust Counter logic on the Arb Board controls the RUN line.

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5.3 ARBITRARY WAVEFORM GENERATOR

5.3.1 Introduction

The Arbitrary Waveform Generator, Arb, consists of three major blocks: the counter, random accessmemory (RAM), and digital to analog convertor (DAC). See figure 5-5. The RAM contains the waveform data. The counter sequences through the RAM addresses. The RAM produces the waveform data which the DAC converts into analog levels. Filters following the DACs smooth the waveform.

5.3.2 Counter and Address Arbitrator

The counter (schematic 1104-00-3327 sheet 3 of 8, U14 and U15) is a presettable 16-bit binary scanner. The preset lines, SO-S15, determine the start address of the waveform. The counter counts up from the preset address until either a LOAD or RSTOP signal is received. At this time, the counter resets to the latest SO - S15 address. The arbitrator (U24, U25, U26, and U27) determines the source of the data for the RAM address lines, AO - A16. The counter is used to address RAM when generating the waveform, and the microprocessor RAM address lines are used when editing the waveform. The control line, ACOE, determines whether U26 and U27 send Microprocessor data or U24 and U25 send the Address Counter contents to the RAM address.

5.3.3 Active and Storage RAM

The active and storage RAM (schematic 1104-00-3327 sheet 3, U16-U19) store up to four arbitrary waveforms. The active RAM (U16 and U18) uses the scanning address lines (A0 - A14) to step through the RAM's data. The microprocessor controls address lines (A0-A16) when editing Arb waveforms. The storage RAM (U17 and U19) stores up to four waveforms as developed in the active RAM. When a stored waveform is to be used, it is first transferred to the active RAM. All RAM outputs are transferred on data lines, D0 - D11, which drives the DAC Register.

The control line, OB, from the Arb I/O enables the active RAM's output. Two lines (WEB and WEH8 from the programmable array logic, PAL) supply write enable lines to the active RAM. The storage RAMs also have similar control lines: OE32 (output enable), and WEB and WEB (write enable).

5.3.4 DAC Register

The DAC register (schematic 1104-00-3327 sheet 3, U20 and U21) isolates the Arb data lines, D0-D11, from the DAC data lines, RD0-RD11. The ACK1 line from the mode control clocks the data into the register. The DAC

5.3.5 ARB DAC and Filters

The waveform DAC (schematic 1104-00-3327 sheet 5, U30) converts the digital data (RD0 - RD11) from the DAC register into an analog signal. The DAC uses the -12V dc supply to provide a -5Vdc operating voltage and a -1.2 V dc reference voltage. The ACK1 line from the mode control clocks the data into the DAC.

The offset DAC (schematic 1104-00-3327 sheet 5, U40) zeros the offset of the signal developed by the waveform DAC, amplifier, and filters. The value (data lines AQ0 - AQ7) for the offset DAC is determined during calibration. The Model 95 clocks the data into the DAC (FOSTB goes low) at power on or when a different filter is selected. The waveform DAC and the offset DAC drive the differential amplifier (U31).

The ARB filters (schematic 1104-00-3327 sheet 5) provide three possible Arb signal paths. One path, no filter, bypasses via relay (K1) the filter routing the Arb signal directly to the Arb output OBSIG. The other paths route the Arb signal through two low pass, three-pole Bessel filters. One filter has 50 kHz cut off frequency and the other has 5MHz cut off frequency. The relay (K2) selects a filter's output and routes it to the Arb output OBSIG. Two control lines, FILT1 and FILT2, select

the filters. With FILT1 and FILT2 high, no filter is selected. Closing the relay (K1) while leaving the relay (K2) open selects the 5MHz filter (FILT1 high and FILT2 low). Closing both relays (K1 and K2) selects the 50 kHz filter (FILT1 and FILT2 low). The Arb signal, OBSIG, is routed to the Function Selector.

5.3.6 RAM Battery Control

The RAM battery control circuit (schematic 1104-00-3327 sheet 7) uses a nonvolatile controller (U39) to select either the dc power supply or the backup battery, RVCC, to power the storage RAM. The microprocessor supplies the RAM chip enable, RC32, to the controller whose output is the storage RAM's chip select line, CS32. If the power supplied to the controller is out of limits, the controller inhibits the CS32. A Model 95 may contain one or two batteries, depending on the RAM installed.

5.3.7 Z-Axis Driver

The Z-Axis Driver (schematic 1104-00-3327 sheet 4 of 8) converts the RZBIT from the DAC register into a 50Ω signal. A three bit DAC (Q5, Q6, Q7, and Q8) controls the level of the signal. Three lines; ZAC0, ZAC1, and ZAC2; sets the DAC's level. The duty-cycle of the

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RZBIT signal may be complemented using the front panel controls or GPIB commands ( Model 95 Operator's Manual ). The Z-Axis output is active only when an Arb function and Arb edit is selected.

5.4 OUTPUT SECTION

5.4.1 General

The Model 95's output section (see figure 5-6 consists of of nine circuit blocks: the Function Selector with Square Shaper, XY Multiplier, AM Summing Amplifier, Preamplifier, Power Amplifier, 0/20 dB Attenuator, Bal-

anced Output Driver, Unbalanced Output Attenuator Network and Impedance Control, and Balanced Output Attenuator network and Impedance Control. The output section, shown in figure 5-6, is located on three separate assemblies in the Model 95: Phase Lock Loop board, Output board and Motherboard. In figure 5-6, the bold lines represent the signal flow through the Output section. The waveform, selected by the Function Selector, flows through the XY Multiplier where its amplitude is determined by the amplitude controlling signal. The waveform is then amplified and routed through attenuators to the selected output connector.

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5.4.2 Square Shaper and Function Selector

The square shaper (schematic 1104-00-3335 sheet 2 of 5) converts the TTL level square wave signal (SQWAVE) from the Function Generator section to a bipolar, 2Vpp square wave. The shaper's input is a non-saturating input transistor (Q1), which produces fast switching edges. This transistor drives the level shifter (Q5 and Q6) whose output is a 3Vpp square wave which switches the diode gate (CR3 - CR6). The gate switches the positive and negative current sources which drive the load resistor (R16T). The +2 amplifier (U11) buffers the square wave and drives the Function Selector. The square wave level is approximately 1Vpp at R16T. The two transistors Q2 and Q4 are used to enable and disable the Square Shaper. When the SQRON line goes high, the Square Shaper is enabled.

The function selector circuit selects and routes either the Sine (SIN1), Triangle (TRIOUT), square (2Vpp SQUARE), or Arb (OPTSIG) waveform to the preamplifier (PREAMPIN). The function selector, located on the Output board, consists of four relays (K1 - triangle, K2 - square, K3 - sine, and K4 - Arb (schematic 1104-00-3335 sheet 2 of 6)). Microprocessor Section (schematic 1104-00-3395 sheet 3 of 10) switches the relays via the interface latch (U2 - schematic 0104-00-3335 sheet 1 of 6). When one of the relay control lines (SINSE, TRISE, SOSE, OPSE) goes low, the relay will be closed. Only one relay will close at a time. In addition, the function selector terminates each waveform input and sets the amplitude of each waveform to approximately 1Vpp using resistor networks.

5.4.3 XY Multiplier and Preamplifier

The XY Multiplier and Preamplifier (schematic 1104-00-3335 sheet 3 of 5) controls or modulates the amplitude of the selected function. The multiplier's Y input receives it's input (PREAMPIN) from the function selector. All function levels are about 1Vpp. The AM Summing Amplifier on the Phase Locked Loop board (schematic 1104-00-3341 sheet 6 of 6) supplies the multiplier's X input (AMSIG). A dc level at the X input controls the generator's amplitude level, and an ac signal modulates the generator's amplitude. The ±6V Supplies (U14A, U14D, Q27, and Q26) provides the power for the XY Multiplier.

The multiplier (U4) is a wide-band device producing differential output currents which are the product of the PREAMPIN signal and the AMSIG input. The resistors (R33 and R34) convert the multiplier's output current into voltage. A pair of Darlington emitter followers (Q22, Q23, Q24, and Q25) buffer the signal from the XY

Multiplier's output and drives the differential amplifier (U5). The differential amplifier (U5) converts the differential output from the emitter followers to a singleended output (PREOUT) of about 6Vpp (full amplitude). PREOUT is offset about +3.5 Vdc to compensate for offsets in the multiplier circuit. The multiplier offset circuit (U14C and U12) supplies a compensation voltage, COMPOUT, to the output amplifier which compensates for offset in the PREOUT signal.

5.4.4 Output Amplifier

The power amplifier (schematic 1104-00-3335 sheet 4 of 6) is a fixed gain, wide-band inverting amplifier with a push-pull complimentary symmetry output stage. This amplifier provides the gain and drive needed to drive the unit's outputs. The Output Amplifier has three signal inputs: PREOUT, COMPOUT, and VOFST. PREOUT is the selected function from the Preamplifier. COMPOUT is the multiplier compensating voltage from the multiplier's offset circuit. VOFST supplies the offset voltage to either dc offset the waveform or dc output level. VOFST is generated by the DAC Sample and Hold Network on the Motherboard. Both the COMPOUT and VOFST inputs contain inductors which improve the transient response.

The Output Amplifier has two distinct signal paths: the ac path and the dc path. The ac path provides the wideband and high speed required by the unit's output (schematic 1104-00-3335 sheet 4 of 6). The ac path routes the signal through C36, C49, and the emitter followers Q12 and Q16 to the current sources Q13 and Q17. The emitter followers Q14, Q15, Q18, and Q19 buffer the current source from the PAOUT and feedback resistor R79 and R80. The dc path provides the low frequency path and dc stability of the output amplifier. The dc path runs through the differential amplifier Q9 and Q10. DC gain rolls off with frequency (about 80 kHz). The BC network C31 and B47 determines the roll-off frequency. The differential amplifier (O9 and Q10) drives the inverting stage of Q11 whose output adjusts the dc bias of the current source. The amplifier's 50Ω output impedance is set by the resistors R95, R96, and R97. PAOUT also drives the Output Board's Peak Detector.

5.4.5 –20 dB Attenuator

The -20 dB attenuator circuit (schematic 1104-00-3335 sheet 5 of 6) together with the XY Multiplier and -40 dB Attenuators (Motherboard) controls the level of the output waveform. The -20 dB attenuator attenuates the power amplifier's PA OUT signal by switching in or out resistors R98 through R108. The microprocessor circuit via the Output board's data register (U3) closes the

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relay (K5) when the ATTEN-20 goes low. R169T and C105T improves the transient response of the attenuator. 54.6 Balanced Drivers

The relay (K6 - schematic 1104-00-3335 sheet 5 OF 6) selects either the Balanced or Unbalanced output and routes the signal from the -20 dB attenuator to either the Unbalanced Output Attenuator Network and Impedance Network or to the Balanced Drivers If balanced output is selected, the signal is routed through two amplifiers which produces two 180° out of phase signals, BOUT1 and BOUT2. The amplifier (U6) is a unity gain inverting amplifier. The other amplifier (U7) is a unity gain, noninverting amplifier. The 50 source and load (R104 -R108) reduce the input level by 1/2 which produces a net gain of ±1/2 in the two amplifiers. The two outputs, BOUT2 and BOUT1, are routed to the Balanced Output Attenuator Network and Impedance Control (Motherboard). Both signals also drive the Peak Detector

The balanced/unbalanced relay (K6) is controlled by the BAL-UB line from the latch (U3). When the BAL-UB line goes low, the Unbalanced output is selected. When the line goes high, the Balanced output is selected.

5.4.7 Unbalanced Output Attenuator Network and Impedance Control

The Unbalanced Output Attenuator Network and Impedance Control block on the Motherboard (schematic 1104-00-3395 sheet 7 of 10) serves two functions. It selects the output impedance of the instrument and provides 0dB or -40 dB of attenuation.

If the unbalanced output is selected, the UBOUT signal from the Balanced Driver is routed through a -40 dB attenuator (K1 – R69 through 74). The relays (K2 and K3) and their associated resistors select the output impedance (50Ω, 75Ω, or 600Ω). The relay (K6) opens the output when the Unbalanced Output is turned off. The output from this block drives the front panel's Unbalanced Output connector.

The attenuator relay (K1) is switched when U30-pin 15 goes low. When K2 and K3 are disabled (U30 pins 14 and 13 high), the output impedance is 50Ω. When relay K2 is disabled (U30 pin 14 high) and relay (K3) is enabled (U30-pin 13 low), the output impedance is 75Ω. When both K2 and K3 are enabled (U30 - pins 14 and 13 low), the output impedance is 600Ω.

5.4.8 Balanced Output Attenuator Network and Impedance Control

The Balanced Output Attenuator Network and Impedance Control block on the Motherboard (schematic 1104-00-3395 sheet 7 of 10) serves two functions. It

selects the output impedance of the instrument and provides 0dB or -40 dB of attenuation.

If the balanced output is selected, the BOUT 1 and BOUT2 signals from the Balanced Driver are routed through the -40 dB attenuator (K4 along with resistors R80 through R89). The relay (K5 and its resistors) select the output impedance (135Ω and 600Ω). The output from this block drives the front panel's Balanced Output connectors.

The attenuator relay (K4) is switched when U30-pin 19 goes low. When K5 is disabled (U30-pin 12 high), the balanced output impedance is 135Ω. When K5 is enabled (U30-pin 12 low), the output impedance is 600Ω.

The control line, POE, from the Microprocessor resets the attenuators to -40 dB at power up or power down.

5.5 FREQUENCY CONTROL

5.5.1 Introduction

Frequency Control covers those items that affect the frequency of the Model 95. These items include the primary frequency control - VFREQ, the sweep generator, the phase lock loop and synthesizer, and Mod In (FM/VCG).

5.5.2 VFREQ

The VFREQ line is the Model 95's basic frequency control. The line originates at the Motherboard's DAC Sample and Hold Network (paragraph 5.7.5) and runs to the Function Generator's VCG Summing Amplifier (paragraph 5.2.3). The VFRQ is a dc voltage between +8Vdc and +0.8 Vdc which represents the programmed frequency of the unit. VFREQ controls the frequency in the Continuous, CW, and AM modes. For FM, VFREQ sets the center frequency. For VCG, VFREQ sets the minimum frequency. For sweep mode, the VFREQ sets the start frequency.

5.5.3 Sweep Generator

The Sweep Generator (schematic 1104-00-3342 sheet 2 of 7) consists of an 8-bit DAC (U7A) and its buffer amplifier (U8) which produces the sweep voltage (0 to +8V) for the function generator. Another part of the sweep generator, DAC (U7B), supplies the sweep output ramp to the Sweep Out connector. VFREQ from the DAC Sample and Hold Network sets the Function Generator to the start frequency (paragraphs 5.5.2 and 5.2.3). Another dc voltage from the DAC Sample and

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Hold Network, VSLEN, provides the reference for the sweep DAC (U7A). To produce the sweep, the Microprocessor sends sweep DAC data (0000 0000 to 1111 1111 for sweep up and 1111 1111 to 0000 0000 for sweep down) representing the sweep voltage for the function generator. Sweep time determines microprocessor generated data rate. The Microprocessor's data also determines the sweep shape: linear sweep or logarithmic sweep. The sweep DAC is hardwired in the write mode. The sweep DAC receives data input when the A/B and DS lines are high, and the DST line is low.

The DAC (U7B), part of the Sweep Generator DAC, and amplifier (U6B) supplies the SWEEP OUT ramp. The Microprocessor writes data (0000 0000 to 1111 1111 for sweep up or 1111 1111 to 0000 0000 for sweep down) to the DAC when the DST and AB lines are low, and DS2 line is high. The shape of the output will always be linear regardless of whether linear or log sweep is selected. The sweep time determines the rate of the data from the Microprocessor. The DACs reference voltage, supplied by Zener diode (CR1) is –6Vdc.

5.5.4 Phase Lock Loop/Synthesizer

5.5.4.1 Introduction

Figure 5-7 provides a simplified illustration of the Phase Lock Loop and Synthesizer. This circuit controls the frequency of the function generator when the Model 95 operates as a synthesizer or variable phase generator. The circuit consists of six blocks located on several assemblies. The Frequency Synthesizer supplies the accurate, stable 20 Hz to 20 MHz frequency reference for the Phase Detector when internal lock is selected. For external lock, the Phase Detector receives its reference via the TRIG/FREQ IN connector on the front panel.

The variable frequency input to the phase detector closes the loop back to the function generator. The frequency input selected depends on the function selected. Either the sine or triangle wave is routed through the Zero Crossing Detector producing a square wave output. The square wave frequency runs directly into the phase detector. The phase lock loop's output, VLOOP, provides one input to the function generator's VCG Summing Amplifier.

5.5.4.2 Frequency Reference

There are two frequency references used in the phase lock loop: the internal frequency synthesizer and the external TRIG/FREQ IN. The internal frequency synthesizer produces a 20 Hz to 20 MHz TTL level output, SYNTH. The frequency synthesizer circuit (figure 5-8) consists of a 500 kHz reference, reference divider, phase detector, low pass filter, voltage controlled oscillator, +N divider, and +M divider. The frequency synthesizer circuit is located on the Motherboard (schematic 1104-0-3395 sheet 4 of 10).

The Voltage Controlled Oscillator - VCO (U15) produces an output between 10 and 20 MHz. The ÷2 and +N divider (part of U13) divides the VCO's output to 500 Hz which drives the variable frequency input to the phase detector (part of U13). The reference frequency, SHCLK, for the phase detector originates in the Microprocessor Section and is divided by the Reference Divider (part of U13) to 500 Hz. The phase detector's output drives the VCO input via the Low Pass Filter (U14) forcing the VCO's output to 2N times 500 Hz. The capacitor (C42) sets the frequency range of the VCO. The ÷M Counter (U17) divides the VCO output down to the programmed frequency. The Microprocessor Section loads serial data, SDATA, through the ÷N Divider to the +M Counter; both are enabled by the SEN line.

The external reference originates at the TRIG/FREQ IN (EXT FREQ INPUT) connector and runs through the Secondary Input/Output (schematic 1104-00-3395 sheet 6 of 10) to the Source Selector.

5.5.4.3 Sine/Tri Z-Crossing Detector

The Sine/Triangle Zero Crossing Detector (schematic 1104-00-3341 sheet 2 of 6) converts the sine wave or triangle signal, ZCSIG into a square wave. As the signal passes through its zero crossing point, the crossing detector dc output level changes high or low producing a square wave. This output is one of the input signals, Z-CROSS, to the source selector circuit. The zero crossing detector consists of a high speed comparator. Its feedback resistors (R2 and R3) ensure noise immunity. Two control lines, SELA and SELB, enable the Zero Crossing Detector.

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5.5.4.4 Source Selector

The source selector circuit (schematic 1104-00-3341 sheet 2 of 6) selects one of each set of frequency sources as inputs for the phase detector.

Reference Frequency Sources SYNTH - internal frequency synthesizer BXFREQ - external reference source (TRIG/ FREQ IN connector) Variable Frequency Sources SQWAVE - square wave PLS/SQR - Arb Sync - not used Z-CROSS - sine or triangle wave converted to square wave

Two control lines, SELA and SELB., to the Source Selector choose the frequency sources. One reference frequency source and one variable frequency source will be selected. When SYNTH is selected, SQWAVE will also be selected. When BXFREQ is selected, either of the three variable frequency waveforms can be selected. The LOCK line enables (low) the Source Selector.

5.5.4.5 Phase Detector

The Phase Detector consists of two biquinary (+2 and +5) Counters, the Phase Comparator, and the Charge Pump (schematic 1104-00-3341 sheets 2 and 3 of 6). Each input to the Phase Comparator runs through the +10 (20 - 2MHz range) or the +2 (all other ranges) counters (U4A and U4B) prescaling the input frequency. The phase comparator, a PAL, compares the reference frequency signal and the variable frequency signal, and produces an output based on edge arrival times of each monitored signal. The comparator generates one of three possible output conditions using the VLAGR and VLEADR lines. These lines drive the charge pump.

The Charge Pump (schematic 1104-00-3341 sheet 3) controls the current to and from the Lock Loop Filter. The Charge Pump consists of a diode gate (CR2-CR5), a positive current source (Q1), and a negative current source (Q2). The diodes (CR1 and CR6) provide temperature compensation for their respective current sources. The VLAGR and VLEADR inputs from the phase comparator switch the charge pump current. The duration and direction of current represents the phase difference between the selected reference frequency signal and the variable frequency signal. The time difference between the edges determines the amount of current pumped into the lock loop filter. The

phase difference between the edges determines the direction of current flow. When the signals arrive concurrently, no current is pumped to the Lock Loop Filter.

5.5.4.6 Lock Loop Filter

The Lock Loop Filter circuit (schematic 1104-00-3341 sheet 3 of 6) converts the pulsating current from the Charge Pump into a dc error voltage, VLOOP. The error voltage, VLOOP, gradually changes the VCG Summing Amplifier output signal, VSUM, to match the generator frequency and phase with the reference frequency.

When the reference to generator frequency difference is too large for the system to handle, the UNLOCK indicator on the front panel will flash. When FM or sweep modulation is selected, the LOCK line is high, opening the VLOOP line, and the UNLOCK indicator remains on.

The filter characteristics of the circuit are controlled by the Microprocessor Section, based on the signal frequency. Solid state switches (U17A - U17D) select the various filter circuit combinations. VPHASE supplies the voltage that varies the phase (PHASE key or PHASE command).

5.6 MODE CONTROL

5.6.1 Introduction

Mode Control (schematic 1104-00-3327 sheet 2) turns on and off the Function Generator Loop (paragraph 5.2.2) via the control line, RUN. The Mode Control consists of the Mode Control GAL (U9), Burst Counter (U13), and Trigger Control (U12A), as well as the board I/O logic (schematic 1104-00-3327 sheet 2 of 8).

5.6.2 Mode Control

The Mode Control (U9) is a programmed GAL that serves several functions: function generator mode control and Arb clock control.

To control the function generator's operating mode, Mode Control decodes lines from the board I/O to control the Trigger Control (U12A). The input lines, MCNTL1 and MCNTL2 select the operating mode, and the input line, SRCNTL, selects the trigger source. SRCNTL low selects External Source, BXFEQ, and SRCNTL high selects Internal Source, SYNTH. Another line, MANTRIG, represents pressing the MAN TRIG key or its GPIB equivalent. The BURST line from the Burst Counter controls Mode Control in the burst and internal gate modes. Table 5-3 describes the relation-

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ship between the Mode Control input control lines and the selected modes. Mode Control produces three control lines; RSET, JSET, and KSET; for the trigger control.

Table 5-3. Mode Control

Control Line	Cont	Trig	Int Gate	Ext Gate	Burst
MCNTL1	0	0	1	0	1
MCNTL2	0	1	1	1	1

The Mode Control also supplies the ARB clocks, ACK1 and ACK2. CLKSEL1 and CLKSEL2 selects the input source for the ARB clocks from the SQWAVE, SYNTH, BXFREQ, or LCLK inputs.

5.6.3 Trigger Control

Trigger Control (U12A), a JK Flip Flop, provides the RUN line that controls the operation of the Function Generator (Trigger Baseline Compensation-paragraph 5.2.5).

Continuous Mode. To place the function generator in the continuous mode, the Mode Control holds its RSET line low which forces the Trigger Control's RUN line high and allows the function generator to run.

Triggered Mode. For the triggered mode, the Mode Control strobes the RSET line low to start the function generator after a triggering event. Also, the Mode Control holds JSET line low and KSET line high. The next negative transition of the SQR (square) from the function generator clocks the Trigger Control, which changes the RUN line to low and turns off the function generator. The function generator will always complete a full cycle.

Internal Gate and Burst Mode. Internal gate mode is actually a burst mode. The Model 95 determines what should be the correct number of cycles for 50% duty cycle of the internal gate frequency, and sets up the Burst Counter. The Mode Control strobes the RSET line low which starts the function generator. Also, the Mode Control places JSET high and KSET low. Once the Burst Counter determines the correct number of cycles has occurred, it places the Mode Controls BURST high which sets JSET low and KSET high until the Trigger Control's QNOT line goes high.

External Gate. The Mode Control strobes the RSET line low which starts the function generator. Also, the Mode Control holds JSET high and KSET low as long as the trigger input is true. When the trigger input goes false,

JSET goes low and KSET goes high until the QNOT goes high.

5.6.4 Burst Counter

The Burst Counter (U13),a programmable ÷N down counter, signals the Mode Control when the programmed number of cycles is completed. The Microprocessor loads the serial data, BRSDIN, into the Burst Counter using the serial clock, BRCLK when the serial input is enabled, SRSEN. The counter, when clocked, BRCP, counts down to zero and the BURST line to the Mode Control goes low, indicating that the burst has been completed.

5.7 MICROPROCESSOR AND INTERFACES

5.7.1 Introduction

The Microprocessor and its interfaces provides the data processing and routing throughout the Model 95. This block includes the Microprocessor Section, Function Generator Interface, Arb Board Interface, Phase Lock Board Interface, Output Board Interface, Front Panel (Keyboard and Display) Interface, and the GPIB Interface. All interfaces, except the GPIB interface, are located on individual boards. Also, the DAC Sample and Hold Network and Internal Calibration Network operate with the Microprocessor Section. Figure 5-9 illustrates the relationship between the Microprocessor Section and Interfaces, as well as lists the Interface's enabling lines and data busses.

5.7.2 Microprocessor Section

The Microprocessor Section (schematic 1104-00-3395 sheet 3 of 10) controls all operations within the Model 95. The Microprocessor Section consists of the Microprocessor, Read Only Memory - ROM, Calibration/ Scratch Pad Memory, and Processor Support Chip, plus support circuits. The Microprocessor section receives its input data from the front panel or GPIB interface, processes the data, and provides data and control lines for internal operation. Figure 5-10 provides a simplified look at the Microprocessor Section.

The microprocessor (U6) executes operating instructions based on firmware stored in the ROM (U12). Another memory, the Calibration/Scratch Pad Memory (U11) - a Random Access Memory - RAM, stores the calibration data taken during Auto cal and manual calibration. This memory also stores the instrument setup at power off and ten stored settings, as well as, providing a temporary storage register during data processing. The RAM accepts data (writes) when its

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WE line goes low. If the WE line is high, the microprocessor section reads data from the RAM. A RAM backup battery (BT1) prevents the loss of data when power is turned off. A flashing life light verifies microprocessor sequencing. The PAL (U35) provides additional address decoding for the ROM(U12) expanding the memory size for the Model 95's firmware.

The Processor Support Chip (U7) controls the interfacing with other parts of the Model 95, as well as, decoding the lower eight address lines, A0 - A7. Seven card select lines from the Processor Support Chip enable interfaces in the Model 95.


GPIB	GPIB interface
ROM	ROM via U35
RAM	RAM via U35
FPSTB	Front Panel
OBSTB	Output Board
FGSTB	Function Generator
OXSTB	Arb Board

Four Quiel Address Lines, QAO - QA3, address the board interfaces in the Model 95. In addition, the Processor Support Chip connects the eight Quiet Data Lines, QDO - QD7, to the board interfaces in the Model

Figure 5-9. Microprocessor and Interfaces

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95. These lines are bidirectional and active when the microprocessor needs to communicate with the board interfaces.

Also, the Processor Support Chip controls the frequency synthesizer via the SEN, SDATA, and SCLK lines. SEN enables the synthesizer, SDATA supplies serial data which loads the synthesizer's +M and + N counters. SCLK clocks the data into the counters.
The Processor Support Chip also produces five sets of control lines for the Sample and Hold Network. The SHEN line enables the network's DAC. SHDATA supplies the serial data that loads the DAC, and SHCLK clocks the data into the DAC. SHSEQM enables the sample and hold selector channel. Three lines; SHSELO, SHSEL, and SHSEL2; select the sample and hold

selector channels.

Another set of lines control the voltage measurement portion of the Model 95's internal calibration network. The lines, DVMO-DVM5, select the inputs to the internal calibration network. DMLB and DMHB selects either the higher or lower order byte to be read by the microprocessor. DVMRUN instructs the DVM to run. DVM_RDY tells the microprocessor it has data to send. During the frequency related portion of the Auto cal cycle, the Processor Support Chip and microprocessor measures the SQWAVE, BXFREQ, and SYNTH frequency, period and symmetry. The FREQOUT line connects the Processor Support Chip and the microprocessor.

Two lines, RKA and RKB, decode the rotary encoder's (front panel control knob) rotation.

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5.7.3 GPIB Interface

The GPIB interface circuit (schematic 1104-00-3390 sheet 10) allows remote operation of the Model 95 using an external IEEE-488 compatible controller. All functions except power and GPIB address are programmable using the interface. The GPIB circuit consists of a GPIB controller and two transceivers.

The GPIB controller (U8) functions as a traffic controller, permitting data to flow in either direction when the correct control information is received. The 'handshaking' routine will ensure neither the signal generator nor the remote controller will send data faster than the other can use. The controller has internal registers where control, data, and address words are loaded and stored until needed or requested. The controller bus connects to the microprocessor circuit address bus A0 - A2. The identification address of an instrument is determined by five bits in the controller address register. The default address (09) automatically loads into the controller from RAM at first (cold start) turn-on. A new address can be entered using the front panel keyboard. The GPIB line from the processor support chip enables the GPIB interface. The E clock from the microprocessor supplies the timing for the GPIB controller. The RW line (read - high, write - low) controls the direction of data flow through the GPIB controller.

The transceivers (U9 and U10) permit bidirectional data flow. They have sufficient input sensitivity to minimize false signals and sufficient drive current to minimize signal loss. The transceiver (U9) handles the GPIB data lines, and the transceiver (U10) handles the GPIB control lines. Direction of data flow through the transceivers is controlled by the GPIB interface chip's T/R2 line.

5.7.4 Board Interfaces

Th following boards have interface logic circuits that converts data lines into control lines for use on that board.

Function Generator board
Schematic 1104-00-3342 1 of 7.
Phase Lock Loop Board
Schematic 1104-00-3341 1 of 6.
Arb Board
Schematic 1104-00-3327 1 of 8.
Output board
Schematic 1104-00-3335 1 of 6.
Display /keyboard of Front Panel
Schematic 0103-00-3001 3 of 3.

5.7.4.1 Function Generator Interface

The function generator's interface logic consists of the input decoder (U1) and data registers (U2 and U3).

The decoder (U1) generates the clocks, CLK0 - CLK5, that will be used on the function generator board. The decoder inputs (QA0, QA1, and QA2) originate from the Microprocessor Section. The data clock selected by the address lines goes low at the the decoder when FGSTB card select line goes low. Two enable lines of the decoder (G1 and G2A) are hardwired enabled. After the FGSTB card select line returns high, all decoder outputs return high. Table 5-4 provides a truth table for the decoder and defines the CLK outputs for the function generator board interface logic.

The registers (U2 and U3) latch data on their inputs on the rising edge of their clocks. The data is generated by the Microprocessor Section. The register (U3) supplies the frequency range control lines for the Frequency Range Switches and Capacitance Multiplier.

5.7.4.2 Phase Lock Loop Interface

The phase lock loop board's interface logic consists of a single Octal data register (U1). The register latches the data on its input lines, QDO-QD7, on the rising edge of the PLSTB card select line. The function generator interface supplies the card select line, and the Micro-processor Section supplies the data lines.

5.7.4.3 Arb Board Interface

The Arb board interface logic consists of two input decoders (U1 and U2), a data buffer (U28), eight octal data registers (U3 - U6, U26, U27, U23, and U29), and two bidirectional data buffers (U7 and U8).

The decoder (U1) selects the eight registers clocks. The other decoder provides strobe lines for the Arb. Table 5-5 defines the decoder outputs. When a decoder is enabled and OXSTB pulses low, a low pulse occurs on the decoder output line selected by QAO - QA2. However, the decoder (U1) is enabled when the QA3 is high, and decoder (U2) is enabled when QA3 goes low. The data buffer (U28) isolates the quiet data lines, QDO - QD7, from the registers. The registers latch data, AQD0 - AQD7, on the rising edge of their respective clocks.

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	Decod	er Inputs			Output	Function
	QA0	QA1	QA2	FGSTB
	0	0	0		CLKO	Clocks Data Register U2
	1	0	0	Ū	CLK1	Clocks DS1 Sweep Generator
	0	1	0	1	CLK2	Clocks DS2Sweep Generator
	1	1	0	1 1	CLK3	Clocks DS1 Symmetry Control
	0	0	1		CLK4	Clocks DS2 Symmetry Control
ı	1	0	1		CLK5	Clocks Range Register U3
	0	1	1	Ū	PLSTB	Card select for Phase Lock Loop Interface

Table 5-4. Function Generator Decoder

Table 5	-5. Arl	b Decoder

Decoder	Inputs				Output	Function
QA0	QA1	QA2	QA3	OXSTB
U1
0	0	0	1	T	CLKO	Clocks Data Register U3
1	0	0	1	ער \|	CLK1	Clock Data Resister U4
0	1	0	1	1	CLK2	Clocks Data Register U6
1	1	0	1	ר \|	CLK3	Clocks Data Register U5
0	О	1	1	· ۲	CLK4	Clocks Data Register U23
1	О	1	1	ר \|	CLK5	Clocks Data Register U27
0	1	1	1	T	CLK6	Clocks Data Register U26
1	1	1	1		CLK7	Clocks Data Register U29
U2
0	0	0	0	1	HIGHSTB	Enables Bidirectional Data Buffer U8
1	о	ο	о	1 7	LOWSTB	Enables Bidirectional Data Buffer U7
0	1	0	0	1	COPYSTB	Drives Arb Gen PAL U22
1	1	0	0		LCLK	Drives Mode PAL U9
0	О	1	0	1 1	FOSTB	Clocks Arb Offset DAC U40

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5.7.4.4 Output Board Interface

The output board's interface logic consists of the input decoder (U1) and data registers (U2 and U3). The input decoder produces the clocks which drive the data registers. The decoder inputs originate from the Microprocessor Section. When the decoder is enabled and OBSTB pulse goes low, a low pulse occurs on the decoder output line selected by QAO - QA2. The registers latch data, QDO - QD7, on the rising edge of their respective clocks. Table 5-6 defines the decoder outputs.

5.7.4.5 Front Panel (Keyboard and Display)

The front panel provides local operator interface to the function generator. This assembly contains the following circuits:

Control Knob Circuit Display Keyboard Circuit Annunciator Circuit

Control Knob The control knob (SW1 - schematic 1104-00-3001 sheet 1 of 3) rotates continuously in both directions. Control knob values per degree of turn depend on the function, mode, and range selected. Rotating the knob pulses its two output lines, RKA and RKB, with TTL logic levels. The Microprocessor Section on the motherboard counts these pulses to determine the amount of change and compares the phase relationship of the output lines to determine the direction of rotation.

Display The display (schematic 0103-00-3001 sheet 1 of 3) consists of the display driver (U1), Vacuum Fluorescent display (VFD1), and data latch (U3). The VFD is a triode vacuum tube with phosphorus coated anode that illuminates when electrons strike it. Each digit consists of 16 anodes with one grid. Elements of a digit lights when both the anode (+15V) and grid (+15V) are biased on. A -24V biases the grids off. The display driver (U1) controls the multiplexed arrangement of anodes and grids.

The driver receives clocked, DSCLK, serial data, DSDATA, from the input latch (U3) via the level shifters

(Q1 and Q2). Another line to the driver, DSPOR, provides a power on reset to the driver.

The display circuit is powered by its own +15 V dc regulator (VR1) which uses the +22 V dc for its input. The fluorescent display filament (8V_rms superimposed on -15 Vdc) receives its power from the FILA and FILB lines. All power is supplied from the motherboard.

Keyboard The keyboard circuit (schematic 0103-00-3001 sheet 1 of 3) consists of an eight-column, six-row matrix, input data register (U3), and decoder (U2). Control signal, FPREG, latches the quiet data bus, QD0-QD2, lines into the latch which drives the decoder. The decoder steps through the six rows, making each row high (+5V) one at a time. When a key is pressed, the high appears on the column associated with that switch. The column lines (P10 - P17) connect directly to the microprocessor circuit. The microprocessor determines which key has been pressed by analyzing the row/column status.

Annunciator Circuit The Light Emitting Diode, LED, circuit (schematic 1104-00-3344 sheets 2 and 3) consists of LEDs (CR4 - CR27), decoder (U4), and data register (U5-U7). The LEDs identify the selected mode and function. Twoother LEDs (CR1 and CR2) connected to the data register (U3) are also part of the LED circuit. The decoder (U4) converts quiet addresses, QA0 and QA1, into clocks for the four registers. Each of four registers (U3, U5 - U7) reads the quiet data bus, QD0 - QD7, and when any of the latches goes low, the LED annunciator lights. Conversely, when a latch output goes high, the LED annunciator remains off.

5.7.5 DAC Sample and Hold Network

The DAC/Sample and Hold Network (schematic 1104-00-3395 sheet 5 of 10) provides the various control voltages required throughout the Model 95. The values for these control voltages are determined during Auto cal and calibration. This circuit consists of the 16 bit DAC (U18), the 1 of 8 selector (U19), and the eight hold capacitors (C49 - 56) and buffers.

The microprocessor section loads serial data, SHDATA, using the clock, SHCLK. The line, SHEN, enables the DAC. Output from the DAC drives the selector. The

Decoder Inputs				Output	Function
QA0	QA1	QA2	OBSTB	•
0	0	0	ר	CLKO	Clocks Attenuator Selector (Motherboard)
1	0	0		CLK1	Clocks Data Register U3
1	1	0	า่า	CLK33	Clock Data Register U2

Table 5-6. Output Decoder

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microprocessor section's SHSEL0 - SHSEL2 lines select the channel. The voltage from the selector charges the selected capacitor (C49-C56). The microprocessor section updates the DAC and selects the next channel. Thus, the microprocessor cycles through channels continuously refreshing the capacitors. Buffers (U20-U24) provide a high impedance which hold the charge on the capacitors.

The DAC supplies a maximum output of ±3 Vdc. Some control voltages require voltages greater than the ±3 Vdc, therefore, some control voltages are amplified. 5.7.6 Internal Calibration Network

During Autocal, the Internal Calibration Network in conjunction with circuits on other boards, makes vari-

ous voltage and frequency measurements and stores correction data in memory. On power up, these correction values are recalled from memory and, via the Sample and Hold Network, routed to control circuits within the Model 95. Each of the test points may have more than one value; for example frequency related test points may have different values for different frequency ranges. Figure 5-11 illustrates the entire internal calibration network used with in the Model 95. The network shown can simply be thought of as a series of selector switches that ultimately route a single test point to the DVM. The calibration network consists of two parts: the voltage measurement section (schematic 1104-00-3395 sheet 2 of 10) and the frequency mea-

Figure 5-11. Internal Calibration

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surement section (schematic 1104-00-3395 sheet 3 of 10). Both sections provide inputs to the Microprocessor section, or to be more specific, the Processor Support Chip.

The heart of the voltage measurement section is the DVM (U4 - Motherboard). The DVM receives a single dc voltage from the Multiplexer, Mux, (U3). The DVM is referenced to the +10Vdc voltage reference (U32 - schematic 1104-00-3395 sheet 8 of 10).

The DVM MUX 1 (U3 - schematic 1104-00-3395 sheet 2 of 10) selects one of its eight inputs for the DVM. Table 5-7 control lines, inputs and the function of the Mux inputs.

The DVM MUX 2 (U1 - Schematic 1104-00-3395 sheet 2 of 10) also selects one of eight inputs. But, its inputs

originate on the Output, Phase Lock Loop, and Function Generator boards. Table 5-8 describes the inputs and the control lines (DVM3, DVM4, and DVM5) that

The function generator's Autocalibration circuit (schematic 1104-00-3342 sheet 4 of 7) consists of an analog multiplexer (U28) which selects one of eight test points on the function generator board. The amplifier, U29A buffers the multiplexer's output. Another amplifier, U29B, amplifies the lower level signals by X101. The two amplifier outputs (FSTST and FGTST100) drives the Internal Calibration Network's DVM MUX 2. Table 5-9 describes the inputs and the control lines (A0, A1, and A2) that selects them.

DVM0	DVM1	DVM2	Name	Function
0	0	0	OUT1	Unbalanced output from "Unbalanced Output and Impedance
1	0	О	OUT2	BAL OUT (+) from "Balanced Output Attenuator Network and
0	1	0	OUT3	BAL OUT (-) from "Balanced Output Attenuator Network and Impedance Control
1	1	0	FGTST100	Low level function generator measurements
0	0	1	DVM BAT	Measures memory back up battery voltage "Microprocessor Section
1	0	1	OPTDVM2	Identifies Options 001 /002
0	1	1		Output from DVM MUX2. Voltages >+4V
1	1	1		Output from DVM MUX2. Voltages <+4V.

Table 5-7. DVM Mux 1

DVM3	DVM4	DVM5	Name	Function
0	0	0	FGTST	Output from Function Generator Mux U28 on Function
				Generator Board.
1	0	0	TEST IN	TP 1
0	1	0	+PK	Positive peak detector output from Output Board
1	1	0	THD	THD filter output from Output Board
0	0	1	Ground	Circuit Common
1	0	1	-PK	Negative peak detector output from Output Board
0	1	1	VLOOP	Phase Lock Loop filter output from Phase Lock Loop Board
1	1	1	OPTDVM1	Not used in the Model 95

Table 5-8. DVM Mux. 2

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Table 5-9	Function	Generator Mux.

	A0	A1	A2	Name	Function
,	0	0	0	Ground	Analog Ground
	1	0	0	VSUM	VCG Summing Amplifier Output from Function Generator Board.
	0	1	0	+FCV	Positive Symmetry Control output from Function Generator Board.
	1	1	0	-FCV	Negative Symmetry Control output from Function Generator Board.
	0	0	1	+COMP	Positive Output from the High Frequency Compensation DAC on
					the Function Generator Board.
	1	0	1	-COMP	Negative Output from the High Frequency Compensation
					DAC on the Function Generator Board.
	0	1	1	TRIBAL	Triangle Buffer output from the Function Generator Board.
	1	1	1	TRICOM	Triangle Buffer's Analog Ground from the Function
		L			Generator Board.

The Output Board's Peak Detector (schematic 1104-00-3335 sheet 6 of 6) selects and routes one of four voltages to the positive and negative Peak Detectors. The Peak Detectors consist of a positive half (U9A and U9D) and a negative half (U9B and U9C). Both detectors function the same, except for the polarity of the outputs. therefore only the positive peak detector will be described. Applying a positive voltage to U9A causes the amplifier's output to swing positive charging capacitor (C69) through diode (CB28). The amplifier (U9D) buffers the capacitor's voltage and provides feedback to the input amplifier (U9A). As the input voltage is reduced, the diode (CR28) becomes reversed biased and the capacitor (C69) holds a charge that represents the most positive (peak) voltage. The diode (CR35) provides local feedback to the input amplifier (U9A) while holding the peak. The transistor (Q20) discharges the capacitor (C69) when the PKRST line goes low which resets the peak detector. The relay (K7) bypasses

the peak detector when the Internal Calibration Network measure dc voltages from the Output Board. Three switches (U8A - U8C) select the inputs to the peak detector. Table 5-10 describes the inputs and the control lines that selects them

The THD Filter is a Twin Tee Notch filter that receives its input, SIN1, from the Sine Buffer on the Phase Lock Loop Board. The Filter (schematic 1104-00-3335 sheet 6 of 6) consists of the actual filter (U10B) and and rms Detector (U10A). The notch filter has a center frequency of about 10 kHz. The rms Detector provides a dc. voltage proportional to the harmonics of the 10kHz sine wave input.

The Frequency Measurement Section consists of three inputs to the Microprocessor Section; refer to paragraph 5.7.2.

Table	5-10.	Peak	Detector
	•

Control Line	Input Name	Function
SELPRE	AMSIG	Amplitude control signal from AM buffer from Phase Lock Loop Board.
SELBAL2	BOUT2	Negative Balance Driver output from Output Board.
SELBAL1	BOUT1	Positive Balance Driver output from Output Board.
SELPA	PA OUT	Power Amplifier output from Output Board.

Page 64

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6.1 INTRODUCTION

This section presents information, which when used with the Verification Procedure (Section 3), the Circuit Description (Section 5), and the Schematic and Assembly Drawings (Section 7), returns the Model 95 to operating condition. This section covers:

Factory Service,

Problem Isolation

Disassembly and Reassemble - including board removal.

6.2 ROUTINE MAINTENANCE

Section 2 of this manual covers routine maintenance of the Model 95.

6.3 FACTORY SERVICE

Wavetek maintains a factory repair department for those customers not possessing the personnel or test equipment to troubleshoot the instrument. If an instrument is returned to the factory for calibration or repair, a detailed description of the problem symptoms should be attached to minimize turnaround time.

Wavetek San Diego, Inc. 9045 Balboa Ave. San Diego, CA 92123 Telephone: (619) 279-2200 TWX: (910) 335-2007 FAX: (619) 595-9558

Before returning the instrument, call Wavetek's Customer Service department and obtain a Return Authorization Number; Wavetek uses this number to identify your instrument while it is in for repair.
The instrument should be packed according to the instructions in paragraph 2.3 of the Model 95 Operator's Manual.

6.4 BEFORE BEGINNING

Before beginning the troubleshooting process, verify that the instrument setup is correct. See section 3 of the Model 95 Operator's Manual.

Visually inspect the instrument for physical damage, paragraph 6.6.1.

Check the primary source:

1. Check the primary source.
2. Check the power cord.
3. Verify the primary supply voltage and the units voltage selection match; see paragraph 2.4.1 of the Model 95 Operator's Manual.
4. Check the unit's fuse; see paragraph 2.2 of this manual.

6.5 TROUBLESHOOTING PHILOSOPHY

The intent of this section is not to isolate failures to the component level but to give service technicians a set of "tools" that will guide them to the most likely circuit or circuits. From that point, the service technician must turn to the appropriate set of schematics and assembly drawings in the rear of this manual, and together with the circuit description (section 5) isolate the faulty component.

6.6 BEFORE TROUBLESHOOTING

6.6.1 Inspection

Before before beginning the troubleshooting procedure, use the following inspection procedures to locate obvious malfunctions with the Model 95.

1. Inspect all external surfaces of Model 95 for physical damage, breakage, loose or dirty contacts, and missing components.
2. Remove top cover, shield, and bottom cover to access components; paragraph 6.9.

WARNING

The Model 95 contains high voltages. After power is removed, discharge capacitors to ground before working inside the instrument to prevent electrical shock.

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CAUTION

Do not disconnect or remove any board assemblies in the Model 95 unless the instrument is unplugged. Some board assemblies contain devices that can be damaged if the board is removed with the power on. Several components, including MOS devices, can be damaged by electrostatic discharge. Use conductive foam and grounding straps when servicing is required around sensitive components. Use care when unplugging ICs from high-grip sockets.

3. Inspect printed circuit board surfaces for discoloration, cracks, breaks, and warping.
4. Inspect printed circuit board conductors for breaks, cracks, cuts, erosion, or looseness.
Inspect all assemblies for burnt or loose components.
6. Inspect all chassis-mounted components for looseness, breakage, loose contacts or conductors.
7. Inspect the Model 95 for disconnected, broken, cut, loose, or frayed cables or wires.

6.6.2 Test Point Access

Test point access on the vertically mounted boards requires that, during signal tracing, a board be connected to the mother board through special extender cards.

Since only one board can be extended at a time and still allow access to components and test points, the person performing the troubleshooting should review the fault and the fault isolation steps logically to determine a plan that will require the least amount of board removal and reinstallation.

CAUTION

Do not install or remove vertical board assemblies from the mother board with the operating power ON. Damage to components on the assemblies will occur if the assemblies are removed or inserted with operating power on.

CAUTION

Before removing Arb board, disconnect cables which are attached to board through holes in the rear shield.

Test points called out in the following procedures are shown on the assembly drawings and the schematic diagrams for each vertical board and the mother board. Three types of test points are shown. Numbered test points which are actual reference designator components on the board, and numbered test points which are locations on components that have been added as an aid in fault isolation. The final test points are actually pins on ICs and connectors.

Some circuits on the mother board and the phase lock loop board are shielded by rectangular metal cans soldered to the board traces. Test points located under these shields must be accessed from the solder side of the boards. Do not remove the shields except if repair is required in the shielded area.

6.6.3 Board Location

Figure 6-1 shows the location of the board assemblies in the Model 95.

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6.7 FAULT ISOLATION

This paragraph provides a series of procedures that when followed will point to recommended circuit blocks. Skip those procedures that do not apply to your symptom. Each circuit block reference will contain additional references to the proper Circuit Description paragraphs and Schematic and Assembly drawings. Use the circuit descriptions in conjunction with the schematics to gain a deeper understanding of the circuit block. Table 6-1 lists the recommended equipment necessary to troubleshoot the Model 95.

Table 6-1. Recommended Equipment
Equipment	Requirements
Scope	Dual trace, 20 MHz Bandwidth
Digital Voltmeter	Three Digit Accuracy (minimum).
Frequency Counter	>Four Digits of resolution, <±10
-	ppm accuracy. (Synthesizer and
	Optional Frequency Reference.
Board Extender Kit	Wavetek part number 1100-00-
	3411

6.7.1 Front Panel Not Active - Neither the front panel's display, annunciators, or keyboard operate.

1. Check the primary source; paragraph 6.4.
2. Visually inspect the unit; paragraph 6.6.

Secondary Supplies

1. Remove the top cover (see paragraph 6.9.1 Top Cover/Shield Removal)
2. Check the unit's secondary supplies using the digital voltmeter. Table 6-2 lists the power supplies, their voltages and tolerances, as well as drawing references. Test Points are located on the Motherboard. All voltages are referenced to analog ground (TP6). Also check the power supplies distribution system.

Power Supplies check OK.

1. Check the Microprocessor Section: Schematic 1104-00-3395 Sheet 3 of 10, Assembly drawing 1101-00-3395 sheet 1 of 3. For a description of the Microprocessor Section's circuits, refer to paragraph 5.7.2.
2. Check the microprocessor section: paragraph 6.8.16.

HINTS

Check the supply voltages to the circuits within the Microprocessor Section. Using the scope, check the control and data lines. Most lines should be "moving". Lines stuck high or low could identify a defective device.

3. If the key pad and display still do not operate, check the front panel input decoder, U4. Refer to schematic 0103-00-3001 sheet 3 of 3, assembly drawing 1101-00-3322 sheet 1 of 2, circuit description paragraph 5.7.4.5.

6.7.2 Front Panel Not Active - Keyboard Does Not Work

1. Refer to schematic 1104-00-3322, assembly drawing 1101-00-3322 sheet 1 of 2, and circuit description paragraph 5.7.4.5 Keyboard.
Check the supply voltages to the circuits within the Keyboard. Using the scope, check the control and data lines. Most lines should be "moving". Lines stuck high or low could identify a defective device.

6.7.3 Front Panel Not Active - Display Does Not Work

1. Refer to schematic 1104-00-3322, assembly drawing 1101-00-3322 sheet 1 of 2, and circuit description paragraph 5.7.4.5 Display.
Check the supply voltages to the circuits within the Display. Using the scope, check the control and data lines. Most lines should be "moving". Lines stuck high or low could identify a defective device.

Test Point	Supply Voltage	Tolerance	Schematic Drawing	Assembly Drawing
JMP 4	+12VDC	±0.2 Vdc	1104-00-3395 Sheet 8 of 10	1101-00-3396 Sheet 1 of 3
JMP 5	-12VDC	±0.2 Vdc	1104-00-3395 Sheet 8 of 10	1101-00-3396 Sheet 1 of 3
JMP 6	+5V	±0.2 Vdc	1104-00-3395 Sheet 8 of 10	1101-00-3396 Sheet 1 of 3
TP14	+24 VDC	±0.2 Vdc	1104-00-3395 Sheet 9 of 10	1101-00-3396 Sheet 1 of 3
TP15	-24VDC	±0.2 Vdc	1104-00-3395 Sheet 9 of 10	1101-00-3396 Sheet 1 of 3

Table 6-2 Power Supply Test Points

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6-4

6.7.4 Front Panel Not Active - Annunciators Do Not Work

1. Refer to schematic 1104-00-3322, assembly drawing 1101-00-3322 sheet 1 of 2, and circuit description paragraph 5.7.4.5 Annunciator Circuit.
Check the supply voltages to the circuits within the Display. Using the scope, check the control and data lines. Most lines should be "moving". Lines stuck high or low could identify a defective device.

6.7.5 Self Test and Self Test Error Messages

When power is first applied, the Model 95 performs Self Test. Self test checks the unit's internal battery, Motherboard memory, and storage memory. Failure of any of the tests will cause the Model 95 to display an error message. Table 6-3 defines the error messages. If Self Test is successful, the Model 95 will display "Wavetek Model 95".

6.7.6 AutoCal and AutoCal Error Messages

The Model 95 contains a powerful fault isolation tool: AutoCal. AutoCal measures numerous "test points" in the Model 95. It compares these measurements against either a frequency standard or voltage standard. AutoCal attempts to make correction for any deviations. But if AutoCal can not bring the measurement within limits, the Model 95 produces an error message. The Model 95 runs AutoCal until it hits its first error. Then it stops until the error is fixed by either performing the Calibration procedure, section 5, or isolating and fixing the problem. Continue running AutoCal until all problems have been identified and fixed.

To AutoCal the Model 95, perform the following steps. AutoCal requires no external test equipment. In fact, test equipment should not be connected to the Model 95's input connectors, otherwise the AutoCal could

alter the calibration of the instrument. Also, disconnect all outputs from the instrument otherwise the sudden changes in the instrument's output waveforms could damage external equipment.

1. Turn on the Model 95 and allow it to warm up for 20 minutes. Pressing the CALIBRATE key during the 20 minute warm up time displays the count-down time, after the 20 minutes the Model 95 begins AutoCal. Pressing any other key during the count down aborts AutoCal and returns the instrument to normal operation.

REMEMBER

Remove all input and output connections to the Model 95 before pressing AutoCal.

2. After a 20 minute warm up, press the SHIFT and CALIBRATE key and allow the unit time to complete the AutoCal cycle. While running AutoCal, the Model 95 displays "CALIBRATING". When completed successfully, the Model 95 displays "AUTOCALIBRATED". Then the unit returns to its last operational setup. If the AutoCal fails the Model 95 displays an error message which identifies the parameter - ERR ( Keyword ); for example ERR VSINCAL. If this occurs occasionally, try to AutoCal the unit again. Note the error keywords and report the errors when the unit is returned for scheduled maintenance.

Following is a listing of the AutoCal error messages. Included is a brief description of the AutoCal step. In addition, each step contains Pass/Fail instructions.

Display	Probable Cause	Corrective Action
Err xxxxxxxx	Improper self-check/unit	Press POWER key OFF and then ON. If identical failure error is displayed, refer to paragraph 6.7.1 - Power Supplies Check OK. If a different error is displayed, press the Calibrate key again. If "WAVETEK MODEL 95" is displayed, the unit is experience!
Low batt x.xxx v	Internal battery voltage low.	Unit is available for immediate operation. Refer to
Cal Required	Internal battery dead.	paragraph 2.3 for battery replacement. Unit has lost its calibration data but can be used after performing and passing AutoCal. Instrument may not meet all specifications.

Table 6-3. Self Test Error Messages

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VCG0 This check adjusts out frequency shift error in the function generator. The test sets the generator to 200 Hz on the 200 kHz range and using the internal calibration network adjusts out 1000:1 frequency errors (<0.7 Hz deviation).</td> Passes: Verifies the function generator operates correctly. No message will be displayed and AutoCal moves to the next step. Fail: If the unit displays the VCGO

message which means the Function Generator may not be working correctly. Use the procedure in paragraph 6.8.1 to isolate the faulty circuit.

VFREQ0 This check zeros the VCG summing amplifier with the VFREQ input connected. It also zeros the Function Generator board's Auto Cal circuit. Test requires the VSUM voltage be <20 mV of analog ground.

Passes: Verifies the VCG Summing Amplifier and Auto Calibration circuit operates correctly. No message will be displayed and AutoCal moves to the next step.

Fail: If the unit displays the VFREQ0 message which means the VCG Summing Amplifier or Auto Cal circuit may not be working correctly. Use the procedure in paragraph 6.8.1 to check the VCG Summing Amplifier. Use paragraph 6.8.9 to check the function generator's AutoCal circuit.

VFREQ0 SCL This check zeros the VCG Summing amplifier with the VFREQ input disconnected. It also zeros the Function Generator board's Auto Cal circuit. Test requires the VSUM voltage be <10 mV of analog ground.

Passes: Verifies the VCG summing Amplifier and Auto Calibration circuit operates correctly. No message will be displayed and AutoCal moves to the next step.

Fail: If the unit displays the VFREQ0 message which means the VCG summing amplifier or AutoCal circuit may not be working correctly. Use the procedure in paragraph 6.8.1 to check the VCG summing amplifier.

S+VCGOFF This check zeros (<20 mV) the positive symmetry control relative to the analog ground.</li> Passes: Verifies the positive symmetry control works. No message will be displayed and AutoCal moves to the next step. Fails: Check the Symmetry Control, paragraph 6.8.3.

S-VCGOFF This check zeros (<20 mV) the negative symmetry control relative to the analog ground.

Passes: Verifies the negative symmetry control works. No message will be displayed and AutoCal moves to the next step.

Fails: Check the Symmetry Control, paragraph 6.8.3.

VTRIBAL This check zeros (<59 mV) the triangle buffer, TRIBAL, relative to analog ground, TRICOM. Passes: Verifies the triangle buffer works. No message will be displayed and AutoCal moves to the next step.. Fails: Check the Triangle Buffer and Comparator, paragraph 6.8.2.

SYMM50PCT This check sets the symmetry control to 50%, symmetry off, and adjusts for 50% ±0.03% symmetry at 201 Hz on the 200 kHz range. Passes: Verifies the symmetry control

and current sources work. Nomessage will be displayed and AutoCal moves to the next step.

Fails: Check the symmetry control (paragraph 6.8.3) and current sources (paragraph 6.8.4).

+VCGOFF This check turns on the symmetry, sets the symmetry to 50%, and adjust the symmetry to 50%. Passes: Verifies the symmetry control and current sources work. Nomessage will be displayed and AutoCal moves to the next step. Fails: Check the symmetry control, paragraph 6.8.3.

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SWPLENGTH This check sets VSLEN (sweep length) DAC reference input and adjusts the sweep DAC to a specified frequency. Passes: Verifies the sweep generator works. No message will be displayed and AutoCal moves to the next step. Fails: Check the Sweep Generator, paragraph 6.8.10.
SCALEThis check sets VFREQ input to the VCG summing amplifier to a level that when the Scale switch is open causes the function generator to produces a 20 kHz signal. The internal calibration network adjusts VFREQ to 20 kHz±1Hz Passes: Verifies the frequency accu- racy at 1000:1 on the 20 MHz range. No message will be displayed and AutoCal moves to the next step.Falls:Check the function generator, paragraph 6.8.1. Also check the DAC Sample and Hold Network, paragraph 6.8.17.

TOFR7This check sets the function generator to the 200 kHz range. The internal calibration network measures and adjusts VFREQ to 200 kHz ±10 Hz. Passes: Verifies the frequency accu- racy at the top of the 200 kHz range. No message will be displayed and AutoCal moves to the next step. Fails: Check Frequency Range Switch Circuit, paragraph 6.8.7. Also check the function generator, paragraph 6.8.1.

TOFR6This check sets the function generator to the 20 kHz range. The internal calibration network measures and adjusts VFREQ to 20 kHz ± 1Hz. Passes: Verifies the frequency accu- racy at the top of the 20 kHz range. No message will be displayed and AutoCal moves to the next step.Fails: Check Frequency Range Switch Circuit, paragraph 6.8.7. Also check the function generator, paragraph 6.8.1.

TOFR5This check sets the function generator to the 2kHz range. The internal cali- bration network measures and adjusts VFREQ to 200 kHz ±0.15 Hz. Passes: Verifies the frequency accu- racy at the top of the 2kHz range. No message will be displayed and AutoCal moves to the next step.Fails: Check Frequency Range Switch Circuit, paragraph 6.8.7. Also check the function generator, paragraph 6.8.1.

TOFR4This check sets the function generator to the 200 Hz range. The internal calibration network measures and adjusts VFREQ to 200 Hz ±0.01 Hz. Passes: Verifies the frequency accu- racy at the top of the 200 Hz range, and verifies the operation of the ca- pacitance multiplier. No message will be displayed and AutoCal moves to the next step. Fails: Check the capacitance multi-

plier, paragraph 6.8.8. Also check the function generator, paragraph 6.8.1.

TOFR3 This check sets the function generator to the 20 Hz range. The internal calibration network measures and adjusts VFREQ to 20 Hz ±0.02 Hz.

Passes: Verifies the frequency accuracy at the top of the 20 Hz range, and verifies the operation of the capacitance multiplier. No message will be displayed and AutoCal moves to the next step.

Fails: Check the capacitance multiplier, paragraph 6.8.8. Also check the function generator, paragraph 6.8.1.

COMP9+ This check sets the function generator to 20 MHz range. Then sets VFREQ to 2MHz. Next the VFREQ value is set for 20 MHz, and the high frequency DAC adjusted for 20 MHz. The cycle repeats for up to 20 iterations. Passes: Verifies the 20 MHz range 10:1

frequency linearity. No message will be displayed and AutoCal moves to the next step.

Fails: Check the high frequency com-

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-		pensation circuit, paragraph 6.8.6. Also check the function generator, paragraph 6.8.1.
-	COMP8+	This check sets the function generator to 2MHz range. Then it sets VFREQ to 200 kHz. Next the VFREQ value is set for 2MHz, and the high frequency DAC adjusted for 2MHz. The cycle repeats
-		for up to 20 iterations. Passes: Verifies the 2MHz range 10:1 frequency linearity. No message will be displayed and AutoCal moves to
_		Fails: Check the high frequency compensation circuit, paragraph 6.8.6. Also check the function generator, paragraph 6.8.1.
-	FINDNOTCH	This check sets the function generator to a 10 kHz sine wave. Then using the notch filter and internal calibration
-		network adjusts the frequency (VFREQ) to 10 kHz. Passes: Verifies the sine convertor and
-		buffer, variable supply, and notch filter operates correctly. No message will be displayed and AutoCal moves to the next step.
-		Fails: Check the Sine Buffer, Sine Converter, and Variable Supply. See paragraph 6.8.11.
-	OFSTZERO	This check sets the function to dc and the offset voltage to OVdc. Then measuring the power amplifiers output with the internal calibration network adjusts the offset (VOEST) to c0 mV
-		Passes: Verifies the operation of the power amplifier. No message will be displayed and AutoCal moves to the next step.
-		Fails: Check the power amplifier; see paragraph 6.8.14. Also, check the DAC Sample and Hold Network, paragraph 6.8.17.
-	OFSTGAIN	This check sets the function to dc and the offset voltage to 5Vdc. Then measuring the power amplifiers output with the internal calibration network adjusts the offset gain (VOFST) to

+5Vdc±9mV.

Passes: Verifies the operation of the power amplifier. No message will be displayed and AutoCal moves to the next step.

Fails: Check the power amplifier; see paragraph 6.8.14. Also check the DAC Sample and Hold Network, paragraph 6.8.17.

BALOFFST This check sets the function to dc and the offset voltage to 0Vdc. The internal calibration network measures the two balanced outputs and adjusts the offset voltage (VOFST) so the difference between the two outputs is <3 mVdc. Passes: Verifies the operation of the balanced drivers. No message will be displayed and AutoCal moves to the next step.

Fails: Check the balanced drivers, paragraph 6.8.14.

SINEAMPL This check sets the function to sine wave and using the peak detector, measures the peak to peak amplitude of the sine wave, and adjusts amplifier output via VAMCAL to 20 ±0.03 Vpp. Passes: Verifies the operation of the function selector, preamplifier and multiplier, and AM buffer. Nomessage will be displayed and AutoCal moves to the next step.

Fails: Check the function selector (paragraph 6.8.14), preamplifier/multiplier (paragraph 6.8.14), and AM buffer (paragraph 6.8.14).

TRIAMPL This check sets the function to triangle wave and using the peak detector, measures the peak to peak amplitude of the triangle wave, and adjusts amplifier output via VAMCAL to 20 ±0.03 Vpp. Passes: Verifies the operation of the

Passes: Verifies the operation of the function selector, preamplifier and multiplier, and AM buffer. Nomessage will be displayed and AutoCal moves to the next step.

Fails: Check the function selector (paragraph 6.8.14), preamplifier/multiplier (paragraph 6.8.14), and AM buffer (paragraph 6.8.14).

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SQURAMPL This check sets the function to square wave and using the peak detector, measures the peak to peak amplitude of the square wave, and adjusts amplifier output via VAMCAL to 20 ±0.03 Vpp.

Passes: Verifies the operation of the function selector, preamplifier and multiplier, and AM buffer. No message will be displayed and AutoCal moves to the next step.

Fails: Check the function selector (paragraph 6.8.14), preamplifier/multiplier (paragraph 6.8.14), and AM buffer (paragraph 6.8.14).

BALAMPL This check adjusts the balanced output amplitude to 20 ±0.03 Vpp by measuring the balanced driver output with the peak detector and varying VAMCAL.

Passes: Verifies the operation of the balanced drivers. No message will be displayed and AutoCal moves to the next step.

Fails: Check the balanced drivers, paragraph 6.8.14. Also, check the -20 dB Attenuator, paragraph 6.8.14.

VSINCAL This check sets the function generator to a 10 kHz sine wave. Then using the notch filter and internal calibration network adjusts the sine wave harmonic distortion.

Passes: Verifies the sine convertor and buffer, variable supply, and notch filter operates correctly. No message will be displayed and AutoCal moves to the next step.

Fails: Check the Sine Buffer, Sine Converter, and Variable Supply. See paragraph 6.8.11.

ARBAMPL This check sets the function to Arb square wave and, using the peak detector, measures the peak to peak amplitude of the Arb square wave, and adjusts amplifier output via VAMCAL to 20 ±0.03 Vpp.

Passes: Verifies the operation of the Arbitrary waveform generator, function selector, preamplifier and multiplier, and AM buffer. The Model 95 has

completed the AutoCal cycle. Fails: Check the Arbitrary waveform generator (paragraph 6.8.13), function selector (paragraph 6.8.14), preamplifier/multiplier (paragraph 6.8.14), and AM buffer (paragraph 6.8.14).

6.8 BLOCK ISOLATION

The following procedures provide a method of isolating faulty circuit blocks. Most steps use test points; see paragraph 6.6.2.

6.8.1 Function Generator

Refer to the function generator assembly drawing (1101-00-3342) and schematic (1104-00-3342 sheets 2 through 7) in section 7 of this manual. Also, refer to paragraph 5.2 of this manual. Reset the unit by pressing SHIFT and RESET ALL keys.

1. First check the function generator board's power input. Schematic 1104-00-3342 sheet 1.
- TP20 +5 Vdc TP23 -12 Vdc TP25 +24 Vdc
- TP26 -24 Vdc
2. Check the following test points which will step you forward through the function generator. If the value at a test point is incorrect, isolate and repair the fault of the circuit between the good and bad test points.

22	VLOOP	Locked: +0.1 Vdc.
		Unlocked: -0.5 Vdc.
TP2	VSUM	-2 Vdc
TP4	-FCV	-4 Vdc.
TP3	+FCV	+4 Vdc
U22A-	1	+COMP ≈+2.6 Vdc
U22B-	7	-COMP ≈-2.6 Vdc
TP6	VI+	+17 Vdc.
TP7	VI-	-17 Vdc.
TP9	TRINODE	2.5 Vpp Triangle @ 1kHz.
TP12	TRIOUT	2.5 Vpp triangle @1kHz.
TP15	SQWAVE	2.25 Vpp square @ 1kHz

6.8.2 Triangle Buffer/Comparator

Refer to the function generator assembly drawing (1101-00-3342) and schematic (1104-00-3342 sheets 6 and 7) in section 7 of this manual. Also, refer to paragraph 5.2.2 - Comparator and Triangle Buffer. Reset the unit by pressing SHIFT and RESET ALL keys.

1. First isolate the triangle buffer and comparator circuits using paragraph 6.8.1.
2. Check the following test points which will step

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you through the triangle buffer and comparator. If the value at a test point is incorrect, isolate and repair the fault of the circuit between the good and bad test points.

28	ISWITCH+	3.5 Vpp@1kHz.
29	ISWITCH-	L 3.5 Vpp@1kHz.
TP9	TRINODE	2.5 Vpp Triangle @ 1kHz
TP12	TRIOUT	2.5 Vpp Triangle @ 1kHz.
27	TRI/SQR	2.5 Vpp@1kHz.
18	SQ1	1Vppsquareoffset+8Vdc
		@ 1kHz.
19	SQ2	4Vpp Square @ 1kHz.
TP15	SQWAVE	2.5 Vpp Square @ 1kHz.
TP13	REFSQR	2.5 Vpp square @ 1kHz.

6.8.3 Symmetry Control

Refer to the function generator assembly drawing (1101-00-3342) and schematic (1104-00-3342 sheet 3) in section 7 of this manual. Also, refer to paragraph 5.2.4. Reset the unit by pressing SHIFT and RESET ALL keys.

1. First isolate the symmetry control circuit using paragraph 6.8.1.
2. Check the following test points which will step you through the symmetry control circuit. If the value at a test point is incorrect, isolate and repair the fault of the circuit between the good and bad test points.

Jot pon
TP2	VSUM	-2 Vdc.
21	DAC ref	-6 Vdc
TP3	+FCV	+4 Vdc
TP4	-FCV	-4 Vdc

Verify the data line "wiggle". U12, pins 9, 10, 11, 12, 13, 14, 15, and 16. U17, pins 9, 10, 11, 12, 13, 14, 15, and 16. The following table identifies the enable DAC.

	DS1	DS2	A/B
Pin #	19	20	17
U7C Enabled	1	0	1
U7D Enabled	1	0	0
U12B Enabled	0	1	0
U12A Enabled	0	1	1

6.8.4 VCG Current Sources

Refer to the function generator assembly drawing (1101-00-3342) and schematic (1104-00-3342 sheet 3) in section 7 of this manual. Also, refer to paragraph 5.2.2, VCG Current Sources. Reset the unit by pressing SHIFT and RESET ALL keys.
- 1. First isolate the symmetry control circuit using paragraph 6.8.1.
- 2. Check the following test points which will step you through the symmetry control circuit. If the value at a test point is incorrect, isolate and repair the fault of the circuit between the good and bad

test points. +FCV +4 Vdc. TP5 +VCG +19 Vdc TP6 VI+ +17 Vdc 28 ISWITCH+ Γ. Γ. 13.5 Vpp@1kHz. TP4 -FCV -4 Vdc TP8 -VCG -19 Vdc TP7 -Vi -17 Vdc ISWITCH- 1 / 3.5 Vpp@1kHz. 20

6.8.5 Trigger Baseline Compensation

Refer to the function generator assembly drawing (1101-00-3342) and schematic (1104-00-3342 sheet 4) in section 7 of this manual. Also, refer to paragraph 5.2.5, Trigger Baseline Compensation. Reset the unit by pressing SHIFT and RESET ALL keys.

1. First isolate the symmetry control circuit using paragraph 6.8.1. Note, if the generator does not run, check this circuit.
2. Check the following test points which will step you through the trigger baseline compensation circuit. If the value at a test point is incorrect, isolate and repair the fault of the circuit between the good and bad test points.

U19-3	VSOURCE	+17 Vdc
TP5	+VCG	+19 Vdc
TP8	-VCG	-19 Vdc
17	RUN	+4 Vdc for continuous.
		0Vdc off.
TP9	TRINODE	2.5 Vpp

6.8.6 High Frequency Compensation

Refer to the function generator assembly drawing (1101-00-3342) and schematic (1104-00-3342 sheet 4) in section 7 of this manual. Also, refer to paragraph 5.2.5. Reset the unit by pressing SHIFT and RESET ALL keys.

1. First isolate the symmetry control circuit using paragraph 6.8.1.
2. Check the following test points which will step you through the high frequency circuit. If the value at a test point is incorrect, isolate and repair the fault of the circuit between the good and bad test points.

TP3	+FCV	+4 Vdc
U12C-2	Vref	-5 Vdc
U22A-1	+COMP	≈+2.6 Vdc
TP4	-FCV	-4 Vdc
U12A-8	Vref	+5 Vdc
U22B-7	-COMP	≈-2.6 Vdc

3. Verify the data lines "wiggle". U12, pins 9, 10, 11, 12, 13, 14, 15,. The following material identifies

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the enabled DAC.

	DS1	DS2	A/B
Pin #	19	20	17
U12C Enabled	1	0	1
U12D Enabled	1	0	0

6.8.7 Frequency Range Switches

Refer to the function generator assembly drawing (1101-00-3342) and schematic (1104-00-3342 sheet 5) in section 7 of this manual. Also, refer to paragraph 5.2.2, Frequency Range Capacitors and Ranges. Reset the unit by pressing SHIFT and RESET ALL keys.

1. First isolate the frequency range capacitor circuit using paragraph 6.8.1.
2. Check the test point, TP9 TRINODE, for a 2.5 Vpp triangle @ 1kHz.
Verify the following frequency range control lines are low: ≤₩5, ≤₩6, ≤₩7 ≤₩8. Note, in the default settings, the 2kHz to 200 Hz range is selected. For all frequencies above 200 Hz, refer to the control lines and capacitors listed in table 6-4..

6.8.8 Capacitance Multiplier

Refer to the function generator assembly drawing (1101-00-3342) and schematic (1104-00-3342 sheet 6) in section 7 of this manual. Also, refer to paragraph 5.2.2, Capacitance Multiplier. Reset the unit by pressing SHIFT and RESET ALL keys.

1. First verify the function generator operates correctly using paragraph 6.8.1.
Change the unit's frequency to 100 Hz. Check the test point, TP11 - CAP MULT, for 5Vpp @ 100 Hz.

Also verify the 2KHz range capacitor is selected: 0.52219 µF - C52, C53, C55, C57, C58, C67 ( $\leq$ FR5, $\leq$ FR6, $\leq$ FR7 $\leq$ FR8)

For frequencies below 200 Hz, refer to the control lines and capacitors listed in table 6-5.

6.8.9 Function Generator Auto Calibration

Refer to the function generator assembly drawing (1101-00-3342) and schematic (1104-00-3342 sheet 4) in section 7 of this manual. Also, refer to paragraph 5.7.6 This circuit is active only when AutoCal is being performed. The following describes the function generator auto cal mux controls.

	A 0	A1	A2	Name
U28 Pin	1	16	15
	0	0	0	Ground
	1	0	0	VSUM
	0	1	0	+FCV
	1	1	0	-FCV
	0	0	1	+COMP
	1	0	1	-COMP
	0	1	1	TRIBAL
	1	1	1	TRICOM

6.8.10 Sweep Generator

Refer to the function generator assembly drawing (1101-00-3342) and schematic (1104-00-3342 sheet 2) in section 7 of this manual. Also, refer to paragraph 5.5.3 Reset the unit by pressing SHIFT and RESET ALL keys.

1. First verify the function generator operates correctly using paragraph 6.8.1.
2. Select the sweep mode.
3. Check the following test points which will step you through the sweep generator. If the value at a test point is incorrect, isolate and repair the fault of the circuit between the good and bad test points.

	DS1	DS2	A/B
Check	the sweep D	AC.
U8-6	Sweep Out	Approx.	3 x (VSLEN)
U7A-8	Vref	-3 x (VS	LEN)
10-39	VSLEN

Pin #	19	20	17
U7A Enabled	0	1	1

Verify the DAC data lines (U7-9, 10, 11, 12, 13, 14, 15, and 16) step from 00000000 to 11111111.

Table 6-4. Frequency Range Switches

Range	Capacitors	Control
20 - 2 MHz	50 pF - (15 pF + Stray) C67	None
2MHz - 200 kHz	490 pF - C57, C58, C67
200 kHz - 20 kHz	0.00519 μF - C55,C57, C58, C67
20 kHz - 2kHz	0.05219 μF - C53,C55,C57, C58, C67
2kHz - 200 Hz	0.52219 μF - C52, C53,C55,C57, C58, C67

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	lable 6-5. Capad
Range	Capacitors		Control
200 Hz - 20 Hz	10 kΩ - R67		FR4
20Hz - 2Hz	110 kΩ - R67, R68		FB4, FB3
2Hz - 200 mHz	1.11 MΩ - R67, R68, R6	9	FRA. FR3. FR2
200 mHz - 20 mHz	11.11 MΩ - R67, R68, R	69. R71	All high
20 mHz - 2mHz	See Note
Note The Model s capacitors a by 1/10th eff input resisto	95 does not switch to the 20 m s the 200 mHz range, but it decre ectively dropping down a decad r (R8) in series with the VFREQ i	Hz range. It actu eases the input to le range by switch nput.	ually keeps the same range the VCG Summing Amplifier hing in, SCALE , an additional
A Check the Sween C	ut (Ramp) concreter test	Droop	the Man Trig key on the front name. The
4. Check the Sweep C	or (namp) generator test	togglo	the Man Thg key on the Iront panel. TP:
LI7A-21	Vref -6 Vdc	3 Refer	to paragraph 5.6 for a detailed description
SWEEP		of the	mode control and burst counter circuits
OUT Connector	0 to +5V linear ramp.	6 8 13 Arbitra	ry Waveform Generator
Check the Sweep (	Dut DAC.	Defer to the	Arb board accomply drawing (1101.00
DS1	DS2 A/B	3327) and so	hometic (1104 DO 2227 choote 2.4 and 5)
Pin # 19	20 17	in section 7	of this manual Also refer to the circuit
U7A Enabled 0	1 0	description	naragraph 5.3 of this manual Reset the
		unit by press	sing SHIFT and RESET ALL kove
Verify the DAC data	lines (U7 - 9, 10, 11, 12, 13,		the block edit mode (paragraph 3.5.19.7 of
14, 15, and 16)	step from 00000000 to	the M	ndel 95 Operators Manual) place a Arb
11111111.		souare	wave in the active memory at full ampli-
5.8.11 Sine Convertor, Buffer, a	and Variable Supply	tude.	Set the waveform frequency to 1kHz.
Refer to the Phase Lock Loo	bassembly drawing (1101-	2. Check	the test points in table 6-6 which will step
00-3341) and schematic (1	104-00-3341 sheets 5 and	you th	rough the Arb waveform generator. If the
6) in section 7 of this manual	Reset the unit by pressing	value a	at a test point is incorrect, isolate and repair
SHIFT and RESET ALL keys	S.	the fau	It of the circuit between the good and bad
First verify the function	n generator operates cor-	test po	bints.
rectly using paragrap	h 6.8.1.
2. Check the following	test points which will step	3. Check	the following test points which will step
you through the sine v	vave circuits. If the value at	you thi	rough the Arb waveform generator's RAM
a test point is incorrec	t, isolate and repair the fault	battery	control (schematic 1104-00-3327 sheet
of the circuit betwee	n the good and bad test	7). If tl	ne value at a test point is incorrect, isolate
points.		and re	pair the fault of the circuit between the
25 TRISIG	2.5 Vpp triangle @ 1kHz.	good a	and bad test points.
27 SINSIG	2.5 Vpp triangle @ 1kHz.	16	+5PV ≈+5 Vdc
TP13 SINCO	0.6 Vpp sine @ 1kHz.	TP14	4 VBAT1 +3.5 Vdc
TP10 SIN	2 Vpp sine @ 1kHz.
1P14 +12VADJ	Approximately +12 Vdc.	6.8.14 Output	Section
IP15 -12VADJ	Approximately -12 Vdc.	This procedu	are steps through each block of the output
5.8.12 Mode Control and Burst	Counter	block. Refe	r to the Output board assembly drawing
Refer to the Arb board ass	embly drawing (1101-00-	(1101-00-333	35), Motherboard assembly drawing (1101-
3327) and schematic (1104-	00-3327 sheet 2) in section	00-3395). O	utput board schematic (1104-00-3335).
7 of this manual. Reset the u	init by pressing SHIFT and	and Motherh	oard schematic (1104-00-3395 sheet 7) in

RESET ALL kevs.

Check the test point, TP3 - RUN, +4 Vdc.

Select the Triggered Mode. Check the test point, TP3 - RUN, 0Vdc.

00-3395), Output board schematic (1104-00-3335), and Motherboard schematic (1104-00-3395 sheet 7) in section 7 of this manual. Also, refer to the output section circuit description, paragraph 5.4.

Check the following test points which will step you through the output section. If the value at a test

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point is incorrect, isolate and repair the fault of the circuit between the good and bad test points

Square Shaper (schematic 1104-00-3335 sheet 2). Reset the unit by pressing SHIFT and RESET ALL kevs
O2 hase SORON≈0Vdc Select Square function
02 hase
SQRON>+2 5Vdc .IMP1 SOWAVE 2.25 Vpp square @ 1kHz.
TP1 2V P-P SQUARE 1Vpp square @1kHz.
2 Function Selector (schematic 1104-00-3335 sheet 3). Reset the unit by pressing SHIFT and RESET ALL KAVS
- 10 PREAMPIN 1Vpp square @ 1kHz. Select Sine function
- 10
- PREAMPIN 1Vpp sine @ 1kHz. Select Triangle function
- 19 PREAMPIN 1Vpp triangle @ 1kHz.
- On the Phase Lock Loop Board, (schematic 1104-00-
- 3341 sheet 4),
- 26 TRIOUT 1.5 Vpp triangle @ 1kHz. Select Arb Square
  - See paragraph 6.8.13.
3. Preamplifier and Multiplier (schematic 1104-00-3335 sheet 3). Reset the unit by pressing SHIFT and RESET ALL keys
- 10 PREAMPIN 1Vop sine @ 1kHz
- TP11 +6V +6 Vdc
- TP12 -6V -6 Vdc
- TP2 PREOUT 1.5 Vpp sine @ 1kHz offset +4 Vdc
AM Summing Amplifier (schematic 1104-00-3341 sheet 6). Reset the unit by pressing SHIFT and

RESET ALL kevs. VAMCAL Approximately 1.55 Vdc TP12 AMSIG -1.5 Vdc.

5 Power Amplifier (schematic 1104-00-3335 sheet 4). Reset the unit by pressing SHIFT and RESET ALL kevs TP2 PREOUT 1.5 Vpp sine @ 1kHz offset
- +4 Vdc 17 +22V +22 Vdc 16 -22V -22 Vdc TPA PA OUT 8Vnn sine @ 1kHz.
6 -20 dB Attenuator (schematic 1104-00-3335 sheet 5). Reset the unit by pressing SHIFT and RESET ALL Kevs
- TPA PA OUT 8Vop sine @ 1kHz. 20 UBOUT 5Vpp sine into 50Ω (10 Vpp unterminated).
7. Unbalanced Output Attenuator Network and Impedance Control (schematic 1104-00-3395 sheet 7). Reset the unit by pressing SHIFT and RESET ALL kevs. Turn the Output On.

P11-1 UBOUT 5Vpp sine into 50Ω (10 Vpp unterminated). Unhalanced

Output connector 5Vpp sine into 50Q (10 Vpp unterminated)

8 Balanced Drivers (schematic 1104-00-3335 sheet 5). Reset the unit by pressing SHIFT and RESET ALL keys. Select the 600Ω Balanced Output. Turn the output On.
- 18 Bal In 5Vpp sine @ 1kHz TP6 BOI IT2 5Vpp sine @ 1kHz TP7 BOUT1 5Vpp sine @ 1kHz.

Test Point	Name	Conditions
Arb Board
TP1	ACK1	4Vpp square @ sample frequency. Sample frequency = # of points between the start and stop addresses
TP5	-5V Supply	-5 Vdc
20	-1.2VREF	-1 2 Vdc
21	VREF	+5 Vdc.
TP6	UNFILTER
	OBSIG	1Vpp Arb square wave @ 1kHz
TP7	50K FILT	1Vpp Arb square wave @ 1kHz with filtering
TP8	5M FILT	1Vpp Arb square wave @ 1kHz with filtering
Output board
TP2	PREOUT	1.5 Vpp Arb square offset +4 Vdc @ 1kHz

Table 6.6 Arb Test Deine

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9 Balanced Output Attenuator Network and Impedance Control (schematic 1104-00-3395 sheet 7). Reset the unit by pressing SHIFT and RESET ALL keys. Select the 6000 Balanced Output. Turn the output On.

On the Output board check:

TP6 5Vpp sine @ 1kHz.
TP7 BOUT1 5Vpp sine @ 1kHz.

On the Motherboard, check:

.121 BAL OUT (-) 5Vpp sine terminated. J20
- BAL OUT (+) 5Vpp sine terminated.

6.8.15 Frequency Synthesizer and Phase Lock Loop

This procedure steps you through the frequency synthesizer and phase lock loop. Also, refer to paragraph 5.5.4. Refer to the following drawings:
- Motherboard assembly drawing 1101-00-3395. Motherboard schematic 1104-00-3395 sheet 4. Phase Lock Loop assembly drawing 1101-00-3341 Phase Lock Loop schematic 1104-00-3341 sheets 2 and 3.

Reset the unit by pressing SHIFT and RESET ALL keys.

Check the following test points on the frequency synthesizer (schematic 1104-00-3395 sheet 4). If the value at a test point is incorrect, isolate and repair the fault of the circuit between the good and had test noints
- 18 OSCIN 3.5 Vpp square @ 500 kHz.
- TP5 +3 Vdc Locked. and +5 Vdc VCLOOP Linlocked

TP17 SYOUT

4Vp TTL 50 ns pulses @ 1kHz.

Check the following test points on the phase lock loop (schematic 1104-00-3341 sheets 2, 3, and 4). If the value at a test point is incorrect isolate and repair the fault of the circuit between the good and bad test points.

TP3	SYNTH	arr with the second se
TP1	Z-CROSS	≈5Vpp Square @ 1kHz.
19	SQWAVE	≈3 Vpp Square @ 1kHz
20	1Y	≈4Vp pulses
21	2Y	≈3 Vpp square
22		3.5 Vp pulses
23		3.5 Vp pulses
TP7	VLEADR	≈4Vp pulses @ 500 Hz.
TP8	VLAGR	~4Vp pulses @

500 Hz

тр9 PLLER (VLOOP) Locked: +0 1Vdc Unlocked: -12 Vdc

3 If Option 001 - Frequency Reference is installed, check the following test points on the phase lock loop (schematic 1104-00-3327 sheet 6). TP11 TCXO Output ≈4Vpp square @ 10 MHz + 100m TP12 OSCIN ≈3.5 Vpp square @ 500 kHz. REF OUT TTL square @ 10 MHz.

Connect a 10 MHz TTL signal to the Ref In connector TP10 EXTREE TTL square @ 10 MHz.

6.8.16 Microprocessor Section

1 Check the Microprocessor Section: Schematic 1104-00-3395 Sheet 3 of 10. Assembly drawing 1101-00-3395 sheet 1 of 3. For a description of the Microprocessor Section' circuits, refer to paraoraph 5.7.2.
Observe the Microprocessor's Life Lite. During 2 normal operation the Microprocessor's Life Lite blinks at a rate of about 2 or 3 blinks per second If the Life Lite blinks, the Microprocessor Section is functioning correctly.

Non-Blinking Life Lite - Microprocessor Section inoperative. The LED may be continuously on or off. If continuously on, the power supplies are probably operational and the fault is in the microprocessor circuits. If continuously off, the possibility of power supply failure should be checked prior to microprocessor circuit troubleshooting.

3. Check the supply voltages to the circuits within the Microprocessor Section.
Δ Using the scope, check the control and data lines. Most lines should be "moving". Lines stuck high or low could identify a defective device.

6.8.17 DAC Sample and Hold Network

Refer to the Motherboard assembly drawing (1101-00-3395) and schematic (1104-00-3395 sheet 5) in section 7 of this manual. Also refer to the circuit description. paragraph 5.7.5 of this manual. Reset the unit by pressing SHIFT and RESET ALL keys.

Check the following test points. If the value at a test point is incorrect, isolate and repair the fault of the circuit between the good and bad test points.

TP7	SHDAC	Verify a stepped waveform.
R33/R34	VOFST	≈0Vdc
U21B-7	VAMCAL	Verify a dc voltage.
U22B-7	VSLEN	Verify a dc voltage.
U23B-7	VFREQ	Verify a dc voltage.

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U22A-1	VCGZERO	Verify a dc voltage
124B-7	VPHASE	Verify a do voltage

		voning a do vonago.
U21A-1	VSINCAL	Verify a dc voltage.

1/24A-1 VTRIBAL Verify a dc voltage.

6.8 18 GPIR Section

Refer to the Motherboard assembly drawing (1101-00-3395) and schematic (1104-00-3395 sheet 10) in section 7 of this manual. Also refer to the circuit description, paragraph 5.7.3 of this manual.

To troubleshoot the GPIB section

1. Check the digital control lines to the GPIB board. Verify the overhead signals work correctly (E clock, Read/Write, chip select).
2 Check the address and data lines between the GPIA (U8) and the microprocessor section.
3. Check the lines connecting the GPIA and transceiver (U9 and U10)
Δ Check the lines between the transceiver and the GPIB controller

6.8.19 Board Interfaces

Each of the Model 95's boards contains interface circuits that "translates" address/data information from the microprocessor section for use on the board. Troubleshooting these interfaces checking the boards enable lines and verifying the activity on the address and data lines

Function Generator Board Interface

Schematic: 1104-00-3342 sheet 1. Assembly: 1101-00-3342 Circuit Description: paragraph 5.7.4.1. Phase Lock Loop Board Interface

Schematic: 1104-00-3341 sheet 1 Assembly: 1101-00-3341 Circuit Description: paragraph 5.7.4.2 Arh Roard Interface

Schematic: 1104-00-3327 sheet 1. Assembly: 1101-00-3327 Circuit Description: paragraph 5.7.4.3.

Output Board Interface

Schematic: 1104-00-3335 sheet 1. Assembly: 1101-00-3335 Circuit Description: paragraph 5.7.4.4. Front Panel Interface Schematic: 1104-00-3322 sheet 2.

Assembly: 1101-00-3322 Circuit Description: paragraph 5.7.4.5.

6.9 DISASSEMBLY AND REASSEMBLY

6.9.1 Disassembly

Top Cover/Shield Removal

To remove the top cover and shield.

1. Set the POWER switch to OFF (extended).
2. Remove the power cable from the rear panel Dower connector
Remove the five screws that secure the top cover: four in the top and one at the rear. Two of the four top cover screws are located under the Calibration Label
۸ Slide the top cover toward the rear and remove Then lift off the shield.

Bottom Cover Removal

To remove the bottom cover

Set the POWER switch to OFF (extended).
2 Remove the power cable from the rear panel power connector.
Turn the Model 95 upside down.
4 Remove the three screws that secure the bottom cover: one in the bottom cover and two in the rear. The one screw on the bottom cover is located under the Calibration Label
Slide the bottom cover towards the rear and 5. remove

6.9.2 Board Removal/Replacement

To remove the Output, PLL, Function Generator, or Arb board

Perform the steps in paragraph 6.9.1 - Top Cover/Shield Removal.

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2. Disconnect the cable from the Output Board. Disconnect the four cables from the Arb Board.
3. Lift out the board using the extractors.
To replace the Output, PLL, Function Generator, or Arb board
- 1. Place the board in its guide and press it down to lock it in the connector
- 2. Connect the cable to the Output Board. Connect the four cables to the Arb Board.
- 2 Perform the steps in paragraph 6.9.3 Top Cover/ Shield Reassembly.

6.9.3 Reassembly

Bottom Cover Replacement

To replace the bottom cover,

1. Turn the Model 95 upside down.
Slide the bottom cover into the slots on the bottom.
3. Secure the bottom cover with three screws (two in the rear and one on the bottom cover).

Top Cover Replacement

Top replace the top cover,

1. Turn the Model right side up.
2. Install the shield, aligning the screw holes.
3. Slide the top cover into the slots on the top.
Secure the top cover using five screws (one at the rear and four in the top). The four top cover

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SECTION PARTS LISTS AND SCHEMATICS

71 DRAWINGS

The following assembly drawings, schematics, and parts lists are arranged in order shown below. 7.1.1 Assembly Drawing

All of the mechanical assembly drawings are show in this section. These drawings contain enough detail and clarity to assist the repair technician in the disassembly and reassembly of the Model 95. The parts lists for each assembly drawing immediately follows that drawing.

712 Schematics

All of the schematics for the Model 95 are shown in this section. Schematic drawings containing a proprietary message may not be copied for resale or use in any other publication nor for any use other than the repair and maintenance of the instrument associated with this manual

7.1.3 Parts Lists

The parts lists for each individual board or assembly are shown immediately following that board or assembly. The parts lists contain Wavetek and manufacturers

DRAWING

parts information. All manufacturers are listed by a Wavetek code designation.

7.2 ADDENDA

Under Wavetek's product improvement program, the latest electronic designs and circuits are incorporated into each Wavetek instrument as guickly as development and testing permits. Because of the time needed to compose and print instruction manuals, it is not always possible to include the most recent changes in the initial printing. Whenever this occurs. addendum pages are prepared to summarize the changes made and are inserted immediately inside the rear cover. If no such pages exist, the manual is correct as printed.

7.3 ORDERING PARTS

When ordering spare parts, please specify the part number, circuit reference, board, serial number of the unit, and, if applicable, the function performed.

The number etched into a PC board is the board part number. The assembly (PC board and components on the board) part number is stamped on the board.

DRAWING NUMBER

Top Assembly Drawing	1001-00-0599
Instrument Schematic	1004-00-0599
Instrument Parts List	1000-00-0609
Installation Drawing	0002-00-0599
Motherboard Schematic Motherboard Assembly Motherboard Parts List	1104-00-3395 1101-00-3395 1100-00-3390 1200-00-3390
Front Panel Assembly	1101-00-3344
Front Panel Assembly Parts List	1100-00-3344
Display / Keyboard Assembly Schematic	1104-00-3322
Display / Keyboard Assembly	1101-00-3322
Display / Keyboard Assembly Parts List	1100-00-3322
Output Board Schematic	1104-00-3335
Output Board Assembly	1101-02-3335
Output Board Parts List	1100-00-3335

Page 82

DRAWING
Phase Lock Board Schematic	1104-00-3437
Phase Lock Board Assembly	1101-00-3437 –
Phase Lock Board Parts List	1100-00-3437
Function Generator Board Schematic	1104-00-3342
Function Generator Board Assembly	1101-00-3342
Function Generator Board Parts List	1100-00-3342
Arb Board Schematic	1104-00-3327
Arb Board Assembly	1101-00-3327
Arb Board Parts List	1100-00-3401
Rear Panel Assembly	1101-00-3325
Rear Panel Assembly Parts List	1100-00-3325
Tilt Bail Assembly	1201-00-3392
Tilt Bail Parts List	1200-00-3392
	1200-00-0002

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	8 \|	6	T	5	*	4			3	2		_	1
ľ	THIS DOCUMENT CONTAINS PROPRIETARY INFORMATION AND DESIGN RIGHTS DELONGING TO WAVETEK AND MAY NOT										REY		ECO BY	DATE APP
	BE REPRODUCED FOR ANY REASON EXCEPT CAUBINATION. OPERATION, AND MAINTENANCE WITHOUT WRITTEN AU- THORIZATION

		-								CART DECERTION	ORIG-HEAR-PART-NO	MEOR	WAVETEK ND	QTY/PT
			REFERENCE DESIGNATORS	PART DESCRIPTION	DRIG-MFOR-PART-ND	MFCR	WAVETEK ND.	GTY/PT	REFERENCE DESIGNATORS	PART DESCRIPTION			1001 00 0500	D
וי			42	LABEL, CABLE	1400-02-5117	WVTK	1400-02-5117	1	NONE	A/D, INSTRUMENT	1001-00-0599	WVTK	1002-00-0599	1
			23	DRIENTATION	334608~1	AMP	2100-07-0024	1		PROCEDURE	1004-00-0809	LINTK	1004-00-0599
			JE	CONN			5400 OF 0020	\|. \|	NONE	S/D. INSTRUMENT	1004-00-0399	WVTK	1006-00-0599	1
			18	FUSE, 1A, 250V, S-B	4-32 NUT F.L.	CHRCL	2800-15-6100	4	1015		1008-00-0596	WUTK	1008-00-0396	1
			20	NUT, HEX, 1/2-28	1-329631-2	ANP	2800-16-0025	5	NUME	PROCEDURE, MODEL 90			1007-00-0599
			24	LOCKWASHER, WØ SPLIT RING, SS	485RLH	CHIRCL	2800-42-8000	з	NONE	LABEL/DRWG, INFO, S/N & PWR-95	1009-00-0399	HVIK	1007-00-0377
-			22	SCREW, 6-32X3/4 FH	6-32 X 3/4 F. H. 100	CHRCL	2600-44-6112	4	NONE	REAR PANEL ASSY, MODEL 90	1100-00-3325	HUTK	1100-00-3325	1
-		1	1	SCREW PLPS PAN M/S	MS 51957-28	CHRCL	2800-48-6106	з	NONE	PCA, DUTPUT BOARD	1100-00-3335	HVTK	1100-00-3335	1
			33	SCREW PLPB PAN M/S	SCREW PH 8-32X1/2	CHRCL	2800-46-8108	э	NONE	PCA, FUNCTION GENERATOR	1100-00-3342	WV TK	1100-00-3342
			30	18-8 9/8 8-32X1/2	E 2800-54-B107	CHCRL	2800-54-8107	6	NONE	ASSY, FRONT PANEL	1100-00-3344		1100-00-3344
			20	C FH, PHLPS, SS			7000-59-4105		NONE	PCA, ARE BOARD OPT 1	1100-00-3401	WVTK	1100-00-3401	1
			27	SCREW, PH, 6-32 X 5/16, PHLPS, NYLOK, 55	2800-54-6105	CRACE	2800-37-8103			AND 2, MODEL 95	1100-00-3437	WVTK	1100-00-3437	1
с			2	SCREW, 6-32/3/8, FH. PH PS, 100 DEC, SS, NYLDK	2800-60-6106	CHRCL.	2800-60-6106	5		FCM FINDL LOUR LOUR					-
		-						DEV		TLE	ASSEMBLY	NO. 1000-4	00-0409	REV
				TITLE MODEL 95 W/001/002	ASSEMBLY	1000-0	0-0803	D		JDEL 95 W/001/002		PAOF 1
		L				PAGE 3					I
									5
															5
*		ſ	REFERENCE DESIGNATORS	PART DESCRIPTION	DRIG-MFOR-PART-ND	NFOR	WAVETEK NO	оту/рт	REFERENCE DESIGNATORS	PART DESCRIPTION	DRIC-HFOR-PART-ND	MFCR	WAVETEK NO.	OTY/PT	F
		1							NONE	ASSY, SIDE PLATE,	1200-00-3347	WVTK	1200-00-3347	1
			NONE	PWR CORD, SHIELDED	6001-80-0009	WVTK	6001-80-0009	1	NONE	ASSY, SIDE PLATE,	1200-00-3348	WVTK	1200-00-3348	. 1
									NONE	LEFT ASY ASSY, COAX J32	1200-00-3381	WVTK	1200-00-3381	. 1
									NONE	ASSY, CDAX J33	1200-00-3382	WVTK	1200-00-3382	- 1
									NUNE	COAX ASSY, J34	1200-00-3383	WTK	1200-00-3383
									NDNE	TILT BAIL ASSY	1200-00-3392	WVTK	1200-00-3426	3 4	В
									NONE	LABEL, CAUTION	B57-1400	HVTK	1400-01-1400	1
		÷.							NONE	LABEL, OPTION, MODEL	1400-017870	WVTK	1400-01-9890	, 1
× (									NONE	SHIELD, INNER	1400-02-3323	HVTK	1400-02-3323	3
Į.						1			NONE	SHIELD, TOP	1400-02-3353	HVTK	1400-02-3353
									NONE	COVER, TOP	1400-02-3532	WTK	1400-02-4526	2 1	L
									NONE	LABLE, SHE CONNECTOR	Z 1400~02~5076	WVTK	1400-02-5076	5 1	F
-									MONTE	AXIS SHIELD, REAR	1400-02-5084	WVTH	1400-02-5084	4 1
- 1											1
			WAVETEK		ASSEMBL	NO. 1000-	00-0609	REV	WAVETEK ,	TITLE 100EL 95 W/001/002	ASSEMBI	YND. 1000	000607	REV D	L
			PARTS LIST	HUDEL 73 W/001/032		PAGE 4			PARTS LIST			PACE 2
ē		l.	L		I ,
											DRAWN DATE 1	A /A-			1
A										AND BREAK SHARP EDGES	CHECKED		ETEK	LAN DIEGO & CALIFORNIA	ť
											PRDJ. ENGR		PARTS LIS	т
Ň										FINISH	RELEASE APPROV.		INSTRUME	ΝT
										WAVETEK PROCESS	UNLESS OTHERWISE SPECIFIED	IZE FSCM NO.	DWG NO	REV	1
	NOTE: UNLESS OTHERWISE SPECIFIED										FRACTIONS DECIMALS ANOLES	D 2333	1000-00	J-0609 D	+

7-5

DO NOT SCALE DRAWING

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-	o \| / /	υ	ບ 👻 🦷	•
	HIS DOCUMENT CONTAINS PROPRIETARY INFORMATION NO DEMON REALTS BELONGING TO WAVETEX AND MAY NOT E REPRODUCED FOR ANY REASON EXCEPT CALIBRATION, PERATION, AND MAINTENANCE WITHOUT WRITTEN AU- HOREATION		•			REV ECO BY DATE APP A ER0 #: 90-462 AT 7.2-90 DEF B EC0 #: 90-506 MS 9-14:90 NM C EC0 #: 90-521 MS Multi/90 NM D EC0 #: 91-116 27± V31/91
	FRONT PANEL BOARD CONNECTOR	OUTPUT BOARD CONNECTORS	BOARD CONNECTORS	BOARD CONNECTORS	CONNECTORS
C	J12 0GN0 1 0A0 2 0D6 3 0D4 4 0D2 5 0D0 6 P10 7 P11 10 P12 9 P14 10 P15 11 DGND 12 45PV 13 DGND 14 DGND 15 FIL_A 16 DGND 19 -24PV 20 FPSTB 21 0A1 22 0D5 24 0D3 226 DGND 22 P13 229 P15 30 P13 229 P15 33 RKA 34 RKA 38 DGND 37 +24PV	P10 SWNTH 2 DGND 3 QA2 5 TRISEL 6 QD5 7 QD4 8 QD2 9 QD0 10 DGND 11 +5PV 12 AGND 11 +5PV 12 AGND 11 +5PV 12 AGND 13 DGND 14 CLK0 15 TRIOUT1 16 AGND 17 AMSIG 18 AGND 17 AMSIG 18 AGND 21 PLS/SOR 22 DGND 23 DBSTB 24 QA1 225 DGND 226 QD7 27 QD3 229 QD1 30 DGND 33 OBSIG 34 AGND 33 OBSIG 34	FP8 SOWAVE 1 SYNTH 2 DGND 3 QA0 4 QA2 5 TRISEL 6 QD4 8 QD2 9 QD0 10 DGND 11 +5PV 12 AGND 11 +5PV 12 AGND 13	P6 SOWAVE 1 SYNTH 2 PLSTB 3 GA0 4 GA2 5 DGND 6 GD6 7 GD4 8 GD2 9 GD0 10 DGND 11 +5PV 12 AGND 11 +5PV 12 AGND 11 +5PV 12 AGND 11 +5PV 12 AGND 11 AGND 11 +5PV 12 AGND 19 MOD_IN 20 BXFREG 22 DGND 21 PLS/SOR 22 DGND 223 FGSTB 24 GA1 25 DGND 31 +5PV 32 AGND 33 -335 34 VCGZERO 36 VSLEN 39	P30 S0WAVE 12 DGND 3 GA0 4 GA2 5 DGND 6 GD6 7 GD6 7 GD6 7 GD6 7 GD6 7 GD6 7 GD6 7 GD6 7 GD7 11 SPU 112 AGND 11 +SPV 112 AGND 11 +SPV 112 AGND 11 +SPV 112 AGND 21 PLS/SOR 221 PLS/SOR 222 GGND 223 GOSTB 224 GA1 225 GA3 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 225 GOS 2	D
В	POWER SUPPLY UNREGULATED P4 AC INPUT	P11 UBOUT 1 AGND 2 BOUT1 3 BOUT2 4 AGND 5 -12PV 6 AGND 7 +12PV 8 AGND 9 +24PV 10 AGND 11 -24PV 10 AGND 11 -24PV 10 AGND 11 -24PV 10 AGND 11 -24PV 12 THD 13 AGND 14 -PK 15 +PK 16 AGND 19 +12PV 20 AGND 21 +24PV 22 AGND 23 -24PV 24	P9 MOD_IN 1 AGND 2 THISIC 3 AGND 4 5 - -12PV 6 AGND 7 +12PV 8 AGND 7 +12PV 8 AGND 11 -24PV 10 AGND 11 -24PV 12 AGND 13 VAMCAL 15 VSINCAL 16 AGND 17 -12PV 20 AGND 19 +12PV 20 AGND 21 +24PV 22 AGND 23 -24PV 24	P7 SWPOUT 1 THISIG 2 VTRIBAL 3 AGND 4 -12PV 6 AGND 5 -12PV 6 AGND 7 +12PV 8 AGND 9 +24PV 10 AGND 9 +24PV 10 AGND 11 -24PV 12 FGTST100 11 -24PV 12 FGTST100 11 AGND 11 -24PV 12 FGTST100 11 -24PV 12 FGTST100 11 AGND 11 -24PV 12 FGTST100 11 AGND 11 -24PV 12 FGTST100 12 14 SGR 15 RUN 16 AGND 17 -12PV 18 AGND 21 +24PV 22 AGND 21 +24PV 22 AGND 221 +24PV 223 -24PV 24	P31 AGND 2 AGND 2 RUN 4 AGND 5 -12PV 6 AGND 7 +12PV 6 AGND 9 +24PV 10 AGND 11 -24PV 12 OPTDVM2 13 AGND 14 OSCIN 16 AGND 17 -12PV 20 AGND 19 +12PV 20 AGND 21 +24PV 20 AGND 23 -24PV 24	B [] [104-00-3395
	A. PART NUMBER. 6. * = PART INSTALLED IN SOCKET. 5. CAPACITORS VALUED IN MICROFRADS (UF). 4. RESISTORS VALUED IN OHMS, 1/8W, 5%. 3. FOR INSTRUMENT INTERCONNECTION, SEE INSTRUMENT SCHEMATIC 1004-00-0559 FOR MODEL 90 AND 1004-00-0599 FOR MODEL 95. 2. INSTALL JMP1 ON PINS 1 & 2 FOR BIPOLAR EXT FREQ INPUTS. INSTALL ON PINS 2 & 3 FOR TIL EXT FREQ INPUTS. INSTALL JMP7 DN PINS 1 & 2 FOR STANDARD INSTRUMENT. INSTALL ON PINS 2 & 3 FOR OPTION 001. NOTE: UNLESS OTHERWISE SPECIFIED	6	5	4 3	CAD JOB#: B064E REMOVE ALL BURRS AND BREAK SHARP EDGES MATERIAL GOTE MIAILISTER PROJEKT FIRESH WAVETER PROCESS DO NOT SCALE DRAWING Z	DATE 10-20 -2-90 TITLE -2-90 SCHEMATIC, MOTHERBOARD SIZE FISCH HO. D 23338 1104-00-3395 D SCALE NONE MODEL 90 SERIES SHEET 1 OF 10 1 7

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8		5	+	4	1		3	. I - 2	2 1		а
DOCUMENT CONTAINS FROPRIETARY UNFORMATION ESIGN RIGHTS BELONGING TO WAVETEK AND MAY NOT OPRODUCED FOR ANY REASON EXCEPT CALIBRATION, ATION, AND MAINTENANCE WITHOUT WRITTEN AU- (ZATION.									REV	). ).	ECO BY	DATE AF

	REFERENCE DESIGNATORS	PART DESCRIPTION	DRIG-MFOR-PART-NO	MFOR	WAVETEK ND.	QTY/PT		PART DESCRIPTION	DRIG-HEGR-PART-ND	HFOR	WAVETER ND.	ату/рт
	NONE	A/D MOTHER BD 90/95	1101-00-3395	HVTK	1101-00-3395	i	13	NADISTR.
	NONE	SCHEMATIC, PCA HOTHER BOARD MODEL 90	1104-00-3395	WVTK	1104-00-3395	1	12	RIVET, 1/B BODY	560435885	EMHRT	2800-11-0015	3
	NONE	90/95 MOTHERBOARD PREMAVE LOAD	1200-00-3390	WVTK	1200-00-3390	1	25	DIA, 1/8-3/16 ORIP SS	N935649-264	CDHL	2800-14-6100
	HL .	FAN CABLE ABBY	1200-00-3429	WVTK	1200-00-3429	1	26	WASHER 06 BAE FLAT, . 375 D. D.	6 SAE FLAT WASHER	CHRCL.	2800-26-6000	1
	19	CAN, SYNTHEBIZER	1400-02-3443	WVTK WVTK	1400-02-3443	1	10	HOLE PLUC, BINDER	207-120241-03-0101	FASTX	2800-35-0009	6
	Э	THERMAL QASKET-REAR	1400-02-4400	WVTK	1400-02-4400	a	27	#6 LOCKWASHER, PLATED	94SRLW	CHRCL.	2800-42-6000	1
	23	THERMAL GASKET-REAR	1400-02-4410	WVTK	1400-02-4410	1	14	HASHER, LOCK REC, S/S	MB 35338-135	CHRCL	2800-45-4000	5
	28	HEATSINK BRIDDE	1400-02-4463	WVTK	1400-02-4463	1	15	SCREW PLPS PAN M/S 18-8 S/S 4-40X1/4	MS 51957-13	CHRCL	2800-48-4104	5
	1	BUPPPORT PLATE,	1400-02-5007	WVTK	140002-5007	a	24	BCREW, PH, PHLPB, 6-32X9	2800-61-6109	CHCRL	2800~61-6109	1

227161-1

929950-00

929834-01-03

2100-01-0019 5

REV

APTRN 2100-02-0196 1

APTRN 2100-02-0213 2

HAKE 2800-11-0001 2

AMP

ASSEMBLY NO. 1100-00-3390

PACE 1

010

VR3 VR7

VR4 VRB

WAVETEK

PARTS LIST

TRANS

TITLE PCA, MOTHER BOARD

VOLT REQULATOR, 3 TERMINAL ADJUSTABLE POS

VOLT REGULATOR

J15 J16 J17 J18 J17

WAVETEK

PARTS LIST

XJMP1

JMP1 JMP7

CONN, BNC (PC)

HEAT BINK

TITLE PCA. MOTHER BOARD

CONN, HEADER, 3 PIN

JUMPER, FEMALE, 2 POSITION, 0.1 SPACE

REFERENCE DESIGNATORS	PART DESCRIPTION	DRIG-MFOR-PART-NO	MFOR	HAVETEK NO.	QTY/PT
015	EPROM. PRD9 USEA 1 EA B002-75-1200 FOR MOD 95 V1.3 REF U12	B400-00-0456	WTK	8600-00-0626	1









	ITLE CA, MOTHER BOARD		0 1100-0	00-3390	REV K

T1P-36

LH317T

LH337T

ті

NSC

ASSEMBLY NO 1100-00-3390

PACE 2

4902-00-0360 1

7000-03-1700 2

7000-03-3700 2

REMOVE ALL BURAS AND BREAK SHARP EDGES	DIAWN	N		TEK
MATERIAL	CHECKED	1011			BAN DIEGO + CALVE	RHIA
	PROJ. ENGR	Conne-	F		эт
FINISH	RELEASE APPROV.	1	MO	THERBO	ARD
WAVETEK PROCESS	UNLESS OTKERWISE SPECIFIED DIMENSIONS ARE IN INCHES	SIZE	FSCM NO.	DWG. ND.		REV
	FRACTIONS DECIMALS ANGLES	D	23338	1100-0	0-3390	ĸ
DO NOT SCALE DRAWING	* XX * *	SCALE	M	odel 95	SHEET 1	DF 1
	2			1	7	20

NOTE: UNLESS OTHERWISE SPECIFIED