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bq2010

Gas Gauge IC

Features

Conservative and repeatable

➤

measurement of available charge in rechargeable batteries

Designed for battery pack inte

➤

gration

120µA typical standby current

Small size enables imple-

mentations in as little as square inch of PCB

Integrate within a system or as a

➤

stand-alone device

Display capacity via single-

wire serial communication port or direct drive of LEDs

➤ Measurements compensated for

current and temperature

➤ Self-discharge compensation us-

ing internal temperature sensor

➤ Accurate measurements across a

wide range of current (> 500:1)

➤ 16-pin narrow SOIC

General Description

The bq2010 Gas Gauge IC is intended for battery-pack or in-system installa tion to maintain an accurate record of a battery's available charge. The IC

monitors a voltage drop across a

sense resistor connected in series be tween the negative battery terminal and ground to determine charge and discharge activity of the battery.

NiMH and NiCd battery self-dis charge is estimated based on an inter nal timer and temperature sensor. Compensations for battery tempera ture and rate of charge or discharge are applied to the charge, discharge, and self-discharge calculations to pro vide available charge information across a wide range of operating conditions. Battery capacity is automatically recalibrated, or “learned,” in the course of a discharge cycle from full to empty.

Nominal available charge may be directly indicated using a five- or six-segment LED display. These segments are used to indicate graphically the nominal available charge.

The bq2010 supports a simple single-line bidirectional serial link to an external processor (common ground). The bq2010 outputs battery

information in response to external commands over the serial link.

The bq2010 may operate directly

from 3 or 4 cells. With the REF out

put and an external transistor, a sim ple, inexpensive regulator can be built to provide V

number of cells.

Internal registers include available

charge, temperature, capacity, battery

ID, battery status, and programming

across a greater

pin settings. To support subassembly testing, the outputs may also be con

trolled. The external processor may

also overwrite some of the bq2010 gas gauge data registers.

Pin Connections

SEG1/PROG

SEG2/PROG

SEG3/PROG

SEG4/PROG

SEG5/PROG

SEG6/PROG

4/95 D

LCOM

16-Pin Narrow SOIC

PN201001.eps

REF

EMPTY

DISP

Pin Names

LCOM LED common output

SEG

/PROG1LED segment 1/

SEG

/PROG2LED segment 2/

SEG

/PROG3LED segment 3/

SEG

/PROG4LED segment 4/

SEG

/PROG5LED segment 5/

SEG

/PROG6LED segment 6/

program 1 input

program 2 input

program 3 input

program 4 input

program 5 input

program 6 input

REF Voltage reference output

NC No connect

DQ Serial communications

input/output

EMPTY Empty battery indicator

output

SB Battery sense input

DISP

Display control input

SR Sense resistor input

3.0–6.5V

System ground

bq2010

Pin Descriptions

LCOM

SEG SEG

PROG PROG

PROG

LED common output

Open-drain output switches V current for the LEDs. The switch is off dur ing initialization to allow reading of the soft pull-up or pull-down program resistors. LCOM is also high impedance when the dis play is off.

LED display segment outputs (dual func

–

tion with PROG

Each output may activate an LED to sink the current sourced from LCOM.

Programmed full count selection inputs

–

(dual function with SEG

These three-level input pins define the pro grammed full count (PFC) thresholds de scribed in Table 2.

Gas gauge rate selection inputs (dual

–

function with SEG

These three-level input pins define the scale factor described in Table 2.

Self-discharge rate selection (dual func-

tion with SEG

This three-level input pin defines the selfdischarge compensation rate shown in Table 1.

Display mode selection (dual function

with SEG

)

This three-level pin defines the display op eration shown in Table 1.

No connect

–PROG6)

)

–SEG4)

–SEG2)

to source

DISP

EMPTY

REF

Sense resistor input

The voltage drop (V sistor R time to interpret charge and discharge activ

is monitored and integrated over

) across the sense re

ity. The SR input is tied to the high side of the sense resistor. V charge, and V effective voltage drop, V bq2010 is V

SR+VOS

SR>VSS

SR<VSS

indicates charge. The

(see Table 5).

indicates dis

, as seen by the

SRO

Display control input

high disables the LED display. DISP

DISP tied to VCCallows PROGXto connect directly to V

or VSSinstead of through a pull-up or

pull-down resistor. DISP

floating allows the LED display to be active during discharge or charge if the NAC registers update at a rate equivalent to |V vates the display. See Table 1.

|≥4mV. DISP low acti

SRO

Secondary battery input

This input monitors the single-cell voltage potential through a high-impedance resistive divider network for end-of-discharge voltage (EDV) thresholds, maximum charge voltage (MCV), and battery removed.

Battery empty output

This open-drain output becomes high-impedance on detection of a valid end-of-discharge voltage (V

) and is low following the next application

EDVF

of a valid charge.

Serial I/O pin

This is an open-drain bidirectional pin.

Voltage reference output for regulator

REF provides a voltage reference output for an optional micro-regulator.

Supply voltage input

Ground

bq2010

Functional Description

General Operation

The bq2010 determines battery capacity by monitoring the amount of charge input to or removed from a re chargeable battery. The bq2010 measures discharge and charge currents, estimates self-discharge, monitors the battery for low-battery voltage thresholds, and compen sates for temperature and charge/discharge rates. The charge measurement derives from monitoring the voltage across a small-value series sense resistor between the negative battery terminal and ground. The available bat tery charge is determined by monitoring this voltage over time and correcting the measurement for the environ mental and operating conditions.

bq2010

Gas Gauge IC

LCOM

SEG1/PROG

SEG2/PROG

SEG3/PROG

SEG4/PROG

SEG5/PROG

SEG6/PROG

REF

DISP

EMPTY

Figure 1 shows a typical battery pack application of the bq2010 using the LED display capability as a chargestate indicator. The bq2010 can be configured to display capacity in either a relative or an absolute display mode. The relative display mode uses the last measured dis charge capacity of the battery as the battery “full” refer

ence. The absolute display mode uses the programmed full count (PFC) as the full reference, forcing each seg ment of the display to represent a fixed amount of

charge. A push-button display feature is available for momentarily enabling the LED display.

The bq2010 monitors the charge and discharge currents as a voltage across a sense resistor (see R

A filter between the negative battery terminal and the SR pin may be required if the rate of change of the bat

in Figure 1).

tery current is too great.

Q1 ZVNL110A

0.1 F

Indicates optional.

Directly connect to VCC across 3 or 4 cells (3 to 5.6V nominal)

Charger

Load with a resistor and a Zener diode to limit voltage during charge. Otherwise, R1, C1, and Q1 are needed for regulation of >4 cells. The value of R1 depends on the number of cells.

Programming resistors (6 max.) and ESD-protection diodes are not shown.

R-C on SR ma

be required, application-specific.

FG201001.eps

Figure 1. Battery Pack Application Diagram—LED Display

bq2010

Voltage Thresholds

In conjunction with monitoring VSRfor charge/discharge currents, the bq2010 monitors the single-cell battery potential through the SB pin. The single-cell voltage potential is determined through a resistor/divider net work according to the following equation:

where N is the number of cells, RB positive battery terminal, and RB negative battery terminal. The single-cell battery volt

1=−

is connected to the

age is monitored for the end-of-discharge voltage (EDV) and for maximum cell voltage (MCV). EDV threshold levels are used to determine when the battery has reached an “empty” state, and the MCV threshold is used for fault detection during charging.

Two EDV thresholds for the bq2010 are fixed at:

(early warning) = 1.05V

EDV1

(empty) = 0.95V

EDVF

If V

is below either of the two EDV thresholds, the as-

sociated flag is latched and remains latched, independent of V monitoring may be disabled under certain conditions as

, until the next valid charge. EDV

described in the next paragraph.

During discharge and charge, the bq2010 monitors V for various thresholds. These thresholds are used to

compensate the charge and discharge rates. Refer to the count compensation section for details. EDV monitoring is disabled if V after V

> -250mV.

-250mV typical and resumes

≤

second

EMPTY Output

The EMPTY output switches to high impedance when V

SB<VEDVF

occurs. The bq2010 also monitors V

2.25V. V

and remains latched until a valid charge

relative to V

falling from above V

resets the device.

MCV

Reset

The bq2010 recognizes a valid battery whenever VSBis greater than 0.1V typical. V or falling from above 2.25V resets the device. Reset can

rising from below 0.25V

also be accomplished with a command over the serial port as described in the Reset Register section.

Temperature

The bq2010 internally determines the temperature in 10°C steps centered from -35°C to +85°C. The tempera ture steps are used to adapt charge and discharge rate compensations, self-discharge counting, and available

charge display translation. The temperature range is available over the serial port in 10°C increments as shown below:

TMPGG (hex) Temperature Range

0x < -30°C

1x -30°C to -20°C

2x -20°C to -10°C

3x -10°C to 0°C

4x 0°C to 10°C

5x 10°C to 20°C

6x 20°C to 30°C

7x 30°C to 40°C

8x 40°C to 50°C

9x 50°C to 60°C

Ax 60°C to 70°C

Bx 70°C to 80°C

Cx > 80°C

Layout Considerations

The bq2010 measures the voltage differential between the SR and V

pin) is greatly affected by PC board layout. For optimal results, the PC board layout should follow the strict rule of a single-point ground return. Sharing high-current ground with small signal ground causes undesirable noise on the small signal nodes. Additionally:

The capacitors (SB and VCC) should be placed as close as possible to the SB and V and their paths to V A high-quality ceramic capacitor of 0.1µf is recommended for V

The sense resistor capacitor should be placed as close as possible to the SR pin.

The sense resistor (R possible to the bq2010.

pins. VOS(the offset voltage at the SR

pins, respectively,

should be as short as possible.

) should be as close as

SNS

Gas Gauge Operation

The operational overview diagram in Figure 2 illustrates the operation of the bq2010. The bq2010 accumulates a measure of charge and discharge currents, as well as an estimation of self-discharge. Charge and discharge cur rents are temperature and rate compensated, whereas self-discharge is only temperature compensated.

The main counter, Nominal Available Charge (NAC), represents the available battery capacity at any given time. Battery charging increments the NAC register, while battery discharging and self-discharge decrement the NAC register and increment the DCR (Discharge Count Register).

The Discharge Count Register (DCR) is used to update the Last Measured Discharge (LMD) register only if a complete battery discharge from full to empty occurs without any partial battery charges. Therefore, the bq2010 adapts its capacity determination based on the actual conditions of discharge.

The battery's initial capacity is equal to the Programmed Full Count (PFC) shown in Table 2. Until LMD is updated, NAC counts up to but not beyond this threshold during subsequent charges. This approach allows the gas gauge to be charger-independent and compatible with any type of charge regime.

bq2010

Last Measured Discharge (LMD) or learned

battery capacity:

LMD is the last measured discharge capacity of the battery. On initialization (application of V

tery replacement), LMD = PFC. During subsequent discharges, the LMD is updated with the latest measured capacity in the Discharge Count Register (DCR) representing a discharge from full to below EDV1. A qualified discharge is necessary for a ca pacity transfer from the DCR to the LMD register. The LMD also serves as the 100% reference thresh old used by the relative display mode.

Programmed Full Count (PFC) or initial bat

tery capacity:

The initial LMD and gas gauge rate values are pro grammed by using PROG provides the 100% reference for the absolute dis

–PROG4. The PFC also

play mode. The bq2010 is configured for a given ap plication by selecting a PFC value from Table 2. The correct PFC may be determined by multiplying the rated battery capacity in mAh by the sense re sistor value:

Battery capacity (mAh)*sense resistor (Ω) =

PFC (mVh)

Selecting a PFC slightly less than the rated capacity for absolute mode provides capacity above the full reference for much of the battery's life.

or bat

Inputs

Main Counters

and Capacity

Reference (LMD)

Outputs

Charge Current

Rate and

Temperature

Compensation

Chip-Controlled

Available Charge

Nominal

Available

Charge

(NAC)

Temperature

Translation

LED Display

Discharge

Current

Rate and

Temperature

Compensation

Discharged

Last

Measured

(LMD)

Serial

Port

Qualified Transfer

Temperature Step, Other Data

Figure 2. Operational Overview

Self-Discharge

Timer

Temperature

Compensation

Discharge

Count

(DCR)

FG201002.eps

bq2010

Example: Selecting a PFC Value

Given:

Sense resistor = 0.1

Ω

Number of cells = 6 Capacity = 2200mAh, NiCd battery Current range = 50mA to 2A Absolute display mode Serial port only Self-discharge = Voltage drop over sense resistor = 5mV to 200mV

Therefore:

2200mAh*0.1Ω= 220mVh

Table 1. bq2010 Programming

Connection

H Disabled

Note: PROG5and PROG6states are independent.

PROG

NAC

Self-Discharge Rate

PROG

Display Mode

Absolute

NAC = PFC on reset

Absolute

NAC = 0 on reset

Relative

NAC = 0 on reset

Table 2. bq2010 Programmed Full Count mVh Selections

Select:

PFC = 33792 counts or 211mVh PROG

= float

PROG

= float

PROG

= float

PROG

= low

PROG

= float

PROG

= float

The initial full battery capacity is 211mVh (2110mAh) until the bq2010 “learns” a new capac ity with a qualified discharge from full to EDV1.

DISP

Display State

LED disabled

LED-enabled on discharge or charge

when equivalent |V

SRO

|≥4mV

LED on

Pro-

grammed

PROG

1 2 PROG3 = H PROG3 = Z PROG3 = L PROG3 = H PROG3 = Z PROG3 = L

-- -

Full

Count

(PFC)

Scale =

1/80

PROG

= L PROG4= Z

Scale =

1/160

Scale =

1/320

Scale =

1/640

Scale =

1/1280

Scale =

1/2560

Units

mVh/ count

H H 49152 614 307 154 76.8 38.4 19.2 mVh

H Z 45056 563 282 141 70.4 35.2 17.6 mVh

H L 40960 512 256 128 64.0 32.0 16.0 mVh

Z H 36864 461 230 115 57.6 28.8 14.4 mVh

Z Z 33792 422 211 106 53.0 26.4 13.2 mVh

Z L 30720 384 192 96.0 48.0 24.0 12.0 mVh

L H 27648 346 173 86.4 43.2 21.6 10.8 mVh

L Z 25600 320 160 80.0 40.0 20.0 10.0 mVh

L L 22528 282 141 70.4 35.2 17.6 8.8 mVh

VSR equivalent to 2

counts/sec. (nom.)

90 45 22.5 11.25 5.6 2.8 mV

bq2010

3. Nominal Available Charge (NAC):

NAC counts up during charge to a maximum value of LMD and down during discharge and self-discharge to 0. NAC is reset to 0 on initializa tion (PROG following discharge to EDV1. NAC is set to PFC on initialization if PROG statement of charge during periods of overcharge,

= Z or low) and on the first valid charge

= high. To prevent over

NAC stops incrementing when NAC = LMD.

4. Discharge Count Register (DCR):

The DCR counts up during discharge independent of NAC and could continue increasing after NAC has decremented to 0. Prior to NAC = 0 (empty battery), both discharge and self-discharge in crement the DCR. After NAC = 0, only discharge increments the DCR. The DCR resets to 0 when NAC = LMD. The DCR does not roll over but stops counting when it reaches ffffh.

The DCR value becomes the new LMD value on the first charge after a valid discharge to V

EDV1

if:

No valid charge initiations (charges greater than 256 NAC counts, where V during the period between NAC = LMD and EDV1

SRO>VSRQ

) occurred

detected.

The self-discharge count is not more than 4096 counts (8% to 18% of PFC, specific percentage threshold determined by PFC).

The temperature is≥0°C when the EDV1 level is reached during discharge.

The valid discharge flag (VDQ) indicates whether the present discharge is valid for LMD update.

Charge Counting

Charge activity is detected based on a positive voltage on the V increments NAC at a rate proportional to V abled, activates an LED display if the rate is equivalent to V compensation for charge rate and temperature.

The bq2010 determines charge activity sustained at a continuous rate equivalent to V charge equates to sustained charge activity greater than 256 NAC counts. Once a valid charge is detected, charge counting continues until V V the Digital Magnitude Filter section. The default value for V

input. If charge activity is detected, the bq2010

> 4mV. Charge actions increment the NAC after

SRO

SRQ.VSRQ

is 375µV.

SRQ

is a programmable threshold as described in

SRO(VSR+VOS

SRO

SRO>VSRQ

) falls below

and, if en

. A valid

Discharge Counting

All discharge counts where V register to decrement and the DCR to increment. Ex

ceeding the fast discharge threshold (FDQ) if the rate is equivalent to V abled. The display becomes inactive after V

above -4mV. V described in the Digital Magnitude Filter section. The default value for V

< -4mV activates the display, if en

SRO

is a programmable threshold as

SRD

SRO<VSRD

is -300µV.

cause the NAC

Self-Discharge Estimation

The bq2010 continuously decrements NAC and incre ments DCR for self-discharge based on time and tempera ture. The self-discharge count rate is programmed to be a

nominal

lected by PROG temperature is between 20°–30°C. The NAC register can

NAC,

NAC per day, or disabled as se

. This is the rate for a battery whose

not be decremented below 0.

Count Compensations

The bq2010 determines fast charge when the NAC updates at a rate of≥2 counts/sec. Charge and discharge activity is compensated for temperature and charge/discharge rate before updating the NAC and/or DCR. Selfdischarge estimation is compensated for temperature before updating the NAC or DCR.

Charge Compensation

Two charge efficiency compensation factors are used for trickle charge and fast charge. Fast charge is defined as a rate of charge resulting in≥2 NAC counts/sec (≥0.15C to 0.32C depending on PFC selections; see Table 2). The compensation defaults to the fast charge factor until the actual charge rate is determined.

Temperature adapts the charge rate compensation factors over three ranges between nominal, warm, and hot tem peratures. The compensation factors are shown below.

Charge

Temperature

<30°C 0.80 0.95

30–40°C 0.75 0.90

> 40°C 0.65 0.80

Discharge Compensation

Corrections for the rate of discharge are made by adjust ing an internal discharge compensation factor. The dis charge compensation factor is based on the namically measured V

Trickle Charge Compensation

Fast Charge

Compensation

SRO

rises

bq2010

The compensation factors during discharge are:

Discharge

Approximate

Threshold

> -150 mV 1.00 100%

< -150 mV 1.05 95%

Compensation

Factor Efficiency

Temperature compensation during discharge also takes place. At lower temperatures, the compensation factor in creases by 0.05 for each 10°C temperature step below 10°C.

Comp. factor = 1.0 + (0.05*N)

Where N = Number of 10°C steps below 10°C and

-150mV < V

<0.

For example:

T > 10°C : Nominal compensation,N = 0

0°C<T<10°C:N = 1 (i.e., 1.0 becomes 1.05)

-10°C<T<0°C:N=2(i.e., 1.0 becomes 1.10)

-20°C<T<-10°C: N = 3 (i.e., 1.0 becomes 1.15)

-20°C<T<-30°C: N = 4 (i.e., 1.0 becomes 1.20)

Self-Discharge Compensation

The self-discharge compensation is programmed for a nominal rate of the rate for a battery within the 20–30°C temperature range (TMPGG = 6x). This rate varies across 8 ranges from <10°C to >70°C, doubling with each higher temperature step (10°C). See Table 3.

NAC,

NAC per day, or disabled. This is

Table 3. Self-Discharge Compensation

Temperature

Range

< 10°C

10–20°C

20–30°C

30–40°C

40–50°C

50–60°C

60–70°C

> 70°C

PROG

Typical Rate

= Z PROG5= L

NAC

256

NAC

128

NAC

188

23.5

11.8

5.88

2.94

1.47

Digital Magnitude Filter

The bq2010 has a programmable digital filter to elimi nate charge and discharge counting below a set thresh old. The default setting is -0.30mV for V +0.38mV for V be calculated using the following equation. Table 4

. The proper digital filter setting can

SRQ

shows typical digital filter settings.

(mV) = -45 / DMF

SRD

(mV) = -1.25*V

SRQ

Table 4. Typical Digital Filter Settings

DMF

Hex.

SRD

(mV)

SRD

V (mV)

75 4B -0.60 0.75

100 64 -0.45 0.56

150 (default) 96 -0.30 0.38

175 AF -0.26 0.32 200 C8 -0.23 0.28

Error Summary

Capacity Inaccurate

The LMD is susceptible to error on initialization or if no updates occur. On initialization, the LMD value includes the error between the programmed full capacity and the actual capacity. This error is present until a valid discharge occurs and LMD is updated (see the DCR description on page 7). The other cause of LMD error is battery wear-out. As the battery ages, the measured capacity must be adjusted to account for changes in actual battery capacity.

A Capacity Inaccurate counter (CPI) is maintained and incremented each time a valid charge occurs (qualified by NAC; see the CPI register description) and is reset whenever LMD is updated from the DCR. The counter does not wrap around but stops counting at 255. The ca pacity inaccurate flag (CI) is set if LMD has not been updated following 64 valid charges.

Current-Sensing Error

Table 5 illustrates the current-sensing error as a func tion of V charge counts to the NAC register when V V

. A digital filter eliminates charge and dis

) is between V

SRQ

and V

SRD

SRO(VSR

Communicating With the bq2010

The bq2010 includes a simple single-pin (DQ plus re turn) serial data interface. A host processor uses the in terface to access various bq2010 registers. Battery char acteristics may be easily monitored by adding a single contact to the battery pack. The open-drain DQ pin on

SRD

SRQ

and

Table 5. bq2010 Current-Sensing Errors

Symbol Parameter Typical Maximum Units Notes

INL

INR

Offset referred to V

Integrated non-linearity error

Integrated nonrepeatability error

150

V DISP

=VCC.

Add 0.1% per °C above or below 25°C and 1% per volt above or below 4.25V.

Measurement repeatability given similar operating conditions.

bq2010

the bq2010 should be pulled up by the host system or may be left floating if the serial interface is not used.

The interface uses a command-based protocol, where the host processor sends a command byte to the bq2010. The command directs the bq2010 either to store the next eight bits of data received to a register specified by the command byte or to output the eight bits of data speci fied by the command byte.

The communication protocol is asynchronous return-toone. Command and data bytes consist of a stream of eight bits that have a maximum transmission rate of 333 bits/sec. The least-significant bit of a command or data byte is transmitted first. The protocol is simple enough that it can be implemented by most host processors using either polled or interrupt processing. Data input from the bq2010 may be sampled using the pulse-width capture timers available on some microcontrollers.

Communication is normally initiated by the host processor sending a BREAK command to the bq2010. A BREAK is detected when the DQ pin is driven to a logic-low state for a time, t to its normal ready-high logic state for a time, t bq2010 is now ready to receive a command from the host

or greater. The DQ pin should then be returned

. The

processor.

The return-to-one data bit frame consists of three distinct sections. The first section is used to start the transmission by either the host or the bq2010 taking the DQ pin to a logic-low state for a period, t actual data transmission, where the data should be valid by a period, t

, after the negative edge used to start

DSU

. The next section is the

STRH,B

communication. The data should be held for a period,

, to allow the host or bq2010 to sample the data bit.

The final section is used to stop the transmission by re turning the DQ pin to a logic-high state by at least a peri od, t

, after the negative edge used to start communica

SSU

tion. The final logic-high state should be held until a peri od, t

, to allow time to ensure that the bit transmission

was stopped properly. The timings for data and break communication are given in the serial communication tim ing specification and illustration sections.

Communication with the bq2010 is always performed with the least-significant bit being transmitted first. Figure 3 shows an example of a communication sequence to read the bq2010 NAC register.

bq2010 Registers

The bq2010 command and status registers are listed in Table 6 and described below.

Command Register (CMDR)

The write-only CMDR register is accessed when eight valid command bits have been received by the bq2010. The CMDR register contains two fields:

W/R bit

Command address

The W/R whether the received command is for a read or a write function.

bit of the command register is used to select

Written by Host to bq2010

CMDR = 03h

LSB MSB LSB MSB

Break 0 0 0 0 0 0 1 0 1 0 0 1

1110

Received by Host to bq2010

NAC = 65h

TD201001.eps

Figure 3. Typical Communication with the bq2010

bq2010

Symbol

CMDR

FLGS1

TMPGG

NACH

NACL

BATID

LMD

FLGS2

PPD

PPU

CPI

DMF

RST Reset register

Command reg ister

Primary status flags register

Temperature and gas gauge register

Nominal avail able charge high byte reg ister

Nominal available charge low byte register

Battery identification register

Last measured discharge register

Secondary status flags register

Program pin pull-down reg ister

Program pin pull-up regis ter

Capacity inaccurate count register

Digital magni tude filter reg ister

Table 6. bq2010 Command and Status Registers

Control Field

(hex)

Read/

Write

7(MSB) 6543210(LSB)

00h Write W/R

01h Read CHGS BRP BRM CI VDQ n/u EDV1 EDVF

02h Read TMP3 TMP2 TMP1 TMP0 GG3 GG2 GG1 GG0

03h R/W NACH7 NACH6 NACH5 NACH4 NACH3 NACH2 NACH1 NACH0

17h Read NACL7 NACL6 NACL5 NACL4 NACL3 NACL2 NACL1 NACL0

04h R/W BATID7 BATID6 BATID5 BATID4 BATID3 BATID2 BATID1 BATID0

05h R/W LMD7 LMD6 LMD5 LMD4 LMD3 LMD2 LMD1 LMD0

06h Read CR DR2 DR1 DR0 n/u n/u n/u OVLD

07h Read n/u n/u PPD6 PPD5 PPD4 PPD3 PPD2 PPD1

08h Read n/u n/u PPU6 PPU5 PPU4 PPU3 PPU2 PPU1

09h Read CPI7 CPI6 CPI5 CPI4 CPI3 CPI2 CPI1 CPI0

0ah R/W DMF7 DMF6 DMF5 DMF4 DMF3 DMF2 DMF1 DMF0

39h Write RST 0000000

AD6 AD5 AD4 AD3 AD2 AD1 AD0

Note: n/u = not used

bq2010

The W/R values are:

CMDR Bits

76543 2 1 0

W/R

Where W/R

- -- - - - -

is:

0 The bq2010 outputs the requested register

contents specified by the address portion of CMDR.

1 The following eight bits should be written

to the register specified by the address por

tion of CMDR.

The lower seven-bit field of CMDR contains the address portion of the register to be accessed. Attempts to write to invalid addresses are ignored.

CMDR Bits

765 4 3 2 1 0

- AD6 AD5 AD4 AD3 AD2 AD1

AD0

(LSB)

Primary Status Flags Register (FLGS1)

The read-only FLGS1 register (address=01h) contains the primary bq2010 flags.

The charge status flag (CHGS) is asserted when a valid charge rate is detected. Charge rate is deemed valid when V discharge activity clears CHGS.

SRO>VSRQ

The CHGS values are:

76543 2 1 0

CHGS - -- - - - -

.AV

SRO

FLGS1 Bits

of less than V

SRQ

tected after the EDV1 flag is asserted. BRP = 1 signifies that the device has been reset.

The BRP values are:

FLGS1 Bits

76543 2 1 0

- BRP - - - - - -

Where BRP is:

0 Battery is charged until NAC = LMD or dis

charged until the EDV1 flag is asserted

dropping from above MCV, VSBrising

from below 0.1V, or a serial port initiated reset has occurred

The battery removed flag (BRM) is asserted whenever the potential on the SB pin (relative to V MCV or falls below 0.1V. The BRM flag is asserted until

) rises above

the condition causing BRM is removed.

The BRM values are:

FLGS1 Bits

76543 2 1 0

- - BRM - - - - -

Where BRM is:

0 0.1V < V

1 0.1 V > V

< 2.25V

or VSB> 2.25V

The capacity inaccurate flag (CI) is used to warn the user that the battery has been charged a substantial number of times since LMD has been updated. The CI flag is asserted on the 64th charge after the last LMD update or when the bq2010 is reset. The flag is cleared after an LMD update.

The CI values are:

Where CHGS is:

0 Either discharge activity detected or V

SRQ

SRO

> V

SRQ

SRO

The battery replaced flag (BRP) is asserted whenever the potential on the SB pin (relative to V from above the maximum cell voltage, MCV (2.25V), or

), VSB, falls

rises above 0.1V. The BRP flag is also set when the bq2010 is reset (see the RST register description). BRP is reset when either a valid charge action increments NAC to be equal to LMD, or a valid charge action is de

FLGS1 Bits

76543 2 1 0

---CI- - - -

Where CI is:

0 When LMD is updated with a valid full dis

charge

1 After the 64th valid charge action with no

LMD updates or the bq2010 is reset

bq2010

The valid discharge flag (VDQ) is asserted when the bq2010 is discharged from NAC=LMD. The flag remains set until either LMD is updated or one of three actions that can clear VDQ occurs:

The self-discharge count register (SDCR) has exceeded the maximum acceptable value (4096 counts) for an LMD update.

A valid charge action sustained at V least 256 NAC counts.

The EDV1 flag was set at a temperature below 0°C

SRO

> V

SRQ

for at

The VDQ values are:

FLGS1 Bits

76543 2 1 0

- - - - VDQ - - -

Where VDQ is:

0 SDCR≥4096, subsequent valid charge ac

tion detected, or EDV1 is asserted with the temperature less than 0°C

1 On first discharge after NAC = LMD

The first end-of-discharge warning flag (EDV1) warns the user that the battery is almost empty. The first segment pin, SEG the display is enabled once EDV1 is asserted, which

, is modulated at a 4Hz rate if

should warn the user that loss of battery power is imminent. The EDV1 flag is latched until a valid charge has been detected.

The EDV1 values are:

FLGS1 Bits

765 4 3 2 1 0

- - - - - - EDV1 -

Where EDV1 is:

0 Valid charge action detected, V

< 1.05V providing that OVLD=0 (see

FLGS2 register description)

≥

1.05V

The final end-of-discharge warning flag (EDVF) is used to warn that battery power is at a failure condition. All segment drivers are turned off. The EDVF flag is latched until a valid charge has been detected. The EMPTY pin is also forced to a high-impedance state on assertion of EDVF. The host system may pull EMPTY high, which may be used to disable circuitry to prevent deep-discharge of the battery.

The EDVF values are:

FLGS1 Bits

765 4 3 2 1 0

---- - - -EDVF

Where EDVF is:

0 Valid charge action detected, V

< 0.95V providing that OVLD=0 (see

FLGS2 register description)

≥

0.95V

Temperature and Gas Gauge Register (TMPGG)

The read-only TMPGG register (address=02h) contains two data fields. The first field contains the battery tem perature. The second field contains the available charge from the battery.

TMPGG Temperature Bits

7 6 5 4 3210

TMP3 TMP2 TMP1 TMP0 - - -

The bq2010 contains an internal temperature sensor. The temperature is used to set charge and discharge efficiency factors as well as to adjust the self-discharge coefficient.

The temperature register contents may be translated as shown below.

TMP3 TMP2 TMP1 TMP0 Temperature

0000 T < -30°C

0001-30°C < T < -20°C

0010-20°C < T < -10°C

0011-10°C < T < 0°C

01000°C < T < 10°C

010110°C < T < 20°C

011020°C < T < 30°C

011130°C < T < 40°C

100040°C < T < 50°C

100150°C < T < 60°C

101060°C < T < 70°C

101170°C < T < 80°C

1100 T > 80°C

bq2010

The bq2010 calculates the available charge as a function of NAC, temperature, and a full reference, either LMD or PFC. The results of the calculation are available via the display port or the gas gauge field of the TMPGG register. The register is used to give available capacity

increments from 0 to

TMPGG Gas Gauge Bits

765 4 3 2 1 0

- - - - GG3 GG2 GG1 GG0

The gas gauge display and the gas gauge portion of the TMPGG register are adjusted for cold temperature de pendencies. A piece-wise correction is performed as fol lows:

Temperature Available Capacity Calculation

> 0°C NAC / “Full Reference”

-20°C < T < 0°C 0.75*NAC / “Full Reference” < -20°C 0.5*NAC / “Full Reference”

The adjustment between > 0°C and -20°C < T < 0°C has a 10°C hysteresis.

Nominal Available Charge Registers (NACH/NACL)

The read/write NACH high-byte register (address=03h) and the read-only NACL low-byte register (address=17h) are the main gas gauging register for the bq2010. The NAC registers are incremented during charge actions and decremented during discharge and self-discharge actions. The correction factors for charge/discharge effi ciency are applied automatically to NAC.

On reset, if PROG cleared to 0; if PROG = 0. When the bq2010 detects a valid charge, NACL resets

= Z or low, NACH and NACL are

= high, NACH = PFC and NACL

to 0. Writing to the NAC registers affects the available

charge counts and, therefore, affects the bq2010 gas gauge operation. Do not write the NAC registers to a value greater than LMD.

Battery Identification Register (BATID)

The read/write BATID register (address=04h) is avail able for use by the system to determine the type of bat tery pack. The BATID contents are retained as long as

is greater than 2V. The contents of BATID have no

effect on the operation of the bq2010. There is no de fault setting for this register.

Last Measured Discharge Register (LMD)

LMD is a read/write register (address=05h) that the bq2010 uses as a measured full reference. The bq2010 adjusts LMD based on the measured discharge capacity

of the battery from full to empty. In this way the bq2010 updates the capacity of the battery. LMD is set to PFC during a bq2010 reset.

Secondary Status Flags Register (FLGS2)

The read-only FLGS2 register (address=06h) contains the secondary bq2010 flags.

The charge rate flag (CR) is used to denote the fast charge regime. Fast charge is assumed whenever a charge action is initiated. The CR flag remains asserted if the charge rate does not fall below 2 counts/sec.

The CR values are:

76543 2 1 0

CR - - - - - - -

Where CR is:

0 When charge rate falls below 2 counts/sec

1 When charge rate is above 2 counts/sec

The fast charge regime efficiency factors are used when CR = 1. When CR = 0, the trickle charge efficiency factors are used. The time to change CR varies due to the user-selectable count rates.

The discharge rate flags, DR2–0, are bits 6–4.

7 6 5 4 3210

- DR2 DR1 DR0 - - -

They are used to determine the current discharge re gime as follows:

DR2 DR1 DR0 VSR(V)

000 V 001 V

The overload flag (OVLD) is asserted when a discharge overload is detected, V serted as long as the condition persists and is cleared

0.5 seconds after V

is used to stop sampling of the battery terminal character

istics for end-of-discharge determination. Sampling is reenabled 0.5 secs after the overload condition is removed.

76543 2 1 0

- - - - - - - OVLD

FLGS2 Bits

> -150mV

< -150mV

< -250mV. OVLD remains as

> -250mV. The overload condition

FLGS2 Bits

bq2010

DR2–0 and OVLD are set based on the measurement of the voltage at the SR pin relative to V this measurement is made varies with device activity.

. The rate at which

Program Pin Pull-Down Register (PPD)

The read-only PPD register (address=07h) contains some of the programming pin information for the bq2010. The segment drivers, SEG sponding PPD register location, PPD tion is set if a pull-down resistor has been detected on

, have a corre

1–6

. A given loca

1–6

its corresponding segment driver. For example, if SEG and SEG4have pull-down resistors, the contents of PPD are xx001001.

PPD/PPU Bits

76543210

- - PPU

PPU5PPU4PPU3PPU2PPU

- - PPD6PPD5PPD4PPD3PPD2PPD

Program Pin Pull-Up Register (PPU)

The read-only PPU register (address=08h) contains the rest of the programming pin information for the bq2010. The segment drivers, SEG register location, PPU up resistor has been detected on its corresponding segment driver. For example, if SEG tors, the contents of PPU are xx100100.

, have a corresponding PPU

1–6

. A given location is set if a pull-

1–6

and SEG6have pull-up resis-

Capacity Inaccurate Count Register (CPI)

The read-only CPI register (address=09h) is used to indi cate the number of times a battery has been charged with out an LMD update. Because the capacity of a recharge able battery varies with age and operating conditions, the bq2010 adapts to the changing capacity over time. A com plete discharge from full (NAC=LMD) to empty (EDV1=1) is required to perform an LMD update assuming there have been no intervening valid charges, the temperature is greater than or equal to 0°C, and the self-discharge coun ter is less than 4096 counts.

The CPI register is incremented every time a valid charge is detected. When NAC > 0.94*LMD, however, the CPI register increments on the first valid charge; CPI does not increment again for a valid charge until NAC < 0.94*LMD. This prevents continuous trickle charging from incrementing CPI if self-discharge decre ments NAC. The CPI register increments to 255 with out rolling over. When the contents of CPI are incre mented to 64, the capacity inaccurate flag, CI, is as serted in the FLGS1 register. The CPI register is reset whenever an update of the LMD register is performed, and the CI flag is also cleared.

Digital Magnitude Filter (DMF)

The read-write DMF register (address = 0ah) provides the system with a means to change the default settings of the digital magnitude filter. By writing different val ues into this register, the limits of V adjusted.

Note: Care should be taken when writing to this regis

ter. A V

versely affect the accuracy of the bq2010. Refer to Table

4 for recommended settings for the DMF register.

SRD

and V

below the specified VOSmay ad

SRQ

SRD

and V

Reset Register (RST)

The reset register (address=39h) provides the means to perform a software-controlled reset of the device. By writing the RST register contents from 00h to 80h, a bq2010 reset is performed. Setting any bit other than the

most-significant bit of the RST register is not allowed,

and results in improper operation of the bq2010.

Resetting the bq2010 sets the following:

LMD = PFC

CPI, VDQ, NACH, and NACL = 0

CI and BRP = 1

Note: NACH = PFC when PROG disabled when PROG

= H. Self-discharge is

Display

The bq2010 can directly display capacity information using low-power LEDs. If LEDs are used, the program pins should be resistively tied to V

gram high or program low, respectively.

The bq2010 displays the battery charge state in either

absolute or relative mode. In relative mode, the battery

charge is represented as a percentage of the LMD. Each

LED segment represents 20% of the LMD. The sixth segment, SEG

In absolute mode, each segment represents a fixed

, is not used.

amount of charge, based on the initial PFC. In absolute mode, each segment represents 20% of the PFC, with SEG

representing “overfull” (charge above the PFC).

As the battery wears out over time, it is possible for the LMD to be below the initial PFC. In this case, all of the LEDs may not turn on in absolute mode, representing the reduction in the actual battery capacity.

The capacity display is also adjusted for the present bat

tery temperature. The temperature adjustment reflects

the available capacity at a given temperature but does not affect the NAC register. The temperature adjustments are detailed in the TMPGG register description.

When DISP When DISP

is tied to VCC, the SEG

is left floating, the display becomes active

or VSSfor a pro

outputs are inactive.

1–6

SRQ

can be

bq2010

whenever the NAC registers are counting at a rate equiva lent to |V puts become active immediately. A capacitor tied to DISP

|≥4mV. When pulled low, the segment out

SRO

allows the display to remain active for a short period of

SEG

blinks at a 4Hz rate whenever VSBhas been de

tected to be below V battery condition. V the display output.

(EDV1 = 1), indicating a low-

EDV1

below V

(EDVF = 1) disables

EDVF

time after activation by a push-button switch.

The segment outputs are modulated as two banks of three, with segments 1, 3, and 5 alternating with seg ments 2, 4, and 6. The segment outputs are modulated at approximately 100Hz with each segment bank active for 30% of the period.

Microregulator

The bq2010 can operate directly from 3 or 4 cells. To fa

cilitate the power supply requirements of the bq2010, an REF output is provided to regulate an external lowthreshold n-FET. A micropower source for the bq2010 can be inexpensively built using the FET and an exter nal resistor; see Figure 1.

Absolute Maximum Ratings

Symbol Parameter Minimum Maximum Unit Notes

All other pins Relative to V

REF Relative to V

OPR

Note: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation

Relative to V

-0.3 +7.0 V

-0.3 +8.5 V

Current limited by R1 (see Figure 1)

Minimum 100Ωseries resistor should

Relative to V

-0.3 +7.0 V

be used to protect SR in case of a shorted battery (see the bq2010 application note for details).

Operating temperature

0 +70 °C

-40 +85 °C

Commercial

Industrial

should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to conditions beyond the operational limits for extended periods of time may affect device reliability.

DC Voltage Thresholds (T

= T

; V = 3.0 to 6.5V)

OPR

Symbol Parameter Minimum Typical Maximum Unit Notes

EDVF

EDV1

SR1

SRO

SRQ

SRD

MCV

Final empty warning

First empty warning

Discharge compensation threshold

SR sense range

Valid charge

Valid discharge

Maximum single-cell voltage

Battery removed/replaced

0.93 0.95 0.97 V

1.03 1.05 1.07 V

-120 -150 -180 mV

-300 - +2000 mV

375 - -

- - -300

2.20 2.25 2.30 V

- 0.1 0.25 V

2.20 2.25 2.30 V

SR, VSR+ V

VVSR+ VOS(see note)

SB pulled low

SB pulled high

Note: Default value; value set in DMF register. VOSis affected by PC board layout. Proper layout guidelines

should be followed for optimal performance. See “LayoutConsiderations.”

bq2010

DC Electrical Characteristics (T

= T

)

OPR

Symbol Parameter Minimum Typical Maximum Unit Notes

excursion from < 2.0V to

REF

SBmax

DISP

LCOM

OLSL

OLSH

OHLCL

OHLCH

OHLCOM

OLS

IHDQ

ILDQ

PROG

FLOAT

Supply voltage

Reference at 25°C

Reference at -40°C to +85°C

Reference input impedance

3.0 4.25 6.5 V

5.7 6.0 6.3 V

4.5 - 7.5 V

2.0 5.0 -

- 90 135

Normal operation

- 120 180

- 170 250

Battery input

SB input impedance

DISP input leakage

LCOM input leakage

Internal pulldown

Sense resistor input

SR input impedance

10 - -

--5

-0.2 - 0.2

500 - -

-0.3 - 2.0 V

10 - -

Logic input high VCC- 0.2

Logic input low

Logic input Z

SEGXoutput low, low V

SEGXoutput low, high V

LCOM output high, low V

LCOM output high, high V

PROG

input high current

1-6

input low current

1-6

LCOM source current

SEGXsink current

Open-drain sink current

Open-drain output low

DQ input high

DQ input low

Soft pull-up or pull-down resis tor value (for programming)

Float state external impedance

float - float V

- 0.1 - V

- 0.4 - V

VCC- 0.3

VCC- 0.6

- 1.2 -

-33 - - mA

- - 11.0 mA

- - 5.0 mA

- - 0.5 V

2.5 - - V

- - 0.8 V

- - 200

-5 -

--V

VSS+ 0.2

--V

3.0V initializes the unit.

= 5µA

REF

= 5µA

REF

Ω

= 3V

REF

= 3.0V, DQ = 0

= 4.25V, DQ = 0

= 6.5V, DQ = 0

0 < VSB< V

Ω

A DISP = V

Ω

= V

DISP

SR<VSS

> VSS= charge

-200mV < VSR< V

PROG1–PROG

= 3V, I

–SEG

SEG

= 6.5V, I

SEG

–SEG

VCC= 3V, I

VCC= 6.5V, I

= VCC/2

PROG

= VCC/2

PROG

At V

OHLCH

At V

OLSH

= VSS+ 0.3V

At V

DQ, EMPTY

5mA, DQ, EMPTY

≤

–PROG

PROG

Ω

PROG1–PROG

= discharge;

≤

OLS

OHLCOM

= VCC- 0.6V

= 0.4V

1.75mA

11.0mA

≤

= -5.25mA

= -33.0mA

≥

bq2010

Serial Communication Timing Specification (T

Symbol Parameter Minimum Typical Maximum Unit Notes

CYCH

CYCB

STRH

STRB

DSU

SSU

Note: The open-drain DQ pin should be pulled to at least VCCby the host system for proper DQ operation. DQ

Cycle time, host to bq2010

Cycle time, bq2010 to host

Start hold, host to bq2010

Start hold, bq2010 to host

Data setup

Data hold

Data valid

Stop setup

Stop hold

Stop valid

Break

Break recovery

may be left floating if the serial interface is not used.

3--ms

3-6ms

5--ns

500 - -

- - 750

750 - -

1.50 - - ms

- - 2.25 ms

700 - -

2.95 - - ms

3--ms

1--ms

)

OPR

See note

Serial Communication Timing Illustration

V1V

(R/W

V0V

(R/W

(BREAK)

)

STRH

STRB

)

DSU

SSU

CYCH, tCYCB, tB

TD201002.eps

bq2010

16-Pin SOIC Narrow (SN)

16-Pin SN(SOIC Narrow

Dimension Minimum Maximum

A 0.060 0.070

A1 0.004 0.010

B 0.013 0.020 C 0.007 0.010 D 0.385 0.400 E 0.150 0.160

e 0.045 0.055 H 0.225 0.245 L 0.015 0.035

All dimensions are in inches.

)

.004

Data Sheet Revision History

Change No. Page No. Description Nature of Change

3 4 EDV monitoring

3 6 Table 1, PROG

3 7,8 Self-discharge Add: or disabled as selected by PROG

3 11 Capacity inaccurate

313

3 13 Overload flag

Notes: Changes 1 and 2; please refer to the 1995 Data Book.

Change 3 = Apr. 1995 D changes from Mar. 1994 C.

Nominal available charge register

Was: EDV monitoring is disabled if V Is: EDV monitoring is disabled if V

Was: PROG5= H = Reserved; Is: PROG

Correction: CI is asserted on the 64th charge after the last LMD update or when the bq2010 is reset

NACL stops counting when NACH reaches zero

Was: V Is: V

= H = Disable self-discharge

< -150mV

< -250mV

bq2010

-150mV;

≤

-250mV

≤

Ordering Information

bq2010

Temperature Range:

blank = Commercial (0 to +70°C) N = Industrial (-40 to +85°C)*

Package Option:

SN = 16-pin narrow SOIC

Device:

bq2010 Gas Gauge IC

* Contact factory for availability.

IMPORTANT NOTICE

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TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.

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UNITRODE bq2010 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual