TEXAS INSTRUMENTS UCD8220, UCD8620 Technical data

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DIGITALLY MANAGED PUSH-PULL ANALOG PWM CONTROLLERS

UCD8220, UCD8620

SLUS652B – MARCH 2005 – REVISED SEPTEMBER 2005

FEATURES

• For Digitally Managed Power Supplies Using µ Cs or the TMS320 ™ DSP Family

• Voltage or Peak Current Mode Control with

Cycle-by-Cycle Current Limiting

• Clock input from Digital Controller to set Operating Frequency and Max Duty Cycle

• Analog PWM Comparator

• 2-MHz Switching Frequency

• 110-V Input Startup Circuit and Thermal

Shutdown (UCD8620)

• Internal Programmable Slope Compensation

• 3.3-V, 10-mA Linear Regulator

• DSP/ µ C Compatible Inputs

• Dual ±4-A TrueDrive™ High Current Drivers

• 10-ns Typical Rise and Fall Times with 2.2-nF

• 25-ns Input-to-Output Propagation Delay

• 25-ns Current Sense-to-Output Propagation

Delay

• Programmable Current Limit Threshold

• Digital Output Current Limit Flag

• 4.5-V to 15.5-V Supply Voltage Range

• Rated from -40°C to 105°C

APPLICATIONS

• Digitally Managed Switch Mode Power

Supplies

• Push-Pull, Half-Bridge, or Full-Bridge

Converters

• Battery Chargers

DESCRIPTION

The UCD8220 and UCD8620 are members of the UCD8K family of analog pulse-width modulator devices to be used in digitally managed power supplies using a microcontroller or the TMS320™ DSP family.

UCD8220 and UCD8620 are double-ended PWM controllers configured with push-pull drive logic. The UCD8620 has a 110-V high-voltage startup circuit which can directly start up the controller from a 48-V telecom input line.

Systems using UCD8K devices close the PWM feedback loop with traditional analog methods, but the UCD8K controllers include circuitry to interpret a time-domain digital pulse train. The pulse train contains the operating frequency and maximum duty cycle limit which are used to control the power supply operation. This eases implementation of a converter with high level control features without the added complexity or possible PWM resolution limitations of closing the control loop in the discrete time domain.

Figure 1. UCD8220 Typical Simplified Push-Pull Converter Application Schematic

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

TMS320, TrueDrive, PowerPAD are trademarks of Texas Instruments.

UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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UCD8220, UCD8620

SLUS652B – MARCH 2005 – REVISED SEPTEMBER 2005

DESCRIPTION (continued)

The UCD8220 and UCD8620 can be configured for either peak current mode or voltage mode control. They provide a programmable current limit function and a digital output current limit flag which can be monitored by the host controller to set the current limit operation. For fast switching speeds, the output stages use the TrueDrive™ architecture, which delivers rated current of ±4 A into the gate of a MOSFET. Finally they also include a 3.3-V, 10-mA linear regulator to provide power to the digital controller or act as a reference in the system.

The UCD8K controller family is compatible with the standard 3.3-V I/O ports of UCD9K digital power controllers, DSPs, Microcontrollers, or ASICs and is offered in PowerPAD™ HTSSOP and QFN packages.

SIMPLIFIED APPLICATION DIAGRAMS

Figure 2. UCD8220 Typical Simplified Half-Bridge Converter Application Schematic

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SIMPLIFIED APPLICATION DIAGRAMS (continued)

UCD8220, UCD8620

SLUS652B – MARCH 2005 – REVISED SEPTEMBER 2005

Figure 3. UCD8620 Typical Simplified Push-Pull Converter Application Schematic

Figure 4. UCD8620 Typical Simplified Half-Bridge Converter Application Schematic

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1 2 3 4 5 6 7 8

16 15 14 13 12 11 10

HTSSOP PACKAGE (PWP −16)

UCD8620 (TOP VIEW)

NC − No internal connection

CLK

3V3

ISET

AGND

CTRL

CLF ILIM

VIN NC VDD PVDD OUT1 OUT2 PGND CS

1 2 3 4 5 6 7 8

16 15 14 13 12 11 10

HTSSOP PACKAGE (PWP −16)

UCD8220 (TOP VIEW)

NC − No internal connection

CLK

3V3

ISET

AGND

CTRL

CLF ILIM

NC NC VDD PVDD OUT1 OUT2 PGND CS

3V3

ISET

AGND

CTRL

CLF

NC ILIM NC CS NC

VDD

PVDD

OUT1

OUT2

PGND

QFN PACKAGE (RGW−20) UCD8620 (BOTTOM VIEW)

20 19 18 17 16

6 7 8 9

CLK

NC NC

VIN

15 14 13 12 11

1 2 3 4 5

3V3

ISET

AGND

CTRL

16 15 14 13

CLK

NC NC

VDD

QFN PACKAGE (RSA−16)

UCD8220 (BOTTOM VIEW)

5 6 7 8

CLF ILIM NC CS

2 3 4

12 11 10 9

PVDD

OUT1

OUT2

PGND

UCD8220, UCD8620

SLUS652B – MARCH 2005 – REVISED SEPTEMBER 2005

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

CONNECTION DIAGRAMS

TEMPERATURE RANGE

-40°C to 105°C No UCD8220PWP UCD8220RSA -

(1) HTSSOP-16 (PWP), QFN-16 (RSA), and QFN-20 (RGW) packages are available taped and reeled. Add R suffix to device type (e.g.

UCD8620PWPR) to order quantities of 2,000 devices per reel for the PWP package and 1,000 devices per reel for the RSA and RGW packages.

(2) These products are packaged in Pb-Free and Green lead finish of Pd-Ni-Au which is compatible with MSL level 1 at 255°C to 260°C

peak reflow temperature to be compatible with either lead free or Sn/Pb soldering operations.

(3) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

Web site at www.ti.com .

(4) Contact factory for availability of QFN packaging. (5) Product preview stage of development.

ORDERING INFORMATION

110-V HV STARTUP

CIRCUIT

Yes UCD8620PWP

PowerPAD™

HTSSOP-16 (PWP)

PACKAGED DEVICES

QFN-16 (RSA)

(5)

- UCD8620RGW

(1) (2) (3)

(4)

QFN-20 (RGW)

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UCD8220, UCD8620

SLUS652B – MARCH 2005 – REVISED SEPTEMBER 2005

PACKAGING INFORMATION

PACKAGE SUFFIX θJC( ° C/W) θJA( ° C/W) = 70 ° C, TJ= 125 ° C ABOVE 70 ° C

POWER RATING T

(mW) (mW/ ° C)

PowerPad™

MSSOP-16

PWP 2.07 37.47

(1)

1470 27

QFN-16 RSA - - - QFN-20 RGW - - - -

(1) PowerPad™ soldered to the PWB with TI recommended PWB as defined in TI's Application Report ( TI Literature Number SLMA002 )

with OLFM.

RATING FACTOR

ABSOLUTE MAXIMUM RATINGS

(1) (2)

SYMBOL PARAMETER UCD8x20 UNIT

O(sink)

O(source)

Input Line Voltage UCD8620 only 110 Supply Voltage 16

Supply Current mA

Quiescent 20 Switching, TA= 25 ° C, TJ= 125 ° C, V

= 12 V 200

Output Gate Drive Voltage OUT -1 to PVDD V

Output Gate Drive Current OUT A

4.0

-4.0 Analog Input ISET, CS, CTRL, ILIM -0.3 to 3.6 V Digital I/O’s CLK, CLF -0.3 to 3.6

TA= 25°C (PWP-16 package) 2.67

Power Dissipation TA= 25°C (QFN-16 package) -

TA= 25°C (QFN-20 package) -

stg

HBM Human body model 2000 CDM Change device model 500

Junction Operating Temperature

Storage Temperature -65 to 150

ESD Rating

(3)

UCD8220 -55 to 150 UCD8620 -55 to 130 °C

Lead Temperature (Soldering, 10 sec) 300 °C

(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating

conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltages are with respect to GND. Currents are positive into, negative out of the specified terminal. (3) Tested to JEDEC standard EIA/JESD22 - A114-B.

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UCD8220, UCD8620

SLUS652B – MARCH 2005 – REVISED SEPTEMBER 2005

ELECTRICAL CHARACTERISTICS

= 12 V, 4.7-µF capacitor from V

TA= TJ= -40°C to 105°C, (unless otherwise noted).

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SUPPLY SECTION

Supply current, OFF V

Supply current, ON mA

LOW VOLTAGE UNDERVOLTAGE LOCKOUT (UCD8220 only)

UVLO ON 4.25 4.5 4.75

UVLO OFF 4.05 4.25 4.45

UVLO hysteresis 150 250 350 mV

110-V HIGH VOLTAGE UNDERVOLTAGE LOCKOUT AND JFET CONTROL (UCD8620 ONLY)

UVLO ON 12.5 13 13.5

UVLO OFF 7 7.5 8

JFET turn-off threshold (V JFET turn-on threshold No switching 11.5 12 12.5 JFET on/off hysteresis 1

High voltage JFET current mA

Thermal shutdown, OFF Thermal shutdown, ON

REFERENCE / EXTERNAL BIAS SUPPLY

3V3 initial set point TA= 25°C, I 3V3 set point over temperature 3.234 3.3 3.366 3V3 load regulation I 3V3 line regulation VDD = 4.75 V to 12 V, I Short circuit current VDD = 4.75 to 12 V 11 20 35 mA 3V3 OK threshold, ON 3.3 V rising 2.9 3.0 3.1 3V3 OK threshold, OFF 3.3 V falling 2.7 2.8 2.9

CLOCK INPUT (CLK)

HIGH, positive-going input threshold voltage (VIT+)

LOW negative-going input threshold voltage (VIT-)

Input voltage hysteresis, (VIT+ - VIT-)

Frequency OUTx = 1 MHz - - 2 MHz Minimum allowable off time

SLOPE COMPENSATION (ISET)

ISET Voltage V

m, V

(I-Mode) R

SLOPE

(V-Mode) R

SLOPE

START_JFET

(1)

to AGND, 1 µ F from PVDD to PGND, 0.22-µF capacitor from 3V3 to AGND,

= 4.2 V µA

UCD8620 500 800

UCD8220 300 500 (UCD8620), outputs not switching, CLK = low 2 3 (UCD8220), outputs not switching, CLK = low 2 3

) No switching, JFET on at startup 12.5 13 13.5 V

< 5 V, VIN = 18 V to 76 V 3 5 8

= 12 V, VIN = 18 V to 76 V 10

= 5 V to 12 V 130 145 160

> 5 V 110 125 140

= 0 3.267 3.3 3.333

LOAD

= 1 mA to 10 mA, VDD = 5 V - 1 6.6

LOAD

= 10 mA - 1 6.6

LOAD

1.65 - 2.08

1.16 - 1.5 V

0.6 - 0.8

, 3V3 = 3.3 V, +/-2% 1.78 1.84 1.90 V

ISET

= 6.19 k Ω to AGND, CS = 0.25 V, CTRL = 2.5 V 1.48 2.12 2.76

ISET

= 100 k Ω to AGND, CS = 0.25 V, CTRL = 2.5 V 0.099 0.142 0.185

ISET

= 499 k Ω to AGND, CS = 0.25 V, CTRL = 2.5 V 0.019 0.028 0.037

ISET

= 4.99 k Ω to 3V3, CTRL = 2.5 V 1.44 2.06 2.68

ISET

= 100 k Ω to 3V3, CTRL = 2.5 V 0.079 0.114 0.148

ISET

= 402 k Ω to 3v3, CTRL = 2.5 V 0.019 0.027 0.035

ISET

°C

20 ns

V/µs

(1) Ensured by design. Not 100% tested in production. 6

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VIT−

10%

90%

INPUT

OUTPUT

VIT+

UCD8220, UCD8620

SLUS652B – MARCH 2005 – REVISED SEPTEMBER 2005

ELECTRICAL CHARACTERISTICS (continued)

= 12 V, 4.7-µF capacitor from V

TA= TJ= -40°C to 105°C, (unless otherwise noted).

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ISET resistor range Current mode control; R ISET resistor range Voltage mode control; R

ISET current range 3.7 300 µ A

PWM

PWM offset at CTRL input 3V3 = 3.3 V +/-2% 0.45 0.51 0.6 V CTRL buffer gain

CURRENT LIMIT (ILIM)

ILIM internal current limit threshold ILIM = OPEN 0.466 0.5 0.536 V ILIM maximum current limit threshold ILIM = 3.3 V 0.975 1.025 1.075 ILIM current limit threshold ILIM = 0.75 V 0.700 0.725 0.750 ILIM minimum current limit threshold ILIM = 0.25 V 0.21 0.23 0.25 V CLF output high level CS > ILIM , I CLF output low level CS ≤ ILIM, I Propagation delay from CLK to CLF CLK rising to CLF falling after a current limit event - 15 25 ns

CURRENT SENSE COMPARATOR

Bias voltage Includes CS comp offset 5 25 50 mV Input bias current - –1 - µ A Propagation delay from CS to OUTx ILIM = 0.5 V, measured on OUTx, CS = threshold + 60 mV - 25 40 Propagation delay from CS to CLF ILIM = 0.5 V, measured on CLF, CS = threshold + 60 mV - 25 50

CURRENT SENSE DISCHARGE TRANSISTOR

Discharge resistance CLK = low, resistance from CS to AGND 10 35 75 Ω

OUTPUT DRIVERS

Source current Sink current Source current Sink current Rise time, t Fall time, t Output with V

Propagation delay from CLK to OUTx ns

(2) Ensured by design. Not 100% tested in production.

(1)

(2)

< UVLO V

to AGND, 1 µ F from PVDD to PGND, 0.22-µF capacitor from 3V3 to AGND,

connected to AGND 6.19 499

ISET

connected to 3V3 4.99 402

ISET

Voltage mode control with Feed-Forward; R VIN

ISET

connected to

Gain from CTRL to PWM comparator input 0.5 V/V

= -7 mA 2.64 - -

LOAD

= 7 mA - - 0.66

LOAD

= 12 V, CLK = high, OUTx = 5 V - 4 -

= 12 V, CLK = low, OUTx = 5 V - 4 -

= 4.75 V, CLK = high, OUTx = 0 - 2 -

= 4.75 V, CLK = low, OUTx = 4.75 V - 3 -

C C

LOAD LOAD DD LOAD LOAD

= 2.2 nF, V = 2.2 nF, V

= 1.0 V, I

= open, V = open, V

= 12 V - 10 20

= 12 V - 10 15

= 10 mA - 0.8 1.2 V

SINK

= 12 V, CLK rising, t

= 12 V, CLK falling, t

- 25 35 25 35

k Ω

Figure 5. Timing Diagram

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CURRENT

LIMIT

PWM

DRIVE

LOGIC

CURRENT

SENSE

3V3 Regulator

and

Reference

UVLO

14 VDD

PVDD

OUT1

OUT2

PGND

3V3

ISET

AGND

ILIM

CLF

CTRL

CLK

CURRENT

LIMIT

PWM

DRIVE

LOGIC

CURRENT

SENSE

3V3 Regulator

and

Reference

UVLO

VDD

VIN

PVDD

OUT1

OUT2

PGND

3V3

ISET

AGND

ILIM

CLF

CTRL

CLK

110−V HV

Start−up

and

JFET Control

UCD8220, UCD8620

SLUS652B – MARCH 2005 – REVISED SEPTEMBER 2005

FUNCTIONAL BLOCK DIAGRAMS

Figure 6. UCD8220

Figure 7. UCD8620

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UCD8220, UCD8620

SLUS652B – MARCH 2005 – REVISED SEPTEMBER 2005

TERMINAL FUNCTIONS

PIN NUMBER

PIN NAME I/O FUNCTION

CLK 2 16 2 20 I 3.3-V logic level signals up to 2 MHz. There is an internal Schmitt trigger

CLF 7 5 7 5 O high. The CLF signal is latched high until the device receives the next rising

ISET 4 2 4 2 I sation in Peak-Current Mode control or to set the frequency in voltage mode

3V3 3 1 3 1 O sourcing up to 10 mA of current. Place 0.22 µ F of ceramic capacitance from

AGND 5 3 5 3 - Analog ground return

ILIM 8 6 8 7 I

CTRL 6 4 6 4 I input is multiplied by 0.5 and routed to the negative input of the PWM

NC 1, 15, 16 7, 14, 15 1, 15 - No connection.

CS 9 8 9 9 I used to protect the power stage by implementing cycle-by-cycle current

PGND

OUT2 11 10 11 12 O The high-current TrueDrive™ driver output. OUT1 12 11 12 13 O The high-current TrueDrive™ driver output.

PVDD 13 12 13 14 to the VDD supply rail. The bypass capacitor for this pin should be returned to

VDD 14 13 14 15 I

VIN

UCD8220 UCD8620

HTSSOP-16 QFN-16 HTSSOP-16 QFN-20

(PWP) (RSA) (PWP) (RGW)

Clock. Input pulse train contains operating frequency and maximum duty cycle limit. This pin is a high impedance digital input capable of accepting

comparator which isolates the internal circuitry CLK 2 16 2 20 I from any external noise.

Current limit flag. When the CS level is greater than the ILIM voltage minus 25 mV, the output driver is forced low and the current limit flag (CLF) is set

edge on the CLK pin. This signal is also used for the start-up handshaking between the Digital controller and the analog controller

Pin for programming the current used to set the amount of slope compencontrol.

Regulated 3.3-V rail. The onboard linear voltage regulator is capable of this pin to analog ground.

Current limit threshold set pin. The current limit threshold can be set to any value between 0.25 V and 1.0 V. The default value while open is 0.5 V.

Input for the error feedback voltage from the external error amplifier. This comparator

6, 8, 10,

16, 18, 19

Current sense pin. Fast current limit comparator connected to the CS pin is limiting.

10 9 10 11 - Power ground return. This pin should be connected close to the source of the

power MOSFET.

Supply pin provides power for the output drivers. It is not connected internally PGND.

Supply input pin to power the control circuitry. Bypass the pin with at least

4.7 µ F of capacitance, returned to AGND.

- - 16 17 I Input to the internal start-up circuitry rated to 110 V. This pin connects directly to the input power rail.

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−50 50

5.0

4.5

2.5

2.0

1.5

0.5

0.0

−25 0 25 75 100

4.0

1.0

3.5

3.0

UVLO on

UVLO off

UVLO hysteresis

t − Temperature − °C

125

UVLO

− UVLO Thresholds − V

−50 50

5.0

4.5

2.5

2.0

1.5

0.5

0.0

−25 0 25 75 100

4.0

1.0

3.5

3.0

UVLO on

UVLO off

TBD

UVLO hysteresis

t − Temperature − °C

125

UVLO

− UVLO Thresholds − V

−50 50 125−25 0 25 75 100

20.0

20.5

21.0

21.5

22.0

22.5

23.0

t − Temperature − °C

SHORT_CKT

− Short Circuit Current − mA

VDD = 4.75 V

VDD = 12 V

−50 50 125−25 0 25 75 100

3.24

3.26

3.28

3.30

3.32

3.34

3.36

t − Temperature − °C

3V3 − Reference Voltage − V

UCD8220, UCD8620

SLUS652B – MARCH 2005 – REVISED SEPTEMBER 2005

UCD8220 UCD8620

UVLO THRESHOLD UVLO THRESHOLD

vs vs

TEMPERATURE TEMPERATURE

TYPICAL CHARACTERISTICS

Figure 8. Figure 9.

3V3 REFERENCE VOLTAGE 3V3 SHORT-CIRCUIT CURRENT

vs vs

TEMPERATURE TEMPERATURE

Figure 10. Figure 11.

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