TEXAS INSTRUMENTS UCD8220, UCD8620 Technical data

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DIGITALLY MANAGED PUSH-PULL ANALOG PWM CONTROLLERS

UCD8220, UCD8620

SLUS652B – MARCH 2005 – REVISED SEPTEMBER 2005

FEATURES

• For Digitally Managed Power Supplies Using µ Cs or the TMS320 ™ DSP Family

• Voltage or Peak Current Mode Control with

Cycle-by-Cycle Current Limiting

• Clock input from Digital Controller to set Operating Frequency and Max Duty Cycle

• Analog PWM Comparator

• 2-MHz Switching Frequency

• 110-V Input Startup Circuit and Thermal

Shutdown (UCD8620)

• Internal Programmable Slope Compensation

• 3.3-V, 10-mA Linear Regulator

• DSP/ µ C Compatible Inputs

• Dual ±4-A TrueDrive™ High Current Drivers

• 10-ns Typical Rise and Fall Times with 2.2-nF

• 25-ns Input-to-Output Propagation Delay

• 25-ns Current Sense-to-Output Propagation

Delay

• Programmable Current Limit Threshold

• Digital Output Current Limit Flag

• 4.5-V to 15.5-V Supply Voltage Range

• Rated from -40°C to 105°C

APPLICATIONS

• Digitally Managed Switch Mode Power

Supplies

• Push-Pull, Half-Bridge, or Full-Bridge

Converters

• Battery Chargers

DESCRIPTION

The UCD8220 and UCD8620 are members of the UCD8K family of analog pulse-width modulator devices to be used in digitally managed power supplies using a microcontroller or the TMS320™ DSP family.

UCD8220 and UCD8620 are double-ended PWM controllers configured with push-pull drive logic. The UCD8620 has a 110-V high-voltage startup circuit which can directly start up the controller from a 48-V telecom input line.

Systems using UCD8K devices close the PWM feedback loop with traditional analog methods, but the UCD8K controllers include circuitry to interpret a time-domain digital pulse train. The pulse train contains the operating frequency and maximum duty cycle limit which are used to control the power supply operation. This eases implementation of a converter with high level control features without the added complexity or possible PWM resolution limitations of closing the control loop in the discrete time domain.

Figure 1. UCD8220 Typical Simplified Push-Pull Converter Application Schematic

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

TMS320, TrueDrive, PowerPAD are trademarks of Texas Instruments.

UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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UCD8220, UCD8620

SLUS652B – MARCH 2005 – REVISED SEPTEMBER 2005

DESCRIPTION (continued)

The UCD8220 and UCD8620 can be configured for either peak current mode or voltage mode control. They provide a programmable current limit function and a digital output current limit flag which can be monitored by the host controller to set the current limit operation. For fast switching speeds, the output stages use the TrueDrive™ architecture, which delivers rated current of ±4 A into the gate of a MOSFET. Finally they also include a 3.3-V, 10-mA linear regulator to provide power to the digital controller or act as a reference in the system.

The UCD8K controller family is compatible with the standard 3.3-V I/O ports of UCD9K digital power controllers, DSPs, Microcontrollers, or ASICs and is offered in PowerPAD™ HTSSOP and QFN packages.

SIMPLIFIED APPLICATION DIAGRAMS

Figure 2. UCD8220 Typical Simplified Half-Bridge Converter Application Schematic

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SIMPLIFIED APPLICATION DIAGRAMS (continued)

UCD8220, UCD8620

SLUS652B – MARCH 2005 – REVISED SEPTEMBER 2005

Figure 3. UCD8620 Typical Simplified Push-Pull Converter Application Schematic

Figure 4. UCD8620 Typical Simplified Half-Bridge Converter Application Schematic

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1 2 3 4 5 6 7 8

16 15 14 13 12 11 10

HTSSOP PACKAGE (PWP −16)

UCD8620 (TOP VIEW)

NC − No internal connection

CLK

3V3

ISET

AGND

CTRL

CLF ILIM

VIN NC VDD PVDD OUT1 OUT2 PGND CS

1 2 3 4 5 6 7 8

16 15 14 13 12 11 10

HTSSOP PACKAGE (PWP −16)

UCD8220 (TOP VIEW)

NC − No internal connection

CLK

3V3

ISET

AGND

CTRL

CLF ILIM

NC NC VDD PVDD OUT1 OUT2 PGND CS

3V3

ISET

AGND

CTRL

CLF

NC ILIM NC CS NC

VDD

PVDD

OUT1

OUT2

PGND

QFN PACKAGE (RGW−20) UCD8620 (BOTTOM VIEW)

20 19 18 17 16

6 7 8 9

CLK

NC NC

VIN

15 14 13 12 11

1 2 3 4 5

3V3

ISET

AGND

CTRL

16 15 14 13

CLK

NC NC

VDD

QFN PACKAGE (RSA−16)

UCD8220 (BOTTOM VIEW)

5 6 7 8

CLF ILIM NC CS

2 3 4

12 11 10 9

PVDD

OUT1

OUT2

PGND

UCD8220, UCD8620

SLUS652B – MARCH 2005 – REVISED SEPTEMBER 2005

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

CONNECTION DIAGRAMS

TEMPERATURE RANGE

-40°C to 105°C No UCD8220PWP UCD8220RSA -

(1) HTSSOP-16 (PWP), QFN-16 (RSA), and QFN-20 (RGW) packages are available taped and reeled. Add R suffix to device type (e.g.

UCD8620PWPR) to order quantities of 2,000 devices per reel for the PWP package and 1,000 devices per reel for the RSA and RGW packages.

(2) These products are packaged in Pb-Free and Green lead finish of Pd-Ni-Au which is compatible with MSL level 1 at 255°C to 260°C

peak reflow temperature to be compatible with either lead free or Sn/Pb soldering operations.

(3) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

Web site at www.ti.com .

(4) Contact factory for availability of QFN packaging. (5) Product preview stage of development.

ORDERING INFORMATION

110-V HV STARTUP

CIRCUIT

Yes UCD8620PWP

PowerPAD™

HTSSOP-16 (PWP)

PACKAGED DEVICES

QFN-16 (RSA)

(5)

- UCD8620RGW

(1) (2) (3)

(4)

QFN-20 (RGW)

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UCD8220, UCD8620

SLUS652B – MARCH 2005 – REVISED SEPTEMBER 2005

PACKAGING INFORMATION

PACKAGE SUFFIX θJC( ° C/W) θJA( ° C/W) = 70 ° C, TJ= 125 ° C ABOVE 70 ° C

POWER RATING T

(mW) (mW/ ° C)

PowerPad™

MSSOP-16

PWP 2.07 37.47

(1)

1470 27

QFN-16 RSA - - - QFN-20 RGW - - - -

(1) PowerPad™ soldered to the PWB with TI recommended PWB as defined in TI's Application Report ( TI Literature Number SLMA002 )

with OLFM.

RATING FACTOR

ABSOLUTE MAXIMUM RATINGS

(1) (2)

SYMBOL PARAMETER UCD8x20 UNIT

O(sink)

O(source)

Input Line Voltage UCD8620 only 110 Supply Voltage 16

Supply Current mA

Quiescent 20 Switching, TA= 25 ° C, TJ= 125 ° C, V

= 12 V 200

Output Gate Drive Voltage OUT -1 to PVDD V

Output Gate Drive Current OUT A

4.0

-4.0 Analog Input ISET, CS, CTRL, ILIM -0.3 to 3.6 V Digital I/O’s CLK, CLF -0.3 to 3.6

TA= 25°C (PWP-16 package) 2.67

Power Dissipation TA= 25°C (QFN-16 package) -

TA= 25°C (QFN-20 package) -

stg

HBM Human body model 2000 CDM Change device model 500

Junction Operating Temperature

Storage Temperature -65 to 150

ESD Rating

(3)

UCD8220 -55 to 150 UCD8620 -55 to 130 °C

Lead Temperature (Soldering, 10 sec) 300 °C

(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating

conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltages are with respect to GND. Currents are positive into, negative out of the specified terminal. (3) Tested to JEDEC standard EIA/JESD22 - A114-B.

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UCD8220, UCD8620

SLUS652B – MARCH 2005 – REVISED SEPTEMBER 2005

ELECTRICAL CHARACTERISTICS

= 12 V, 4.7-µF capacitor from V

TA= TJ= -40°C to 105°C, (unless otherwise noted).

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SUPPLY SECTION

Supply current, OFF V

Supply current, ON mA

LOW VOLTAGE UNDERVOLTAGE LOCKOUT (UCD8220 only)

UVLO ON 4.25 4.5 4.75

UVLO OFF 4.05 4.25 4.45

UVLO hysteresis 150 250 350 mV

110-V HIGH VOLTAGE UNDERVOLTAGE LOCKOUT AND JFET CONTROL (UCD8620 ONLY)

UVLO ON 12.5 13 13.5

UVLO OFF 7 7.5 8

JFET turn-off threshold (V JFET turn-on threshold No switching 11.5 12 12.5 JFET on/off hysteresis 1

High voltage JFET current mA

Thermal shutdown, OFF Thermal shutdown, ON

REFERENCE / EXTERNAL BIAS SUPPLY

3V3 initial set point TA= 25°C, I 3V3 set point over temperature 3.234 3.3 3.366 3V3 load regulation I 3V3 line regulation VDD = 4.75 V to 12 V, I Short circuit current VDD = 4.75 to 12 V 11 20 35 mA 3V3 OK threshold, ON 3.3 V rising 2.9 3.0 3.1 3V3 OK threshold, OFF 3.3 V falling 2.7 2.8 2.9

CLOCK INPUT (CLK)

HIGH, positive-going input threshold voltage (VIT+)

LOW negative-going input threshold voltage (VIT-)

Input voltage hysteresis, (VIT+ - VIT-)

Frequency OUTx = 1 MHz - - 2 MHz Minimum allowable off time

SLOPE COMPENSATION (ISET)

ISET Voltage V

m, V

(I-Mode) R

SLOPE

(V-Mode) R

SLOPE

START_JFET

(1)

to AGND, 1 µ F from PVDD to PGND, 0.22-µF capacitor from 3V3 to AGND,

= 4.2 V µA

UCD8620 500 800

UCD8220 300 500 (UCD8620), outputs not switching, CLK = low 2 3 (UCD8220), outputs not switching, CLK = low 2 3

) No switching, JFET on at startup 12.5 13 13.5 V

< 5 V, VIN = 18 V to 76 V 3 5 8

= 12 V, VIN = 18 V to 76 V 10

= 5 V to 12 V 130 145 160

> 5 V 110 125 140

= 0 3.267 3.3 3.333

LOAD

= 1 mA to 10 mA, VDD = 5 V - 1 6.6

LOAD

= 10 mA - 1 6.6

LOAD

1.65 - 2.08

1.16 - 1.5 V

0.6 - 0.8

, 3V3 = 3.3 V, +/-2% 1.78 1.84 1.90 V

ISET

= 6.19 k Ω to AGND, CS = 0.25 V, CTRL = 2.5 V 1.48 2.12 2.76

ISET

= 100 k Ω to AGND, CS = 0.25 V, CTRL = 2.5 V 0.099 0.142 0.185

ISET

= 499 k Ω to AGND, CS = 0.25 V, CTRL = 2.5 V 0.019 0.028 0.037

ISET

= 4.99 k Ω to 3V3, CTRL = 2.5 V 1.44 2.06 2.68

ISET

= 100 k Ω to 3V3, CTRL = 2.5 V 0.079 0.114 0.148

ISET

= 402 k Ω to 3v3, CTRL = 2.5 V 0.019 0.027 0.035

ISET

°C

20 ns

V/µs

(1) Ensured by design. Not 100% tested in production. 6

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VIT−

10%

90%

INPUT

OUTPUT

VIT+

UCD8220, UCD8620

SLUS652B – MARCH 2005 – REVISED SEPTEMBER 2005

ELECTRICAL CHARACTERISTICS (continued)

= 12 V, 4.7-µF capacitor from V

TA= TJ= -40°C to 105°C, (unless otherwise noted).

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

ISET resistor range Current mode control; R ISET resistor range Voltage mode control; R

ISET current range 3.7 300 µ A

PWM

PWM offset at CTRL input 3V3 = 3.3 V +/-2% 0.45 0.51 0.6 V CTRL buffer gain

CURRENT LIMIT (ILIM)

ILIM internal current limit threshold ILIM = OPEN 0.466 0.5 0.536 V ILIM maximum current limit threshold ILIM = 3.3 V 0.975 1.025 1.075 ILIM current limit threshold ILIM = 0.75 V 0.700 0.725 0.750 ILIM minimum current limit threshold ILIM = 0.25 V 0.21 0.23 0.25 V CLF output high level CS > ILIM , I CLF output low level CS ≤ ILIM, I Propagation delay from CLK to CLF CLK rising to CLF falling after a current limit event - 15 25 ns

CURRENT SENSE COMPARATOR

Bias voltage Includes CS comp offset 5 25 50 mV Input bias current - –1 - µ A Propagation delay from CS to OUTx ILIM = 0.5 V, measured on OUTx, CS = threshold + 60 mV - 25 40 Propagation delay from CS to CLF ILIM = 0.5 V, measured on CLF, CS = threshold + 60 mV - 25 50

CURRENT SENSE DISCHARGE TRANSISTOR

Discharge resistance CLK = low, resistance from CS to AGND 10 35 75 Ω

OUTPUT DRIVERS

Source current Sink current Source current Sink current Rise time, t Fall time, t Output with V

Propagation delay from CLK to OUTx ns

(2) Ensured by design. Not 100% tested in production.

(1)

(2)

< UVLO V

to AGND, 1 µ F from PVDD to PGND, 0.22-µF capacitor from 3V3 to AGND,

connected to AGND 6.19 499

ISET

connected to 3V3 4.99 402

ISET

Voltage mode control with Feed-Forward; R VIN

ISET

connected to

Gain from CTRL to PWM comparator input 0.5 V/V

= -7 mA 2.64 - -

LOAD

= 7 mA - - 0.66

LOAD

= 12 V, CLK = high, OUTx = 5 V - 4 -

= 12 V, CLK = low, OUTx = 5 V - 4 -

= 4.75 V, CLK = high, OUTx = 0 - 2 -

= 4.75 V, CLK = low, OUTx = 4.75 V - 3 -

C C

LOAD LOAD DD LOAD LOAD

= 2.2 nF, V = 2.2 nF, V

= 1.0 V, I

= open, V = open, V

= 12 V - 10 20

= 12 V - 10 15

= 10 mA - 0.8 1.2 V

SINK

= 12 V, CLK rising, t

= 12 V, CLK falling, t

- 25 35 25 35

k Ω

Figure 5. Timing Diagram

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CURRENT

LIMIT

PWM

DRIVE

LOGIC

CURRENT

SENSE

3V3 Regulator

and

Reference

UVLO

14 VDD

PVDD

OUT1

OUT2

PGND

3V3

ISET

AGND

ILIM

CLF

CTRL

CLK

CURRENT

LIMIT

PWM

DRIVE

LOGIC

CURRENT

SENSE

3V3 Regulator

and

Reference

UVLO

VDD

VIN

PVDD

OUT1

OUT2

PGND

3V3

ISET

AGND

ILIM

CLF

CTRL

CLK

110−V HV

Start−up

and

JFET Control

UCD8220, UCD8620

SLUS652B – MARCH 2005 – REVISED SEPTEMBER 2005

FUNCTIONAL BLOCK DIAGRAMS

Figure 6. UCD8220

Figure 7. UCD8620

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UCD8220, UCD8620

SLUS652B – MARCH 2005 – REVISED SEPTEMBER 2005

TERMINAL FUNCTIONS

PIN NUMBER

PIN NAME I/O FUNCTION

CLK 2 16 2 20 I 3.3-V logic level signals up to 2 MHz. There is an internal Schmitt trigger

CLF 7 5 7 5 O high. The CLF signal is latched high until the device receives the next rising

ISET 4 2 4 2 I sation in Peak-Current Mode control or to set the frequency in voltage mode

3V3 3 1 3 1 O sourcing up to 10 mA of current. Place 0.22 µ F of ceramic capacitance from

AGND 5 3 5 3 - Analog ground return

ILIM 8 6 8 7 I

CTRL 6 4 6 4 I input is multiplied by 0.5 and routed to the negative input of the PWM

NC 1, 15, 16 7, 14, 15 1, 15 - No connection.

CS 9 8 9 9 I used to protect the power stage by implementing cycle-by-cycle current

PGND

OUT2 11 10 11 12 O The high-current TrueDrive™ driver output. OUT1 12 11 12 13 O The high-current TrueDrive™ driver output.

PVDD 13 12 13 14 to the VDD supply rail. The bypass capacitor for this pin should be returned to

VDD 14 13 14 15 I

VIN

UCD8220 UCD8620

HTSSOP-16 QFN-16 HTSSOP-16 QFN-20

(PWP) (RSA) (PWP) (RGW)

Clock. Input pulse train contains operating frequency and maximum duty cycle limit. This pin is a high impedance digital input capable of accepting

comparator which isolates the internal circuitry CLK 2 16 2 20 I from any external noise.

Current limit flag. When the CS level is greater than the ILIM voltage minus 25 mV, the output driver is forced low and the current limit flag (CLF) is set

edge on the CLK pin. This signal is also used for the start-up handshaking between the Digital controller and the analog controller

Pin for programming the current used to set the amount of slope compencontrol.

Regulated 3.3-V rail. The onboard linear voltage regulator is capable of this pin to analog ground.

Current limit threshold set pin. The current limit threshold can be set to any value between 0.25 V and 1.0 V. The default value while open is 0.5 V.

Input for the error feedback voltage from the external error amplifier. This comparator

6, 8, 10,

16, 18, 19

Current sense pin. Fast current limit comparator connected to the CS pin is limiting.

10 9 10 11 - Power ground return. This pin should be connected close to the source of the

power MOSFET.

Supply pin provides power for the output drivers. It is not connected internally PGND.

Supply input pin to power the control circuitry. Bypass the pin with at least

4.7 µ F of capacitance, returned to AGND.

- - 16 17 I Input to the internal start-up circuitry rated to 110 V. This pin connects directly to the input power rail.

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−50 50

5.0

4.5

2.5

2.0

1.5

0.5

0.0

−25 0 25 75 100

4.0

1.0

3.5

3.0

UVLO on

UVLO off

UVLO hysteresis

t − Temperature − °C

125

UVLO

− UVLO Thresholds − V

−50 50

5.0

4.5

2.5

2.0

1.5

0.5

0.0

−25 0 25 75 100

4.0

1.0

3.5

3.0

UVLO on

UVLO off

TBD

UVLO hysteresis

t − Temperature − °C

125

UVLO

− UVLO Thresholds − V

−50 50 125−25 0 25 75 100

20.0

20.5

21.0

21.5

22.0

22.5

23.0

t − Temperature − °C

SHORT_CKT

− Short Circuit Current − mA

VDD = 4.75 V

VDD = 12 V

−50 50 125−25 0 25 75 100

3.24

3.26

3.28

3.30

3.32

3.34

3.36

t − Temperature − °C

3V3 − Reference Voltage − V

UCD8220, UCD8620

SLUS652B – MARCH 2005 – REVISED SEPTEMBER 2005

UCD8220 UCD8620

UVLO THRESHOLD UVLO THRESHOLD

vs vs

TEMPERATURE TEMPERATURE

TYPICAL CHARACTERISTICS

Figure 8. Figure 9.

3V3 REFERENCE VOLTAGE 3V3 SHORT-CIRCUIT CURRENT

vs vs

TEMPERATURE TEMPERATURE

Figure 10. Figure 11.

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0 1000 1500500

100

120

140

160

f − Frequency − kHz

− Supply Current − mA

LOAD

= 10 nF

LOAD

= 4.7 nF

LOAD

= 2.2 nF

LOAD

= 1 nF

120

160

200

240

280

0 500

1000

1500

f − Frequency − kHz

− Supply Current − mA

LOAD

= 10 nF

LOAD

= 4.7 nF

LOAD

= 2.2 nF

LOAD

= 1 nF

120

160

200

240

280

320

0 500

1000

1500

f − Frequency − kHz

− Supply Current − mA

LOAD

= 10 nF

LOAD

= 4.7 nF

LOAD

= 2.2 nF

LOAD

= 1 nF

100

150

200

250

300

350

400

500

1000

1500

f − Frequency − kHz

− Supply Current − mA

LOAD

= 10 nF

LOAD

= 4.7 nF

LOAD

= 2.2 nF

LOAD

= 1 nF

TYPICAL CHARACTERISTICS (continued)

UCD8220, UCD8620

SLUS652B – MARCH 2005 – REVISED SEPTEMBER 2005

SUPPLY CURRENT SUPPLY CURRENT

vs vs

FREQUENCY (V

= 5 V) FREQUENCY (V

Figure 12. Figure 13.

= 8 V)

SUPPLY CURRENT SUPPLY CURRENT

FREQUENCY (V

vs vs

= 10 V) FREQUENCY (V

Figure 14. Figure 15.

= 12 V)

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100

150

200

250

300

350

400

450

500

1000

1500

f − Frequency − kHz

− Supply Current − mA

LOAD

= 10 nF

LOAD

= 4.7 nF

LOAD

= 2.2 nF

LOAD

= 1 nF

−50 50 125−25 0 25 75 100

0.0

0.5

1.0

1.5

2.0

2.5

TJ− Temperature − °C

V − CLK Input V

oltage − V

CLK Input Rising

CLK Input Falling

5 7.5 10 12.5 15

VDD− Supply Voltage − V

t − Output Rise T

ime − ns

LOAD

= 10 nF

LOAD

= 4.7 nF

LOAD

= 2.2 nF

LOAD

= 1 nF

−50 50 125−25 0 25 75 100

TJ− Temperature − °C

− Rise and Fall Times − ns

tR= Rise Time

tF= Fall Time

LOAD

= 2.2 nF

UCD8220, UCD8620

SLUS652B – MARCH 2005 – REVISED SEPTEMBER 2005

TYPICAL CHARACTERISTICS (continued)

SUPPLY CURRENT CLK INPUT THRESHOLD

vs vs

FREQUENCY (V

= 15 V) TEMPERATURE

Figure 16. Figure 17.

OUTPUT RISE TIME AND FALL TIME OUTPUT RISE TIME

TEMPERATURE (V

Figure 18. Figure 19.

vs vs

= 12 V) SUPPLY VOLTAGE

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5 7.5 10 12.5 15

VDD− Supply Voltage − V

− Propagation Delay, Rising − ns

LOAD

= 10 nF

LOAD

= 4.7 nF

LOAD

= 2.2 nF

LOAD

= 1 nF

5 7.5 10 12.5 15

VDD− Supply Voltage − V

t − Output Fall T

ime − ns

LOAD

= 10 nF

LOAD

= 4.7 nF

LOAD

= 2.2 nF

LOAD

= 1 nF

5 7.5 10 12.5 15

VDD− Supply Voltage − V

− Propagation Delay, Falling − ns

LOAD

= 10 nF

LOAD

= 4.7 nF

LOAD

= 2.2 nF

LOAD

= 1 nF

−50 50 125−25 0 25 75 100

0.51

0.52

0.53

0.54

0.55

0.56

0.57

0.58

0.59

TJ− Temperature − °C

− Current Limit Threshold − V

TYPICAL CHARACTERISTICS (continued)

UCD8220, UCD8620

SLUS652B – MARCH 2005 – REVISED SEPTEMBER 2005

OUTPUT FALL TIME CLK to OUTx PROPAGATION DELAY RISING

vs vs

SUPPLY VOLTAGE SUPPLY VOLTAGE

Figure 20. Figure 21.

CLK TO OUTx PROPAGATION DELAY FALLING DEFAULT CURRENT LIMIT THRESHOLD

vs vs

SUPPLY CURRENT TEMPERATURE

Figure 22. Figure 23.

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−50 50−25 0 25 75 100

TJ− Temperature − °C

− CS to CLF Propagation Delay − ns

125

−50 50 125−25 0 25 75 100

TJ− Temperature − °C

− CS to OUTx Propagation Delay − ns

t − Time − 40 ms/div

VDD (2 V/div)

CLK = CTRL = 3V3

OUTx (2 V/div)

3V3 (2 V/div)

−50 50 125−25 0 25 75 100

TJ− Temperature − °C

− Propagation Delay − ns

UCD8220, UCD8620

SLUS652B – MARCH 2005 – REVISED SEPTEMBER 2005

TYPICAL CHARACTERISTICS (continued)

CS TO OUTx PROPAGATION DELAY CS TO CLF PROPAGATION DELAY

vs vs

TEMPERATURE TEMPERATURE

Figure 24. Figure 25.

CLK TO OUT PROPAGATION DELAY UCD8220

TEMPERATURE

vs START-UP BEHAVIOR AT V

Figure 26. Figure 27.

= 12 V

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t − Time − 40 ms/div

VDD (2 V/div)

OUTx (2 V/div)

3V3 (2 V/div)

CLK = CTRL = 3V3

t − Time − 40 ms/div

TBD

CLK = CTRL = 3V3

t − Time − 40 ms/div

VDD (2 V/div)

3V3 (2 V/div)

OUTx (2 V/div)

CLK = AGND CTRL = 3V3

t − Time − 40 ms/div

TBD

CLK = CTRL = 3V3

TYPICAL CHARACTERISTICS (continued)

UCD8220, UCD8620

SLUS652B – MARCH 2005 – REVISED SEPTEMBER 2005

START-UP BEHAVIOR AT V

UCD8620 UCD8220

Figure 28. Figure 29.

UCD8620 UCD8220

SHUT-DOWN BEHAVIOR AT V

= 12 V SHUT-DOWN BEHAVIOR AT V

= 12 V START-UP BEHAVIOR AT V

= 12 V

Figure 30. Figure 31.

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t − Time − 40 ms/div

VDD (2 V/div)

3V3 (2 V/div)

OUTx (2 V/div)

CLK = AGND CTRL = 3V3

t − Time − 40 ms/div

TBD

CLK = AGND CTRL = 3V3

t − Time − 40 ns/div

Output Voltage − 2 V/div

t − Time − 40 ms/div

TBD

CLK = AGND CTRL = 3V3

UCD8220, UCD8620

SLUS652B – MARCH 2005 – REVISED SEPTEMBER 2005

TYPICAL CHARACTERISTICS (continued)

START-UP BEHAVIOR AT V

UCD8620 UCD8220

Figure 32. Figure 33.

UCD8620 OUTPUT RISE AND FALL TIME

SHUT-DOWN BEHAVIOR AT V

= 12 V SHUT-DOWN BEHAVIOR AT V

= 12 V (V

= 12 V, C

= 12 V

= 10 nF)

LOAD

Figure 34. Figure 35.

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−50 50 125−25 0 25 75 100

TJ− Temperature − °C

Current Mode Slope, R = 100 k

ISET

0.134

0.136

0.138

0.140

0.142

0.144

0.146

Internal Slope Compensation in CMC - V/ms

0.518

0.520

0.522

0.524

0.526

0.528

0.530

0.532

PWM Offset at CTRL Input − V

−50 50 125−25 0 25 75 100

TJ− Temperature − °C

−50 50 125−25 0 25 75 100

TJ− Temperature − °C

V = 76 V

V = 18 V

V = 12 V

Source Current - mA

TBD

TYPICAL CHARACTERISTICS (continued)

UCD8220, UCD8620

SLUS652B – MARCH 2005 – REVISED SEPTEMBER 2005

INTERNAL SLOPE COMPENSATION IN CMC PWM OFFSET AT CTRL INPUT

vs vs

TEMPERATURE TEMPERATURE

Figure 36. Figure 37.

HIGH VOLTAGE JFET CURRENT

TEMPERATURE

Figure 38.

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UCD8220, UCD8620

SLUS652B – MARCH 2005 – REVISED SEPTEMBER 2005

APPLICATION INFORMATION

Introduction

operating frequency and maximum duty cycle limit

and hence controls the power supply operation as The UCD8220 and UCD8620 are digitally managed listed above. The pulse train uses a Texas Instruanalog PWM controllers configured with push-pull ments communication protocol which is a proprietary drive logic. The UCD8620 has a 110-V high-voltage communication system that provides handles for startup circuit which can directly start up the controller control of the power supply operation through from a 48-V telecom input line. software programming. The rising edge of the CLK

In systems using UCD8K devices, the PWM feedback loop is closed using the traditional analog methods, but the UCD8K controllers include circuitry to interpret a time-domain digital pulse train from a digital controller. The pulse train contains the operating frequency and maximum duty cycle limit and hence controls the power supply operation. This eases implementing a converter with high-level control features without the added complexity or digital PWM resolution limitations encountered when closing the voltage control loop in the discrete time domain.

The UCD8220 and UCD8620 can be configured for either peak current mode or voltage mode control. They provide a programmable current limit function and a digital output current limit flag which can be monitored by the host controller. For fast switching speeds, the output stages use the TrueDrive™ output architecture, which delivers rated current of ±4 A into the gate of a MOSFET during the Miller plateau region of the switching transition. Finally they also include a 3.3-V, 10-mA linear regulator to provide power for the digital controller.

The UCD8620 includes circuitry and features to ease implementing a converter that is managed by a microcontroller or a digital signal processor. Digitally managed power supplies provide software programmability and monitoring capability of the power supply operation including:

• Switching frequency

• Synchronization

• D

MAX

• V x S clamp

• Input UVLO start/stop voltage

• Input OVP start/stop voltage

• Soft-start profile

• Current limit operation

• Shutdown

• Temperature shutdown

signal represents the switching frequency. Figure 39

depicts the operation of the UCD8K device in one of

5 modes. At the time when the internal signal REF

OK is low, the UCD8K device is not ready to accept

CLK inputs. Once the REF OK signal goes high, then

the device is ready to process inputs. While the CLK

input is low, the outputs are disabled and the CLK

signal is used as an enable input. Once the Digital

controller completes its initialization routine and ver-

ifies that all voltages are within their operating range,

then it starts the soft-start procedure by slowly

ramping up the duty cycle of the CLK signal, while

maintaining the desired switching frequency. The duty

cycle continues to increase until it reaches

steady-state where the analog control loop takes over

and regulates the output voltage to the desire set

point. During steady state, the maximum duty cycle

can be set using a volt second product calculation in

order to protect the primary of the power transformer

from saturation during transients. When the power

supply enters current limit, the outputs are quickly

turned off, and the CLF signal is set high in order to

notify the digital controller that the last power pulse

was truncated because of an overcurrent event. The

benefit of this technique is in the flexibility it offers.

The software is now in charge of the response to

overcurrent events. In typical analog designs, the

power supply response to overcurrent is hardwired in

the silicon. With this method, the user can configure

the response differently for different applications. For

example, the software can be configured to latch-off

the power supply in response the first overcurrent

event, or to allow a fixed number of current limit

events, so that the supply is capable of starting up

into a capacitive load. The user can also configure

the supply to enter into hiccup mode immediately or

after a certain number of current limit events. As

described later in this data sheet, the current limit

threshold can be varied in time to create unique

current limit profiles. For example, the current limit set

point can be set high for a predefined number of

cycles to blow a manual fuse, and can be reduced

down to protect the system in the event of a faulty

CLK Input Time-Domain Digital Pulse Train

fuse. While the loop is closed in the analog domain, the

UCD8K devices are managed by a time-domain digital pulse train from a digital controller. The pulse train, shown as CLK in Figure 39 , contains the

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OUT

RAMP*

CTRL

CLF

CLK

UVLO and REF OK*

* - Internal signals

PWM*

Start up Steady State Current Limit

UCD8220, UCD8620

SLUS652B – MARCH 2005 – REVISED SEPTEMBER 2005

Figure 39. UCD8220 and UCD8620 Timing and Circuit Operation Diagram

JFET Operation (UCD8620 Only)

to switch. The JFET remains off provided the outputs

are switching and the VDD voltage stays above 7.5 The UCD8620 digitally managed push-pull analog V. If the VDD voltage drops below 7.5 V while the PWM Controller contains a 110-V start-up JFET to outputs are switching, the outputs are immediately simplify the start-up and standby power requirements disabled, and the JFET is switched back on. It then for systems with digital controllers. The JFET circuit attempts to charge the VDD voltage back up to 13 V. has two operating modes. When the VDD voltage is Once the VDD voltage reaches 13 V, the outputs are less than 5 V, the circuit is limited to 5 mA of source enabled again and allowed to switch. If the CLK input current into VDD. The VDD reaches 5 V, the circuit is not switched by the digital controller, then the VDD switches into temperature protection mode and pro- voltage decays to 12 V, and the JFET turns on again. vides 10 mA until the temperature of the die exceeds This charges the VDD capacitor back to 13 V where 145 ° C. Figure 40 shows the operation of the JET the cycle repeats until the input voltage drops to a circuitry during various operating conditions. At point where the VDD voltage can no longer be start-up, the JFET is on and charges up the VDD maintained. Figure 41 shows the graph of available capacitor. Once the VDD voltage reaches its UVLO of source current as a function of input and VDD 13 V, the JFET turns off and the outputs are allowed voltage.

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0 2 4 6 8 10 12 14

−50

−40

−30

−20

−10

TBD

V - Supply Voltage - V

I − Supp;y Current

− mA

UCD8220, UCD8620

SLUS652B – MARCH 2005 – REVISED SEPTEMBER 2005

(1) For VDD to go below 12 V, the input supply must be dropping out.

Figure 40. UCD8620 JFET Operation Waveforms

Reference / External Bias Supply

All devices in the UCD8K family are capable of

supplying a regulated 3.3-V rail to power various

types of external loads such as a microcontroller or

an ASIC. The onboard linear voltage regulator is

capable of sourcing up to 10 mA of current. For

normal operation, place 0.22-µF of ceramic capaci-

tance between the 3V3 pin and the AGND pin.

Supply

The UCD8K devices accept an input range of 4.5 V to 15.5 V. The device has an internal precision linear regulator that produces the 3V3 output from this VDD input. A separate pin, PVDD, not connected internally to the VDD supply rail provides power for the output drivers. In all applications the same bus voltage must supply the two pins. It is recommended that a low value of resistance be placed between the two pins so that the local capacitance on each pin forms low pass filters to attenuate any switching noise that may be on the bus.

Figure 41. UCD8620 Supply Current vs Supply

Voltage

Current Sensing and Protection

Figure 42. Current Sense Filter

A fast current limit comparator connected to the CS

pin is used to protect the power stage by im-

plementing cycle-by-cycle current limiting.Figure 43

shows various methods for setting the ILIM threshold.

The current limit threshold may be set to any value

between 0.25 V and 1 V by applying the desired

threshold voltage to the current limit (ILIM) pin. If the

ILIM pin is left floating, the internal current limit

threshold is 0.5 V. When the CS level is greater than

the ILIM voltage minus 25 mV, the output of the

driver is forced low and the current limit flag (CLF) is

set high. The CLF signal is latched high until the

UCD8K device receives the next rising edge on the

CLK pin.

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UCD8220, UCD8620

SLUS652B – MARCH 2005 – REVISED SEPTEMBER 2005

When the CS voltage is below ILIM, the driver output restart the device in the event that it is not operating follows the PWM command. The CLF digital output properly. But these peripherals typically do not react flag is monitored by the host controller to determine fast enough to save the power stage. The UCD87K’s when a current limit event occurs, and to then apply local current limit comparator provides the required the appropriate algorithm to obtain the desired current fast protection for the power stage. limit profile (i.e. straight line, fold back, hickup, or latch-off).

A benefit of this local protection feature is that the CS pin is at ground, the CLF flag latches high until UCD8620 devices protects the power stage if the the CLK pin receives a pulse. At start-up, it is software code in the digital controller becomes cor- necessary to ensure that the ILIM pin is always rupted. If the controller’s PWM output stays high, the greater than the CS pin for the handshaking to work. local current sense circuit turns off the driver output If for any reason the CS pin comes to within 25 mV of when an overcurrent event occurs. The system then the ILIM pin during start-up, then the CLF flag is goes into retry mode because most DSP and latched high and the digital controller must poll the microcontrollers have an on-board watchdog, UCD8620 device, by sending it a narrow CLK pulse. brown-out, and other supervisory peripherals to If a fault condition is not present, the CLK pulse

The CS threshold is 25 mV below the ILIM voltage. If

the user attempts to command zero current while the

resets the CLF signal to low indicating that the

UCD8620 device is ready to process power pulses.

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40 kW

20 kW

10 kW

2.5 kW

UCD8220, UCD8620

SLUS652B – MARCH 2005 – REVISED SEPTEMBER 2005

Figure 43. ILIM Settings

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PWM

3V3

CTRL

(6)

ISET

(4)

9.4 pF

int

OUT

TO CLEAR

PWM LATCH

ON OFF

I_SC = (3.3 - 1.85) / (11 x R_ISET)

R_ISET

0.25 V

3V3

(3)

PWM

3V3

CTRL

(6)

ISET

(4)

OUT

ON OFF

R_ISET

0.25 V

VIN

9.4 pF

int

I_SC = (3.3 - 1.85) / (11 x R_ISET)

TO CLEAR

PWM LATCH

11 x 1.4 x fclk x 1000 x 9.4

(3.3 - 1.85) x 10

R_ISET =

11 x 1.4 x fclk x 9.4

(Vin_max - 1.85) x 10

R_ISET =

1 k

10 k

100 k

1 M

1000 1000010 100

Clock Frequency − kHz

R_ISET Resistance − W

UCD8220, UCD8620

SLUS652B – MARCH 2005 – REVISED SEPTEMBER 2005

Selecting the ISET Resistor for Voltage Mode Control

Figure 44. UCD8x20 Configured in Voltage Mode

Control with an Internal Timing Capacitor

When the ISET resistor is configured as shown in

Figure 44 with the ISET resistor connected between

the ISET pin and the 3V3 pin, the device is set-up for voltage mode control. For purposes of voltage loop compensation the, voltage ramp is 1.4 V from the valley to the peak. See Equation 1 for selecting the proper resistance for a desired clock frequency.

Where:

fclk = Desired Clock Frequency in Hz.

Figure 45 shows the nominal value of resistance to

use for a desired clock frequency. Note that for the

UCD8220 and the UCD8620 controllers, which have

two outputs controlled by Push-Pull logic, the output

ripple frequency is equal to the clock frequency; and

each output switches at half the clock frequency.

Selecting the ISET Resistor for Voltage Mode

Control with Voltage Feed forward

Figure 46. UCD8x20 Configured in Voltage Mode

Control with Voltage Feed Forward

When the ISET resistor is configured as shown in

(1)

Figure 46 with the ISET resistor connected between

the ISET pin and the input voltage, VIN, the device is

configured for voltage mode control with voltage feed

forward. For the purposes of voltage loop compen-

sation, the voltage ramp is 1.4 x Vin/Vin_max Volts

from the valley to the peak. See Equation 2 for

selecting the proper resistance for a desired clock

frequency and input voltage range.

Figure 45. ISET Resistance vs Clock Frequency

(2)

Where:

fclk = Desired Clock Frequency in Hz.

For a general discussion of the benefits of Voltage

Mode Control with Voltage feed forward, see Refer-

ence [5].

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(9)

3V3

OUT

ON OFF

CTRL

(6)

ISET

(4)

R_ISET

PWM

0.25 V

C 12 pF

int

I_SC = 1.85 / (11 x R_ISET)

TO CLEAR

PWM LATCH

11 x R_ISET x 12

V/ sm

1.85 x 10

SLOPE =

0.01

0.1

100

1 k

10 k

1 k

10 k 100 k

1 M

101100

R_ISET Resistance - W

Slope - V/ sm

UCD8220, UCD8620

SLUS652B – MARCH 2005 – REVISED SEPTEMBER 2005

Selecting the ISET Resistor for Peak Current Mode Control with Internal Slope Compensation

Figure 47. UCCD8x20 Configured in Peak Current

Control with Internal Slope Compensation

When the ISET resistor is configured as shown in

Figure 47 with the ISET resistor connected between

the ISET pin and AGND, the device is configured for peak current mode control with internal slope compensation. The voltage at the ISET pin is 1.85 volts so the internal slope compensation current, I_SC, being fed into the internal slope compensation capacitor is equal to 1.85 / (11x R_ISET). The voltage slope at the PWM comparator input which is generated by this current is equal to:

The amount of slope compensation required depends

on the design of the power stage and the output

specifications. A general rule is to add an up-slope

equal to the down slope of the output inductor.

Handshaking

The UCD8K family of devices have a built-in hand-

shaking feature to facilitate efficient start-up of the

digitally managed power supply. At start-up the CLF

flag is held high until all the internal and external

supply voltages of the UCD8K device are within their

operating range. Once the supply voltages are within

acceptable limits, the CLF goes low and the device

processes the CLK signals. The digital controller

should monitor the CFL flag at start-up and wait for

the CLF flag to go LOW before sending CLK pulses

to the UCD8K device.

Driver Output

The high-current output stage of the UCD8K device

family is capable of supplying ±4-A peak current

pulses and swings to both PVDD and PGND.

The drive output uses the Texas Instruments

TrueDrive™ architecture, which delivers rated current

into the gate of a MOSFET when it is most needed,

during the Miller plateau region of the switching

transition providing efficiency gains.

TrueDrive™ consists of pull-up/pull-down circuits with

bipolar and MOSFET transistors in parallel. The peak

output current rating is the combined current from the

bipolar and MOSFET transistors. This hybrid output

stage also allows efficient current sourcing at low

(3)

supply voltages.

Figure 48. Slope vs RISET Resistance

Source/Sink Capabilities During Miller Plateau

Large power MOSFETs present a large load to the

control circuitry. Proper drive is required for efficient,

reliable operation. The UCD8K drivers have been

optimized to provide maximum drive to a power

MOSFET during the Miller plateau region of the

switching transition. This interval occurs while the

drain voltage is swinging between the voltage levels

dictated by the power topology, requiring the charg-

ing/discharging of the drain-gate capacitance with

current supplied or removed by the driver device. See

Reference [2].

Drive Current and Power Requirements

The UCD8620 family of controllers contains drivers

which can deliver high current into a MOSFET gate

for a period of several hundred nanoseconds.

High-peak current is required to turn on a MOSFET.

Then, to turn off a MOSFET, the driver is required to

sink a similar amount of current to ground. This

repeats at the operating frequency of the power

device.

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E =

x CV

P = CV x 1

P = 2.2 nF x 12 x 300 kHz = 0.095 W

I =

0.095 W

12 V

= 7.9 mA

UCD8220, UCD8620

SLUS652B – MARCH 2005 – REVISED SEPTEMBER 2005

Reference [2] discusses the current required to drive ture range the package must allow for the efficient a power MOSFET and other capacitive-input removal of the heat produced while keeping the switching devices. junction temperature within rated limits. The UCD8K

When a driver device is tested with a discrete, capacitive load it is a fairly simple matter to calculate the power that is required from the bias supply. The energy that must be transferred from the bias supply to charge the capacitor is given by:

where C is the load capacitor and V is the bias voltage feeding the driver.

There is an equal amount of energy transferred to ground when the capacitor is discharged. This leads to a power loss given by the following:

where f is the switching frequency. This power is dissipated in the resistive elements of

the circuit. Thus, with no external resistor between the driver and gate, this power is dissipated inside the driver. Half of the total power is dissipated when the capacitor is charged, and the other half is dissipated when the capacitor is discharged.

With V

= 12 V, C

= 2.2 nF, and f = 300 kHz,

LOAD

the power loss can be calculated as:

With a 12-V supply, this would equate to a current of:

Thermal Information

The useful range of a driver is greatly affected by the drive power requirements of the load and the thermal characteristics of the device package. In order for a power driver to be useful over a particular tempera-

(4)

(5)

(6)

(7)

family of drivers is available in PowerPAD™ TSSOP

and QFN/DFN packages to cover a range of appli-

cation requirements. Both have an exposed pad to

enhance thermal conductivity from the semiconductor

junction.

As illustrated in Reference [3], the PowerPAD™

packages offer a leadframe die pad that is exposed at

the base of the package. This pad is soldered to the

copper on the PC board (PCB) directly underneath

the device package, reducing the θ

down to

37.47°C/W. The PC board must be designed with

thermal lands and thermal vias to complete the heat

removal subsystem, as summarized in Reference [4].

Note that the PowerPAD™ is not directly connected

to any leads of the package. However, it is electrically

and thermally connected to the substrate which is the

ground of the device. The PowerPAD™ should be

connected to the quiet ground of the circuit.

Circuit Layout Recommendations

In a MOSFET driver operating at high frequency, it is

critical to minimize stray inductance to minimize

overshoot/undershoot and ringing. The low output

impedance of the drivers produces waveforms with

high di/dt. This tends to induce ringing in the parasitic

inductances. It is advantageous to connect the driver

device close to the MOSFETs. It is recommended

that the PGND and the AGND pins be connected to

the PowerPAD™ of the package with a thin trace. It

is critical to ensure that the voltage potential between

these two pins does not exceed 0.3 V. The use of

schottky diodes on the outputs to PGND and PVDD is

recommended when driving gate transformers.

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UCD8220, UCD8620

SLUS652B – MARCH 2005 – REVISED SEPTEMBER 2005

REFERENCES

1. Power Supply Seminar SEM-1600 Topic 6: A Practical Introduction to Digital Power Supply Control, by Laszlo Balogh, Texas Instruments Literature No. SLUP224

2. Power Supply Seminar SEM–1400 Topic 2: Design And Application Guide For High Speed MOSFET Gate Drive Circuits, by Laszlo Balogh, Texas Instruments Literature No. SLUP133.

3. Technical Brief, PowerPad Thermally Enhanced Package, Texas Instruments Literature No. SLMA002

4. Application Brief, PowerPAD™ Made Easy, Texas Instruments Literature No. SLMA004

5. Power Supply Seminar SEM-300 Topic 2, "Closing the Feedback Loop", by Lloyd Dixon Jr., Texas Instruments, (Literature Number SLUP068)

TEXAS INSTRUMENTS UCD8220, UCD8620 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual