Texas Instruments UCD7100, UCD7100RGYR Datasheet

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FEATURES DESCRIPTION

APPLICATIONS

TYPICAL APPLICATION DIAGRAMS

OUT

3V3

AGND

CLF

ILIM

UCD7100PWP

Bias

Winding

VIN

VOUT

VDD

Isolation

Amplifier

PWMB

INT

Digital Controller

PWMA

VDD

AN2

AN3

AN1

AGND

Communication

UCD7100

SLUS651A – MARCH 2005 – REVISED MAY 2005

Digital Control Compatible Single Low-Side ± 4-A MOSFET Driver with Current Sense

• Adjustable Current Limit Protection

The UCD7100 is a member of the UCD7K family of digital control compatible drivers for applications

• 3.3-V, 10-mA Internal Regulator

utilizing digital control techniques or applications re-

• DSP/µC Compatible Inputs

quiring fast local peak current limit protection.

• Single ± 4-A TrueDrive™ High Current Driver The UCD7100 is a low-side ± 4-A high-current

• 10-ns Typical Rise and Fall Times with 2.2-nF

MOSFET gate driver. It allows the digital power

Loads

controllers such as UCD9110 or UCD9501 to

• 25-ns Input-to-Output Propagation Delay

interface to the power stage in single ended topologies. It provides a cycle-by-cycle current limit

• 25-ns Current Sense to Output Delay

function with programmable threshold and a digital

• Programmable Current Limit Threshold

output current limit flag which can be monitored by

• Digital Output Current Limit Flag

the host controller. With a fast 25-ns cycle-by-cycle current limit protection, the driver can turn off the

• 4.5-V to 15-V Supply Voltage Range

power stage in the unlikely event that the digital

• Rated from -40 ° C to 105 ° C

system can not respond to a failure situation in time.

• Lead(Pb)-Free Packaging

For fast switching speeds, the UCD7100 output stage uses the TrueDrive™ output architecture, which delivers rated current of ± 4 A into the gate of a

• Digitally Controlled Power Supplies

MOSFET during the Miller plateau region of the

• DC/DC Converters

switching transition. It also includes a 3.3-V, 10-mA

• Motor Controllers linear regulator to provide power to the digital control- ler.

• Line Drivers

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

TrueDrive, PowerPAD are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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DESCRIPTION (CONT.)

CONNECTION DIAGRAMS

1 2 3 4 5 6 7

14 13 12 11 10

9 8

PWP−14 PACKAGE

(TOP VIEW)

NC − No internal connection

VDD

3V3

AGND

CLF ILIM

PVDD PVDD OUT OUT PGND PGND CS

VDD

PVDD

OUT

PGND

RGY−14 PACKAGE

(BOTTOM VIEW)

1 7

3V3

AGND

CLF

ILIM

1321231141059

14 8

CSPVDD

UCD7100

SLUS651A – MARCH 2005 – REVISED MAY 2005

The UCD7K driver family is compatible with standard 3.3 volt I/O ports of DSPs, Microcontrollers, or ASICs. UCD7100 is offered in PowerPAD™ HTSSOP-14 or space-saving QFN-14 packages.

ORDERING INFORMATION

Packaged Devices

(1) (2) (3)

Temperature Range 110-V HV Startup Circuit

PowerPAD™ HTSSOP-14

QFN-14 (RGY)

(PWP)

-40 ° C to 105 ° C No UCD7100PWP UCD7100RGYT

(1) HTSSOP-14 (PWP) and QFN-14 (RGY) packages are available taped and reeled. Add R suffix to device type (e.g. UCD7100PWPR) to

order quantities of 2,000 devices per reel for the PWP package and 1,000 devices per reel for the RGY packages. Standard pack quantity for the UCD7100RGYT is 250 devices.

(2) These products are packaged in Pb-Free and Green lead finish of Pd-Ni-Au which is compatible with MSL level 1 at 255 ° C to 260 ° C

peak reflow temperature to be compatible with either lead free or Sn/Pb soldering operations.

(3) QFN packaging is not yet available.

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ABSOLUTE MAXIMUM RATINGS

(1) (2)

RECOMMENDED OPERATING CONDITIONS

UCD7100

SLUS651A – MARCH 2005 – REVISED MAY 2005

SYMBOL PARAMETER UCD7100 UNIT

Supply Voltage 16

Quiescent 20

Supply Current mA

Switching, TA= 25 ° C, TJ= 125 ° C, V

= 12 V 200

Output Gate Drive Volt-

OUT

OUT -1 V to VDD V

age

OUT(sink)

4.0

Output Gate Drive Cur-

OUT A

rent

OUT(source)

-4.0

ISET, CS -0.3 to 3.6

Analog Input

ILIM -0.3 to 3.6 V Digital I/O’s IN, CLF -0.3 to 3.6 Power Dissipation TA= 25 ° C, TJ= 125 ° C, (PWP-14) 2.67 W

Junction Operating Temperature -55 to 150

° C

str

Storage Temperature -65 to 150

HBM Human body model 2000

ESD Rating V

CDM Change device model 500 T

SOL

Lead Temperature (Soldering, 10 sec) +300 ° C

(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to GND. Currents are positive into, negative out of the specified terminal.

PARAMETER MIN TYP MAX UNIT

Supply Voltage, VDD 4.25 12 14.5 V Supply bypass capacitance 1

µF

Reference bypass capacitance 0.22 Operating junction temperature -40 105 ° C

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ELECTRICAL CHARACTERISTICS

UCD7100

SLUS651A – MARCH 2005 – REVISED MAY 2005

= 12 V, 4.7-µF capacitor from V

to GND, TA= TJ= -40 ° C to 105 ° C, (unless otherwise noted).

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SUPPLY SECTION

Supply current, OFF V

= 4.2 V 200 400 µA

Supply current Outputs not switching IN = LOW 1.5 2.5 mA

LOW VOLTAGE UNDER-VOLTAGE LOCKOUT

VDD UVLO ON 4.25 4.5 4.75

VDD UVLO OFF 4.05 4.25 4.45 VDD UVLO hysteresis 150 250 350 mV

REFERENCE / EXTERNAL BIAS SUPPLY

3V3 initial set point TA= 25 ° C 3.267 3.3 3.333

3V3 over temperature 3.234 3.3 3.366 3V3 load regulation I

LOAD

= 1 mA to 10 mA, VDD = 5 V 1 6.6

3V3 line regulation VDD = 4.75 V to 12 V, I

LOAD

= 10 mA 1 6.6 Short circuit current VDD = 4.75 to 12 V 11 20 35 mA 3V3 OK threshold, ON 3.3 V rising 2.9 3.0 3.1

3V3 OK threshold, OFF 3.3 V falling 2.7 2.8 2.9

INPUT SIGNAL

HIGH, positive-going input threshold

1.65 2.08

voltage (VIT+) LOW negative-going input threshold

1.16 1.5 V

voltage (VIT-) Input voltage hysteresis, (VIT+ -

0.6 0.8

VIT-) Frequency 2 MHz

CURRENT LIMIT (ILIM)

ILIM internal current limit threshold ILIM = OPEN 0.466 0.50 0.536 V ILIM maximum current limit threshold I

LIM

= 3.3 V 0.975 1.025 1.075

ILIM current limit threshold I

LIM

= 0.75 V 0.700 0.725 0.750

ILIM minimum current limit threshold I

LIM

= 0.25 V 0.21 0.23 0.25 mV

CLF output high level CS > I

LIM

, I

LOAD

= -7 mA 2.64

CLF output low level CS ≤ I

LIM

, I

LOAD

= 7 mA 0.66

Propagation delay from IN to CLF IN rising to CLF falling after a current limit event 10 20 ns

CURRENT SENSE COMPARATOR

Bias voltage Includes CS comp offset 5 25 50 mV Input bias current –1 uA Propagation delay from CS to OUTx I

LIM

= 0.5 V, measured on OUTx, CS = threshold + 60 mV 25 40

Propagation delay from CS to CLF I

LIM

= 0.5 V, measured on CLF, CS = threshold + 60 mV 25 50

CURRENT SENSE DISCHARGE TRANSISTOR

Discharge resistance IN = low, resistance from CS to AGND 10 35 75 Ω

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VIT−

10%

90%

INPUT

OUTPUT

VIT+

UCD7100

SLUS651A – MARCH 2005 – REVISED MAY 2005

ELECTRICAL CHARACTERISTICS (continued)

= 12 V, 4.7-µF capacitor from V

to GND, TA= TJ= -40 ° C to 105 ° C, (unless otherwise noted).

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

OUTPUT DRIVERS

Source current

(1)

= 12 V, IN = high, OUT = 5 V 4

Sink current

(1)

= 12 V, IN = low, OUT = 5 V 4

Source current

(1)

= 4.75 V, IN = high, OUT = 0 2

Sink current

(1)

= 4.75 V, IN = low, OUT = 4.75 V 3

Rise time, t

(1)

LOAD

= 2.2 nF, V

= 12 V 10 20

Fall time, t

(1)

LOAD

= 2.2 nF, V

= 12 V 10 15

Output with V

< UVLO V

= 1.0 V, I

SINK

= 10 mA 0.8 1.2 V

Propagation delay from IN to OUTx,

LOAD

= 2.2 nF, V

= 12 V, CLK rising 20 35 ns

(1) Ensured by design. Not 100% tested in production.

NOTE:

The 10% and 90% thresholds depict the dynamics of the bipolar output devices that dominate the power MOSFET transition through the Miller regions of operation.

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FUNCTIONAL BLOCK DIAGRAM

3V3 Regulator

Reference

UVLO

PVDD

N/C

3V3

AGND

CLF

ILIM

OUT

PGND

PVDD

VDD

25 mV

SDQ

Q R

UCD7100

SLUS651A – MARCH 2005 – REVISED MAY 2005

Figure 1. UCD7100

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TERMINAL FUNCTIONS

UCD7100

SLUS651A – MARCH 2005 – REVISED MAY 2005

UCD7100

I/O FUNCTION

HTSSOP DFN-14

NAME

-14 PIN # PIN #

Supply input pin to power the driver. The UCD7K devices accept an input range of 4.25 V to

1 1 VDD I

15 V. Bypass the pin with at least 4.7 µF of capacitance. The IN pin is a high impedance digital input capable of accepting 3.3-V logic level signals up

2 2 IN I to 2 MHz. There is an internal Schmitt trigger comparator which isolates the internal circuitry

from any external noise. Regulated 3.3-V rail. The onboard linear voltage regulator is capable of sourcing up to 10 mA

3 3 3V3 O

of current. Place 0.22-µF of ceramic capacitance from the pin to ground.

4 4 AGND - Analog ground return.

Current limit flag. When the CS level is greater than the ILIM voltage minus 25 mV, the output

5 5 CLF O of the driver is forced low and the current limit flag (CLF) is set high. The CLF signal is

latched high until the UCD7K device receives the next rising edge on the IN pin. Current limit threshold set pin. The current limit threshold can be set to any value between

6 6 ILIM I

0.25 V and 1.0 V.

7 7 NC - No Connection.

Current sense pin. Fast current limit comparator connected to the CS pin is used to protect

8 8 CS I

the power stage by implementing cycle-by-cycle current limiting. Power ground return. Connect the two PGNDs together. These ground pins should be

9 9 PGND -

connected very closely to the source of the power MOSFET. Power ground return. Connect the two PGNDs together. These ground pins should be

10 10 PGND -

connected very closely to the source of the power MOSFET. 11 11 OUT O The high-current TrueDrive™ driver output. Connect the two OUT pins together. 12 12 OUT O The high-current TrueDrive™ driver output. Connect the two OUT pins together.

Supply pin provides power for the output drivers. It is not connected internally to the VDD

13 13 PVDD I

supply rail. Connect the two PVDD pins together.

Supply pin provides power for the output drivers. It is not connected internally to the VDD

14 14 PVDD I

supply rail. Connect the two PVDD pins together.

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APPLICATION INFORMATION

Supply

Current Sensing and Protection

Reference / External Bias Supply

Input

UCD7100

SLUS651A – MARCH 2005 – REVISED MAY 2005

The UCD7100 is part of a family of digital compatible If limiting the rise or fall times to the power device is drivers targeting applications utilizing digital control desired, then an external resistance can be added techniques or applications that require local fast peak between the output of the driver and the load device, current limit protection. which is generally a power MOSFET gate. The

external resistor may also help remove power dissipation from the package.

The UCD7K devices accept an input range of 4.5 V to 15 V. The device has an internal precision linear regulator that produces the 3V3 output from this VDD A very fast current limit comparator connected to the input. A separate pin, PVDD, not connected internally CS pin is used to protect the power stage by to the VDD supply rail provides power for the output implementing cycle-by-cycle current limiting. drivers. In all applications the same bus voltage

The current limit threshold is equal to the lesser of

supplies the two pins. It is recommended that a low

the positive inputs at the current limit comparator.

value of resistance be placed between the two pins

The current limit threshold can be set to any value

so that the local capacitance on each pin forms low

between 0.25 V and 1.0 V by applying the desired

pass filters to attenuate any switching noise that may

threshold voltage to the current limit (ILIM) pin. When

be on the bus.

the CS level is greater than the ILIM voltage minus Although quiescent VDD current is low, total supply 25 mV, the output of the driver is forced low and the current will be higher, depending on the gate drive current limit flag (CLF) is set high. The CLF signal is output current required by the switching frequency. latched high until the UCD7K device receives the Total V

current is the sum of quiescent V

current next rising edge on the IN pin.

and the average OUT current. Knowing the operating

When the CS voltage is below ILIM, the driver output

frequency and the MOSFET gate charge (Q

), aver-

will follow the PWM input. The CLF digital output flag

age OUT current can be calculated from:

can be monitored by the host controller to determine I

OUT

= Q

x f, where f is frequency. when a current limit event occurs and to then apply

the appropriate algorithm to obtain the desired current For high-speed circuit performance, a V

bypass

limit profile. capacitor is recommended to prevent noise problems.

A 4.7-µF ceramic capacitor should be located close to One of the main benefits of this local protection the V

to ground connection. A larger capacitor with feature is that the UCD7K devices can protect the relatively low ESR should be connected to the PVDD power stage if the software code in the digital pin, to help deliver the high current peaks to the load. controller becomes corrupted and hangs up. If the The capacitors should present a low impedance controller’s PWM output stays high, the local current characteristic for the expected current levels in the sense circuit will turn off the driver output when an driver application. The use of surface mount over-current condition occurs. The system would components for all bypass capacitors is highly rec- likely go into a retry mode because; most DSP and ommended. microcontrollers have on-board watchdog, brown-out,

and other supervisory peripherals to restart the device in the event that it is not operating properly. But these peripherals typically do not react fast enough to

All devices in the UCD7K family are capable of

save the power stage. The UCD7K’s local current

supplying a regulated 3.3-V rail to power various

limit comparator provides the required fast protection

types of external loads such as a microcontroller or

for the power stage.

an ASIC. The onboard linear voltage regulator is capable of sourcing up to 10 mA of current. For The CS threshold is 25 mV below the ILIM voltage. normal operation, place a minimum of 0.22 µF of This way, if the user attempts to command zero ceramic capacitance from the reference pin to current (I

LIM

< 25 mV) while the CS pin is at ground,

ground. for example at start-up, the CLF flag latches high until

the IN pin receives a pulse. At start-up it is necessary to ensure that the ILIM pin always greater than the CS pin for the handshaking to work as described

The IN pin is a high impedance digital input capable

below. If for any reason the CS pin comes to within

of accepting 3.3-V logic level signals up to 2 MHz.

25 mV of the ILIM pin during start-up, then the CLF

There is an internal Schmitt Trigger comparator which isolates the internal circuitry from any external noise.

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