Texas Instruments UCD3138 Technical Reference Manual

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UCD3138 Digital Power Supply Controller

Technical Reference Manual

Literature Number: SNIU028A

February 2016–Revised April 2016

Contents

1 Introduction....................................................................................................................... 30

1.1 Scope of This Document.................................................................................................. 30

1.2 A Guide to Other Documentation for all Members of UCD3138 Family of Products.............................. 30

2 Digital Pulse Width Modulator (DPWM) ................................................................................. 33

2.1 DPWM Block Diagram..................................................................................................... 35

2.2 Introduction to DPWM (DPWM Multi-Mode, Open Loop)............................................................. 37

2.3 DPWM Normal Mode ...................................................................................................... 39

2.4 DPWM Phase Shift Mode................................................................................................. 41

2.5 DPWM Multiple Output Mode (Multi Mode)............................................................................. 42

2.6 DPWM Resonant Mode ................................................................................................... 43

2.7 Triangular Mode ............................................................................................................ 45

2.8 DPWM Leading Edge Mode .............................................................................................. 46

2.9 Sync FET Ramp and IDE Calculation ................................................................................... 47

2.10 Automatic Mode Switching................................................................................................ 48

2.10.1 Resonant LLC Example......................................................................................... 48

2.10.2 Mechanism for Automatic Mode Switching ................................................................... 48

2.11 DPWMC, Edge Generation, IntraMax ................................................................................... 50

2.12 Time Resolution of Various DPWM Registers.......................................................................... 51

2.13 PWM Counter and Clocks................................................................................................. 53

2.14 DPWM Registers - Overview ............................................................................................. 53

2.15 DPWM Control Register 0 (DPWMCTRL0)............................................................................. 53

2.15.1 DPWM Auto Config Mid and Max Registers.................................................................. 53

2.15.2 Intra Mux .......................................................................................................... 53

2.15.3 Cycle by Cycle Current Limit Enable .......................................................................... 54

2.15.4 Multi Mode On/Off................................................................................................ 56

2.15.5 Minimum Duty Mode............................................................................................. 56

2.15.6 Master Sync Control Select..................................................................................... 58

2.15.7 Master Sync Slave Enable...................................................................................... 58

2.15.8 D Enable........................................................................................................... 58

2.15.9 Resonant Mode Fixed Duty Enable............................................................................ 58

2.15.10 DPWM A and B Fault Priority................................................................................. 58

2.15.11 Blank Enable .................................................................................................... 59

2.15.12 DPWM Mode .................................................................................................... 59

2.15.13 DPWM Invert .................................................................................................... 59

2.15.14 1.15.14 Filter Enable (CLA_EN) .............................................................................. 59

2.15.15 DPWM Enable .................................................................................................. 59

2.16 DPWM Control Register 1................................................................................................. 59

2.16.1 Period Counter Preset Enable.................................................................................. 59

2.16.2 Sync FET Ramp Enable......................................................................................... 60

2.16.3 Burst Mode Enable............................................................................................... 60

2.16.4 Current/Flux Balancing Duty Adjust............................................................................ 60

2.16.5 1.16.5 Sync Out Divisor Selection ............................................................................. 60

2.16.6 FIlter Scale ........................................................................................................ 60

2.16.7 External Sync Enable............................................................................................ 60

2.16.8 Cycle By Cycle B Side Active Enable ......................................................................... 60

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2.17 DPWM Control Register 2................................................................................................. 62

2.18 Period and Event Registers............................................................................................... 64

2.19 Phase Trigger Registers................................................................................................... 64

2.20 Cycle Adjust Registers..................................................................................................... 64

2.21 Resonant Duty Register ................................................................................................... 64

2.22 DPWM Fault Control Register............................................................................................ 64

2.23 DPWM Overflow Register................................................................................................. 64

2.24 DPWM Interrupt Register.................................................................................................. 65

2.25 DPWM Counter Preset Register ......................................................................................... 65

2.26 Blanking Registers ......................................................................................................... 65

2.27 DPWM Adaptive Sample Register ....................................................................................... 66

2.28 DPWM Fault Status Register ............................................................................................. 66

2.29 DPWM Auto Switch Registers............................................................................................ 66

2.30 DPWM Edge PWM Generation Register................................................................................ 66

2.31 DPWM 0-3 Registers Reference......................................................................................... 66

2.16.9 Auto Mode Switching Enable................................................................................... 60

2.16.10 1.16.10 Event Update Select.................................................................................. 61

2.16.11 Check Override ................................................................................................. 61

2.16.12 Global Period Enable........................................................................................... 61

2.16.13 Using DPWM Pins as General Purpose I/O................................................................. 61

2.16.14 High Resolution enable/disable............................................................................... 62

2.16.15 Asynchronous Protection Disable ............................................................................ 62

2.16.16 Single Frame Enable........................................................................................... 62

2.17.1 External Synchronization Input Divide Ratio.................................................................. 62

2.17.2 Resonant Deadtime Compensation Enable .................................................................. 62

2.17.3 Filter Duty Select................................................................................................. 63

2.17.4 IDeal Diode Emulation (IDE) Enable for PWMB ............................................................. 63

2.17.5 Sample Trigger 1 Oversampling ............................................................................... 63

2.17.6 Sample Trigger 1 Mode ......................................................................................... 63

2.17.7 Sample Trigger Enable Bits..................................................................................... 64

2.24.1 DPWM Period Interrupt Bits .................................................................................... 65

2.24.2 Mode Switching Interrupt Bits .................................................................................. 65

2.24.3 INT Bit ............................................................................................................. 65

2.31.1 DPWM Control Register 0 (DPWMCTRL0)................................................................... 66

2.31.2 DPWM Control Register 1 (DPWMCTRL1)................................................................... 70

2.31.3 DPWM Control Register 2 (DPWMCTRL2)................................................................... 73

2.31.4 DPWM Period Register (DPWMPRD)......................................................................... 75

2.31.5 DPWM Event 1 Register (DPWMEV1) ........................................................................ 76

2.31.6 DPWM Event 2 Register (DPWMEV2) ........................................................................ 77

2.31.7 DPWM Event 3 Register (DPWMEV3) ........................................................................ 78

2.31.8 DPWM Event 4 Register (DPWMEV4) ........................................................................ 79

2.31.9 DPWM Sample Trigger 1 Register (DPWMSAMPTRIG1).................................................. 80

2.31.10 DPWM Sample Trigger 2 Register (DPWMSAMPTRIG2) ................................................ 81

2.31.11 DPWM Phase Trigger Register (DPWMPHASETRIG) .................................................... 82

2.31.12 DPWM Cycle Adjust A Register (DPWMCYCADJA)....................................................... 83

2.31.13 DPWM Cycle Adjust B Register (DPWMCYCADJB)....................................................... 84

2.31.14 DPWM Resonant Duty Register (DPWMRESDUTY) ...................................................... 85

2.31.15 DPWM Fault Control Register (DPWMFLTCTRL) ......................................................... 86

2.31.16 DPWM Overflow Register (DPWMOVERFLOW)........................................................... 87

2.31.17 DPWM Interrupt Register (DPWMINT) ...................................................................... 88

2.31.18 DPWM Counter Preset Register (DPWMCNTPRE)........................................................ 90

2.31.19 DPWM Blanking A Begin Register (DPWMBLKABEG).................................................... 91

2.31.20 DPWM Blanking A End Register (DPWMBLKAEND)...................................................... 92

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2.31.21 DPWM Blanking B Begin Register (DPWMBLKBBEG).................................................... 93

2.31.22 DPWM Blanking B End Register (DPWMBLKBEND)...................................................... 94

2.31.23 DPWM Minimum Duty Cycle High Register (DPWMMINDUTYHI)....................................... 95

2.31.24 DPWM Minimum Duty Cycle Low Register (DPWMMINDUTYLO) ...................................... 96

2.31.25 DPWM Adaptive Sample Register (DPWMADAPTIVE) ................................................... 97

2.31.26 DPWM Fault Status (DPWMFLTSTAT)...................................................................... 98

2.31.27 DPWM Auto Switch High Upper Thresh Register (DPWMAUTOSWHIUPTHRESH) ................. 99

2.31.28 DPWM Auto Switch High Lower Thresh Register (DPWMAUTOSWHILOWTHRESH).............. 100

2.31.29 DPWM Auto Switch Low Upper Thresh Register (DPWMAUTOSWLOUPTHRESH)................ 101

2.31.30 DPWM Auto Switch Low Lower Thresh Register (DPWMAUTOSWLOLOWTHRESH) ............. 102

2.31.31 DPWM Auto Config Max Register (DPWMAUTOMAX).................................................. 103

2.31.32 DPWM Auto Config Mid Register (DPWMAUTOMID).................................................... 105

2.31.33 DPWM Edge PWM Generation Control Register (DPWMEDGEGEN) ................................ 107

2.31.34 DPWM Filter Duty Read Register (DPWMFILTERDUTYREAD)........................................ 109

2.31.35 DPWM BIST Status Register (DPWMBISTSTAT) ........................................................ 110

3 Front End......................................................................................................................... 111

3.1 Error ADC and Front End Gain ......................................................................................... 113

3.1.1 Front End Gain................................................................................................... 113

3.1.2 EADC Error Output .............................................................................................. 113

3.1.3 EADC Triggering, EADC Output to Filter ..................................................................... 115

3.1.4 EADC Timing..................................................................................................... 115

3.1.5 EADC Averaging................................................................................................. 116

3.1.6 Enabling EADC and Front End ................................................................................ 117

3.2 Front End DAC............................................................................................................ 118

3.3 Ramp Module ............................................................................................................. 119

3.3.1 DAC Ramp Overview............................................................................................ 119

3.3.2 DAC Ramp Start and End Points.............................................................................. 119

3.3.3 DAC Ramp Steps................................................................................................ 120

3.3.4 DAC Ramp Start, Interrupts, Start Delay ..................................................................... 121

3.3.5 RAMPSTAT Register............................................................................................ 121

3.3.6 DAC RAMP when EADC is Saturated ........................................................................ 121

3.3.7 Using Ramp Module for Peak Current Mode ................................................................ 121

3.3.8 Sync FET Soft On/Off using Ramp Module.................................................................. 122

3.4 Successive Approximation Mode ....................................................................................... 123

3.4.1 SAR Control Parameters ....................................................................................... 123

3.4.2 SAR Algorithm Overview ....................................................................................... 123

3.4.3 Non-Continuous SAR Mode.................................................................................... 123

3.4.4 Continuous SAR Mode.......................................................................................... 123

3.5 Absolute Value Without SAR............................................................................................ 124

3.6 EADC Modes.............................................................................................................. 124

3.7 Front End Control Registers............................................................................................. 124

3.7.1 Ramp Control Register (RAMPCTRL) ....................................................................... 124

3.7.2 Ramp Status Register (RAMPSTAT) ......................................................................... 126

3.7.3 Ramp Cycle Register (RAMPCYCLE) ........................................................................ 127

3.7.4 EADC DAC Value Register (EADCDAC)..................................................................... 128

3.7.5 Ramp DAC Ending Value Register (RAMPDACEND) ...................................................... 129

3.7.6 DAC Step Register (DACSTEP)............................................................................... 130

3.7.7 DAC Saturation Step Register (DACSATSTEP)............................................................. 131

3.7.8 EADC Trim Register (EADCTRIM) – (For Factory Test Use Only) ....................................... 132

3.7.9 EADC Control Register (EADCCTRL) ........................................................................ 133

3.7.10 Analog Control Register (ACTRL) (For Test Use Only) ................................................... 135

3.7.11 Pre-Bias Control Register 0 (PREBIASCTRL0) ............................................................ 136

3.7.12 Pre-Bias Control Register 1 (PREBIASCTRL1) ............................................................ 137

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3.7.13 SAR Control Register (SARCTRL) ........................................................................... 138

3.7.14 SAR Timing Register (SARTIMING) ......................................................................... 139

3.7.15 EADC Value Register (EADCVALUE) ....................................................................... 140

3.7.16 EADC Raw Value Register (EADCRAWVALUE)........................................................... 141

3.7.17 DAC Status Register (DACSTAT)............................................................................ 142

4 Filter ............................................................................................................................... 143

4.1 Filter Math Details ........................................................................................................ 144

4.1.1 Filter Input and Branch Calculations .......................................................................... 144

4.1.2 Proportional Branch ............................................................................................. 145

4.1.3 Integral Branch................................................................................................... 145

4.1.4 Differential Branch ............................................................................................... 145

4.1.5 Add, Saturate, Scale and Clamp .............................................................................. 146

4.1.6 Filter Output Stage............................................................................................... 147

4.2 Filter Status Register ..................................................................................................... 148

4.3 Filter Control Register.................................................................................................... 148

4.3.1 Filter Enable ...................................................................................................... 149

4.3.2 Use CPU Sample ................................................................................................ 149

4.3.3 Force Start........................................................................................................ 149

4.3.4 Kp Off, Kd Off, Ki Off ............................................................................................ 149

4.3.5 Kd Stall, Ki Stall.................................................................................................. 149

4.3.6 Nonlinear Mode .................................................................................................. 149

4.3.7 Output Scaling.................................................................................................... 149

4.3.8 Output Multiplier Select ......................................................................................... 150

4.3.9 Switching Period as Output Multiplier......................................................................... 150

4.3.10 KComp as Output Multiplier................................................................................... 151

4.3.11 Feed Forward as Output Multiplier ........................................................................... 151

4.3.12 Period Multiplier Select ........................................................................................ 151

4.3.13 Ki Adder Mode .................................................................................................. 151

4.4 XN, YN Read and Write Registers ..................................................................................... 152

4.4.1 CPU Xn Register................................................................................................. 152

4.4.2 Filter XN Read Register......................................................................................... 152

4.4.3 Filter YN Read Registers ....................................................................................... 152

4.5 Coefficient Configuration Register...................................................................................... 153

4.6 Kp, Ki, and Kd Registers................................................................................................. 155

4.7 Alpha Registers ........................................................................................................... 155

4.8 Filter Nonlinear Limit Registers ......................................................................................... 155

4.9 Clamp Registers .......................................................................................................... 156

4.10 Filter Preset Register..................................................................................................... 156

4.11 Filter Registers Reference............................................................................................... 156

4.11.1 Filter Status Register (FILTERSTATUS) .................................................................... 156

4.11.2 Filter Control Register (FILTERCTRL)....................................................................... 158

4.11.3 CPU XN Register (CPUXN)................................................................................... 160

4.11.4 Filter XN Read Register (FILTERXNREAD) ................................................................ 161

4.11.5 Filter KI_YN Read Register (FILTERKIYNREAD).......................................................... 162

4.11.6 Filter KD_YN Read Register (FILTERKDYNREAD) ....................................................... 163

4.11.7 Filter YN Read Register (FILTERYNREAD) ................................................................ 164

4.11.8 Coefficient Configuration Register (COEFCONFIG) ....................................................... 165

4.11.9 Filter KP Coefficient 0 Register (FILTERKPCOEF0)....................................................... 168

4.11.10 Filter KP Coefficient 1 Register (FILTERKPCOEF1)..................................................... 169

4.11.11 Filter KI Coefficient 0 Register (FILTERKICOEF0) ...................................................... 170

4.11.12 Filter KI Coefficient 1 Register (FILTERKICOEF1) ....................................................... 171

4.11.13 Filter KD Coefficient 0 Register (FILTERKDCOEF0)..................................................... 172

4.11.14 Filter KD Coefficient 1 Register (FILTERKDCOEF1)..................................................... 173

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4.11.15 Filter KD Alpha Register (FILTERKDALPHA) ............................................................. 174

4.11.16 Filter Nonlinear Limit Register 0 (FILTERNL0)............................................................ 175

4.11.17 Filter Nonlinear Limit Register 1 (FILTERNL1)............................................................ 176

4.11.18 Filter Nonlinear Limit Register 2 (FILTERNL2)............................................................ 177

4.11.19 Filter KI Feedback Clamp High Register (FILTERKICLPHI) ............................................ 178

4.11.20 Filter KI Feedback Clamp Low Register (FILTERKICLPLO) ............................................ 179

4.11.21 Filter YN Clamp High Register (FILTERYNCLPHI)....................................................... 180

4.11.22 Filter YN Clamp Low Register (FILTERYNCLPLO) ...................................................... 181

4.11.23 Filter Output Clamp High Register (FILTEROCLPHI).................................................... 182

4.11.24 Filter Output Clamp Low Register (FILTEROCLPLO).................................................... 183

4.11.25 Filter Preset Register (FILTERPRESET)................................................................... 184

5 Loop Mux......................................................................................................................... 185

5.1 Front End Control Muxes (FECTRL0MUX, FECTRL1MUX, FECTRL2MUX) .................................... 187

5.2 Sample Trigger Control (SAMPTRIGCTRL)........................................................................... 187

5.3 External DAC Control (EXTDACCTRL)................................................................................ 187

5.4 Filter Mux Register (FILTERMUX)...................................................................................... 188

5.5 Filter KComp Registers (FILTERKCOMPx) ........................................................................... 188

5.6 DPWM Mux Register (DPWMMUX) ................................................................................... 188

5.7 Global Enable Register (GLBEN)....................................................................................... 188

5.8 PWM Global Period Register (PWMGLBPRD) ....................................................................... 189

5.9 Sync Control (SYNCCTRL).............................................................................................. 189

5.10 Light Load (Burst) Mode ................................................................................................. 189

5.11 Constant Current / Constant Power .................................................................................... 189

5.12 Analog Peak Current Mode.............................................................................................. 190

5.13 Automatic Cycle Adjustment ............................................................................................ 190

5.13.1 Calculation....................................................................................................... 190

5.13.2 Configuration .................................................................................................... 191

5.13.3 Scaling ........................................................................................................... 191

5.14 Loop Mux Registers Reference......................................................................................... 191

5.14.1 Front End Control 0 Mux Register (FECTRL0MUX) ....................................................... 191

5.14.2 Front End Control 1 Mux Register (FECTRL1MUX) ....................................................... 193

5.14.3 Front End Control 2 Mux Register (FECTRL2MUX) ....................................................... 195

5.14.4 Sample Trigger Control Register (SAMPTRIGCTRL)...................................................... 197

5.14.5 External DAC Control Register (EXTDACCTRL) .......................................................... 198

5.14.6 Filter Mux Register (FILTERMUX) ........................................................................... 199

5.14.7 Filter KComp A Register (FILTERKCOMPA) ............................................................... 201

5.14.8 Filter KComp B Register (FILTERKCOMPB) ............................................................... 202

5.14.9 DPWM Mux Register (DPWMMUX) ......................................................................... 203

5.14.10 Constant Power Control Register (CPCTRL) ............................................................. 205

5.14.11 Constant Power Nominal Threshold Register (CPNOM) ................................................ 207

5.14.12 Constant Power Max Threshold Register (CPMAX) ..................................................... 208

5.14.13 Constant Power Configuration Register (CPCONFIG) .................................................. 209

5.14.14 Constant Power Max Power Register (CPMAXPWR) ................................................... 210

5.14.15 Constant Power Integrator Threshold Register (CPINTTHRESH) ..................................... 211

5.14.16 Constant Power Firmware Divisor Register (CPFWDIVISOR) ......................................... 212

5.14.17 Constant Power Status Register (CPSTAT) .............................................................. 213

5.14.18 Cycle Adjustment Control Register (CYCADJCTRL) .................................................... 214

5.14.19 Cycle Adjustment Limit Register (CYCADJLIM) .......................................................... 215

5.14.20 Cycle Adjustment Status Register (CYCADJSTAT) ..................................................... 216

5.14.21 Global Enable Register (GLBEN) ........................................................................... 217

5.14.22 PWM Global Period Register (PWMGLBPRD)............................................................ 218

5.14.23 Sync Control Register (SYNCCTRL) ....................................................................... 219

5.14.24 Light Load Control Register (LLCTRL) ..................................................................... 220

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5.14.25 Light Load Enable Threshold Register (LLENTHRESH)................................................. 221

5.14.26 Light Load Disable Threshold Register (LLDISTHRESH) ............................................... 222

5.14.27 Peak Current Mode Control Register (PCMCTRL) ....................................................... 223

5.14.28 Analog Peak Current Mode Control Register (APCMCTRL) ............................................ 224

5.14.29 Loop Mux Test Register (LOOPMUXTEST) (Test Use Only) ........................................... 225

6 Fault Mux......................................................................................................................... 226

6.1 Analog Comparator Configuration ...................................................................................... 228

6.1.1 ACOMP_EN ...................................................................................................... 228

6.1.2 ACOMP_x_THRESH............................................................................................ 228

6.1.3 ACOMP_x_POL.................................................................................................. 228

6.1.4 ACOMP_x_INT_EN ............................................................................................. 228

6.1.5 ACOMP_x_OUT_EN............................................................................................ 228

6.1.6 ACOMP_x_SEL.................................................................................................. 228

6.1.7 ACOMP_F_REF_SEL........................................................................................... 229

6.1.8 ACOMPCTRL Register Arrangement ......................................................................... 229

6.2 Analog Comparator Ramp............................................................................................... 229

6.3 Digital Comparator Configuration....................................................................................... 229

6.4 Fault Pin Configuration................................................................................................... 230

6.5 Analog Peak Current ..................................................................................................... 230

6.6 Fault Status Registers.................................................................................................... 230

6.7 Fault Mux Control Registers............................................................................................. 230

6.8 DPWM Fault Action....................................................................................................... 231

6.9 IDE / DCM Detection Control............................................................................................ 232

6.10 Oscillator Failure Detection.............................................................................................. 234

6.10.1 High Frequency Oscillator Failure Detection................................................................ 234

6.10.2 Low Frequency Oscillator Failure Detection ................................................................ 234

6.11 Fault Mux Registers Reference......................................................................................... 234

6.11.1 Analog Comparator Control 0 Register (ACOMPCTRL0) ................................................ 234

6.11.2 Analog Comparator Control 1 Register (ACOMPCTRL1) ................................................ 237

6.11.3 Analog Comparator Control 2 Register (ACOMPCTRL2) ................................................ 239

6.11.4 Analog Comparator Control 3 Register (ACOMPCTRL3) ................................................ 241

6.11.5 External Fault Control Register (EXTFAULTCTRL) ....................................................... 242

6.11.6 Fault Mux Interrupt Status Register (FAULTMUXINTSTAT) ............................................. 243

6.11.7 Fault Mux Raw Status Register (FAULTMUXRAWSTAT) ................................................ 245

6.11.8 Comparator Ramp Control 0 Register (COMPRAMP0) .................................................. 247

6.11.9 Digital Comparator Control 0 Register (DCOMPCTRL0).................................................. 249

6.11.10 Digital Comparator Control 1 Register (DCOMPCTRL1) ................................................ 250

6.11.11 Digital Comparator Control 2 Register (DCOMPCTRL2) ................................................ 251

6.11.12 Digital Comparator Control 3 Register (DCOMPCTRL3) ................................................ 252

6.11.13 Digital Comparator Counter Status Register (DCOMPCNTSTAT) ..................................... 253

6.11.14 DPWM 0 Current Limit Control Register (DPWM0CLIM) ................................................ 254

6.11.15 DPWM 0 Fault AB Detection Register (DPWM0FLTABDET) ........................................... 256

6.11.16 DPWM 0 Fault Detection Register (DPWM0FAULTDET) ............................................... 257

6.11.17 DPWM 1 Current Limit Control Register (DPWM1CLIM) ................................................ 260

6.11.18 DPWM 1 Fault AB Detection Register (DPWM1FLTABDET) ........................................... 262

6.11.19 DPWM 1 Fault Detection Register (DPWM1FAULTDET) ............................................... 264

6.11.20 DPWM 2 Current Limit Control Register (DPWM2CLIM) ................................................ 267

6.11.21 DPWM 2 Fault AB Detection Register (DPWM2FLTABDET) ........................................... 269

6.11.22 DPWM 2 Fault Detection Register (DPWM2FAULTDET) ............................................... 271

6.11.23 DPWM 3 Current Limit Control Register (DPWM3CLIM) ................................................ 274

6.11.24 DPWM 3 Fault AB Detection Register (DPWM3FLTABDET) ........................................... 276

6.11.25 DPWM 3 Fault Detection Register (DPWM3FAULTDET) ............................................... 278

6.11.26 HFO Fail Detect Register (HFOFAILDET) ................................................................. 281

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6.11.27 LFO Fail Detect Register (LFOFAILDET).................................................................. 282

6.11.28 IDE Control Register (IDECTRL)............................................................................ 283

7 GIO Module...................................................................................................................... 284

7.1 Fault IO Direction Register (FAULTDIR)............................................................................... 285

7.2 Fault Input Register (FAULTIN)......................................................................................... 286

7.3 Fault Output Register (FAULTOUT).................................................................................... 287

7.4 Fault Interrupt Enable Register (FAULTINTENA) .................................................................... 288

7.5 Fault Interrupt Polarity Register (FAULTINTPOL).................................................................... 289

7.6 Fault Interrupt Pending Register (FAULTINTPEND)................................................................. 290

7.7 External Interrupt Direction Register (EXTINTDIR) .................................................................. 291

7.8 External Interrupt Input Register (EXTINTIN)......................................................................... 292

7.9 External Interrupt Output Register (EXTINTOUT).................................................................... 293

7.10 External Interrupt Enable Register (EXTINTENA).................................................................... 294

7.11 External Interrupt Polarity Register (EXTTINTPOL).................................................................. 295

7.12 External Interrupt Pending Register (EXTINTPEND) ................................................................ 296

7.13 References ................................................................................................................ 296

8 ADC12 Overview............................................................................................................... 297

8.1 ADC12 Input Impedance Model ........................................................................................ 299

8.2 ADC12 Impedance vs. Sampling Frequency Data ................................................................... 300

8.3 Effect of External Capacitance.......................................................................................... 301

8.4 Channel to Channel Crosstalk .......................................................................................... 301

8.5 Impedance Roll-Off Due to Crosstalk .................................................................................. 302

8.6 ADC12 Control FSM...................................................................................................... 302

8.7 Conversion................................................................................................................. 302

8.8 Sequencing................................................................................................................ 303

8.9 Digital Comparators ...................................................................................................... 304

8.10 ADC Averaging............................................................................................................ 305

8.11 Temperature Sensor ..................................................................................................... 305

8.12 Temp Sensor Control Register (TEMPSENCTRL)................................................................... 306

8.13 PMBus Addressing ....................................................................................................... 307

8.13.1 PMBus Control Register 3 (PMBCTRL3).................................................................... 307

8.14 Dual Sample and Hold................................................................................................... 308

8.14.1 ADC Control Register (ADCCTRL)........................................................................... 309

8.15 Usage of Sample and Hold Circuitry for High Impedance Measurement ......................................... 309

8.15.1 C Code Example................................................................................................ 311

8.16 ADC Configuration Examples ........................................................................................... 311

8.16.1 Software Initiated Conversions ............................................................................... 311

8.16.2 Single Sweep Operation....................................................................................... 312

8.16.3 Auto-Triggered Conversions .................................................................................. 313

8.16.4 Continuous Conversions....................................................................................... 313

8.16.5 Start/Stop Operation (External Trigger)...................................................................... 314

8.17 Useful C Language Statement Examples ............................................................................. 315

8.18 ADC Registers ............................................................................................................ 316

8.18.1 ADC Control Register (ADCCTRL) .......................................................................... 316

8.18.2 ADC Status Register (ADCSTAT) ........................................................................... 318

8.18.3 ADC Test Control Register (ADCTSTCTRL)................................................................ 319

8.18.4 ADC Sequence Select Register 0 (ADCSEQSEL0) ....................................................... 320

8.18.5 ADC Sequence Select Register 1 (ADCSEQSEL1) ....................................................... 321

8.18.6 ADC Sequence Select Register 2 (ADCSEQSEL2) ....................................................... 322

8.18.7 ADC Sequence Select Register 3 (ADCSEQSEL3) ....................................................... 323

8.18.8 ADC Result Registers 0-15 (ADCRESULTx, x=0:15)...................................................... 324

8.18.9 ADC Averaged Result Registers 0-5 (ADCAVGRESULTx, x=0:15)..................................... 325

8.18.10 ADC Digital Compare Limits Register 0-5 (ADCCOMPLIMx, x=0:5)................................... 326

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8.18.11 ADC Digital Compare Enable Register (ADCCOMPEN)................................................. 327

8.18.12 ADC Digital Compare Results Register (ADCCOMPRESULT)......................................... 329

8.18.13 ADC Averaging Control Register (ADCAVGCTRL)....................................................... 331

9 Advanced Power Management Control Functions................................................................. 333

9.1 Package ID Information .................................................................................................. 334

9.2 Brownout................................................................................................................... 334

9.3 Temperature Sensor Control ............................................................................................ 334

9.4 I/O Mux Control ........................................................................................................... 334

9.5 Current Sharing Control.................................................................................................. 334

9.6 Temperature Reference.................................................................................................. 336

9.7 Power Disable Control or (Clock Gating Control) .................................................................... 336

9.8 Miscellaneous Analog Control Registers .............................................................................. 336

9.8.1 Package ID Register (PKGID) ................................................................................. 336

9.8.2 Brownout Register (BROWNOUT) ............................................................................ 337

9.8.3 Temp Sensor Control Register (TEMPSENCTRL).......................................................... 338

9.8.4 I/O Mux Control Register (IOMUX)............................................................................ 339

9.8.5 Current Sharing Control Register (CSCTRL) ................................................................ 340

9.8.6 Temperature Reference Register (TEMPREF) .............................................................. 341

9.8.7 Power Disable Control Register (PWRDISCTRL) ........................................................... 342

9.9 GPIO Overview ........................................................................................................... 343

9.10 Interaction with a Single Pin............................................................................................. 344

9.11 Interaction with Multiple Pins............................................................................................ 345

9.12 Registers................................................................................................................... 346

9.12.1 Global I/O EN Register (GBIOEN) ........................................................................... 346

9.12.2 Global I/O OE Register (GLBIOOE).......................................................................... 347

9.12.3 Global I/O Open Drain Control Register (GLBIOOD)...................................................... 348

9.12.4 Global I/O Value Register (GLBIOVAL) ..................................................................... 349

9.12.5 Global I/O Read Register (GLBIOREAD).................................................................... 350

9.13 Trim and Test Registers - Note ......................................................................................... 351

9.13.1 Clock Trim Register (CLKTRIM) (For Factory Test Use Only, Except HFO_LN_FILTER_EN) ...... 351

10 PMBus Interface/I2C Interface ............................................................................................ 352

10.1 PMBus Register Summary .............................................................................................. 353

10.2 PMBus Slave Mode Initialization........................................................................................ 353

10.2.1 Initialization for Polling and Maximum Automatic Acknowledgement.................................... 353

10.2.2 Initialization for Interrupts and for Manual Acknowledgement ............................................ 353

10.2.3 Initialization for I2C............................................................................................. 354

10.2.4 Initialization for Advanced Features in Some Devices..................................................... 354

10.3 PMBus Slave Mode Command Examples............................................................................. 355

10.3.1 Write Command (Send Byte), No PEC ...................................................................... 355

10.3.2 Other Simple Writes with Auto Acknowledge............................................................... 357

10.3.3 Quick Command Write......................................................................................... 358

10.3.4 Writes of 4 Bytes or More With Full Auto Acknowledge................................................... 358

10.3.5 Writes with Less than 3 Bytes Auto-Acknowledged........................................................ 360

10.3.6 Manual Slave Address ACK for Write........................................................................ 360

10.3.7 Manual Command ACK........................................................................................ 361

10.3.8 Read Messages with Full Automation ....................................................................... 361

10.3.9 Simple Read of 4 Bytes with Full Automation............................................................... 362

10.3.10 Simple Read of More than 4 Bytes with Full Automation................................................ 363

10.3.11 Quick Command Read ....................................................................................... 364

10.3.12 Simple Read with Manual Slave Address ACK ........................................................... 364

10.3.13 Write/Read with Repeated Start............................................................................. 365

10.3.14 Automatic PEC Addition...................................................................................... 366

10.4 Avoiding Clock Stretching ............................................................................................... 367

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10.4.1 Using Early TXBUF Write to Avoid Clock Stretch .......................................................... 367

10.4.2 Alert Response.................................................................................................. 368

10.5 PMBus Slave Mode Low Level Timing................................................................................. 369

10.6 Effect of MAN_SLAVE_ACK bit on EOM Handling .................................................................. 371

10.7 Master Mode Operation Reference..................................................................................... 372

10.7.1 Quick Command ................................................................................................ 373

10.7.2 Send Byte........................................................................................................ 373

10.7.3 Receive Byte .................................................................................................... 373

10.7.4 Write Byte/Word ................................................................................................ 374

10.7.5 Read Byte/Read Word......................................................................................... 375

10.7.6 Process Call ..................................................................................................... 376

10.7.7 Block Write ...................................................................................................... 377

10.7.8 Block Read ...................................................................................................... 378

10.7.9 Block Write-Block Read Process Call........................................................................ 379

10.7.10 Alert Response ................................................................................................ 379

10.7.11 Extended Command - Write Byte/Word, Read Byte/Word .............................................. 380

10.7.12 Group Command.............................................................................................. 381

10.8 PMBUS Communications Fault Handling.............................................................................. 381

10.8.1 Bit Counter....................................................................................................... 381

10.8.2 Test Mode (Manufacturer Reserved Address Match)...................................................... 382

10.9 Other Functions of the PMBus Module ................................................................................ 382

10.10 PMBus Interface Registers Reference ................................................................................ 382

10.10.1 PMBUS Control Register 1 (PMBCTRL1) ................................................................. 382

10.10.2 PMBus Transmit Data Buffer (PMBTXBUF)............................................................... 384

10.10.3 PMBus Receive Data Register (PMBRXBUF) ............................................................ 385

10.10.4 PMBus Acknowledge Register (PMBACK) ................................................................ 386

10.10.5 PMBus Status Register (PMBST)........................................................................... 387

10.10.6 PMBus Interrupt Mask Register (PMBINTM) .............................................................. 389

10.10.7 PMBus Control Register 2 (PMBCTRL2) .................................................................. 390

10.10.8 PMBus Hold Slave Address Register (PMBHSA)......................................................... 392

10.10.9 PMBus Control Register 3 (PMBCTRL3) .................................................................. 393

11 Timer Module Overview..................................................................................................... 396

11.1 T24 – 24 Bit Free-Running Timer with Capture and Compare ..................................................... 397

11.2 T24 Clock Source, Prescaler and Counter ............................................................................ 397

11.3 T24 Capture Block........................................................................................................ 398

11.4 T24 Compare Blocks ..................................................................................................... 399

11.5 T24 Interrupts ............................................................................................................. 399

11.6 T16PWMx - 16 Bit PWM Timers ....................................................................................... 399

11.7 T16PWMx Summary ..................................................................................................... 399

11.8 T16PWMx Prescaler and Counter...................................................................................... 400

11.9 T16PWMx Compare Blocks ............................................................................................. 400

11.10 T16 Shadow Bit........................................................................................................... 401

11.11 T16 Interrupts ............................................................................................................. 401

11.12 Using the T16 for a Timer Interrupt .................................................................................... 402

11.13 Using the T16 for PWM Generation.................................................................................... 402

11.14 WD - Watchdog........................................................................................................... 402

11.15 Watchdog Prescale and Counter....................................................................................... 403

11.16 Watchdog Compare Blocks ............................................................................................. 403

11.17 Watchdog Protect Bit .................................................................................................... 403

11.18 Watchdog Timer Example............................................................................................... 404

11.19 Warnings for Watchdog Status Register .............................................................................. 404

11.20 System Fault Recovery Basics ......................................................................................... 404

11.21 Timer Module Register Reference ..................................................................................... 405

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11.21.1 24-bit Counter Data Register (T24CNTDAT) .............................................................. 405

11.21.2 24-bit Counter Control Register (T24CNTCTRL) ......................................................... 406

11.21.3 24-bit Capture Channel Data Register (T24CAPDAT) or (T24CAPDATx) ............................ 407

11.21.4 24-bit Capture Channel Control Register (T24CAPCTRLx or T24CAPCTRL......................... 408

11.21.5 24-bit Capture I/O Control and Data Register (T24CAPIO) ............................................. 409

11.21.6 24-bit Output Compare Channel 0 Data Register (T24CMPDAT0) .................................... 410

11.21.7 24-bit Output Compare Channel 1 Data Register (T24CMPDAT1) .................................... 411

11.21.8 24-bit Output Compare Channel 0 Control Register (T24CMPCTRL0)................................ 412

11.21.9 24-bit Output Compare Channel 1 Control Register (T24CMPCTRL1)................................ 413

11.21.10 PWMx Counter Data Register (T16PWMxCNTDAT) ................................................... 414

11.21.11 PWMx Counter Control Register (T16PWMxCNTCTRL)............................................... 415

11.21.12 PWMx 16-bit Compare Channel 0-1 Data Register (T16PWMxCMPyDAT)......................... 416

11.21.13 PWMx Compare Control Register (T16PWMxCMPCTRL)............................................. 417

11.21.14 Watchdog Status (WDST).................................................................................. 419

11.21.15 Watchdog Control (WDCTRL) ............................................................................. 420

12 UART Overview ................................................................................................................ 421

12.1 UART Frame Format ..................................................................................................... 422

12.2 Asynchronous Timing Mode............................................................................................. 422

12.3 UART Interrupts........................................................................................................... 423

12.4 Transmit Interrupt......................................................................................................... 424

12.5 Receive Interrupt.......................................................................................................... 424

12.6 Error Interrupts ............................................................................................................ 424

12.7 UART Registers Reference ............................................................................................. 426

12.7.1 UART Control Register 0 (UARTCTRL0) ................................................................... 426

12.7.2 UART Receive Status Register (UARTRXST) ............................................................. 427

12.7.3 UART Transmit Status Register (UARTTXST) ............................................................. 428

12.7.4 UART Control Register 3 (UARTCTRL3) ................................................................... 429

12.7.5 UART Interrupt Status Register (UARTINTST) ............................................................ 430

12.7.6 UART Baud Divisor High Byte Register (UARTHBAUD) ................................................. 431

12.7.7 UART Baud Divisor Middle Byte Register (UARTMBAUD) .............................................. 432

12.7.8 UART Baud Divisor Low Byte Register (UARTLBAUD)................................................... 433

12.7.9 UART Receive Buffer (UARTRXBUF) ....................................................................... 434

12.7.10 UART Transmit Buffer (UARTTXBUF) ..................................................................... 435

12.7.11 UART I/O Control Register (UARTIOCTRLSCLK, UARTIOCTRLRX, UARTIOCTRLTX)........... 436

13 Boot ROM and Boot Flash ................................................................................................. 437

13.1 Boot ROM Function ...................................................................................................... 438

13.1.1 Initializing UCD3138............................................................................................ 438

13.1.2 Verifying Checksums........................................................................................... 438

13.1.3 Uses for 2 Different Checksums.............................................................................. 438

13.1.4 Avoiding Program Flash Lockup.............................................................................. 440

13.1.5 Using BOOT ROM PMBus Interface......................................................................... 441

13.2 Memory Read Functionality ............................................................................................. 441

13.2.1 Configure Read Address....................................................................................... 441

13.2.2 Read 4 Bytes.................................................................................................... 442

13.2.3 Read 16 Bytes .................................................................................................. 442

13.2.4 Read Next 16 Bytes............................................................................................ 442

13.3 Read Version.............................................................................................................. 442

13.4 Memory Write Functionality ............................................................................................. 443

13.4.1 Write 4 Bytes.................................................................................................... 443

13.4.2 Write 16 Bytes................................................................................................... 443

13.4.3 Write Next 16 Bytes ............................................................................................ 444

13.5 Flash Functions ........................................................................................................... 444

13.5.1 Mass Erase...................................................................................................... 444

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13.5.2 Page Erase ...................................................................................................... 445

13.5.3 Execute Flash ................................................................................................... 446

13.5.4 Flash Programming Sequence using Boot ROM........................................................... 446

13.6 Checksum Functions ..................................................................................................... 447

13.6.1 Calculation of Checksum ...................................................................................... 447

13.6.2 Reading Checksum............................................................................................. 447

13.7 Trim Flash Checksum Verification...................................................................................... 447

13.8 Boot ROM for the Other Members of the UCD3138 Family ........................................................ 448

13.8.1 UCD3138064 and UCD3138064A............................................................................ 448

13.8.2 UCD3138A64 and UCD3138A64A........................................................................... 449

13.8.3 UCD3138128 and UCD3138128A............................................................................ 450

14 ARM7TDMI-S MPUSS ........................................................................................................ 452

14.1 ARM7TDMI-S Modes of Operation..................................................................................... 453

14.1.1 Exceptions....................................................................................................... 455

14.2 Hardware Interrupts ...................................................................................................... 455

14.2.1 Standard Interrupt (IRQ)....................................................................................... 455

14.2.2 Fast Interrupt (FIQ)............................................................................................. 456

14.3 Software Interrupt......................................................................................................... 456

14.4 ARM7TDMI-S Instruction Set ........................................................................................... 457

14.4.1 Instruction Compression ....................................................................................... 457

14.4.2 The Thumb Instruction Set .................................................................................... 457

14.5 Dual-State Interworking .................................................................................................. 457

14.5.1 Level of Dual-State Support................................................................................... 458

14.5.2 Implementation.................................................................................................. 459

14.5.3 Naming Conventions for Entry Points (CCS 3.x)........................................................... 459

14.5.4 Indirect Calls..................................................................................................... 459

14.5.5 UCD3138 Reference Code.................................................................................... 461

15 Memory ........................................................................................................................... 465

15.1 Memory Controller – MMC Registers Reference ..................................................................... 468

15.1.1 Static Memory Control Register (SMCTRL)................................................................. 468

15.1.2 Write Control Register (WCTRL) ............................................................................. 470

15.1.3 Peripheral Control Register (PCTRL) ........................................................................ 471

15.1.4 Peripheral Location Register (PLOC) ........................................................................ 472

15.1.5 Peripheral Protection Register (PPROT) .................................................................... 473

15.2 DEC – Address Manager Registers Reference....................................................................... 473

15.2.1 Memory Fine Base Address High Register 0 (MFBAHR0)................................................ 473

15.2.2 Memory Fine Base Address Low Register 0 (MFBALR0)................................................. 475

15.2.3 1.1.1 Memory Fine Base Address High Register 1-3,17-19 (MFBAHRx)............................... 476

15.2.4 Memory Fine Base Address Low Register 1-3, 17-19 (MFBALRx)...................................... 477

15.2.5 Memory Fine Base Address High Load Differences for Enhanced 3138 Devices ..................... 478

15.2.6 Memory Fine Base Address High Register 4 (MFBAHR4)................................................ 479

15.2.7 Memory Fine Base Address Low Register 4-16 (MFBALRx) ............................................. 480

15.2.8 Memory Fine Base Address High Register 5 (MFBAHR5)................................................ 481

15.2.9 Memory Fine Base Address High Register 6 (MFBAHR6)................................................ 482

15.2.10 Memory Fine Base Address High Register 7 (MFBAHR7) .............................................. 483

15.2.11 Memory Fine Base Address High Register 8 (MFBAHR8) .............................................. 484

15.2.12 Memory Fine Base Address High Register 9 (MFBAHR9) .............................................. 485

15.2.13 Memory Fine Base Address High Register 10 (MFBAHR10) ........................................... 486

15.2.14 Memory Fine Base Address High Register 11 (MFBAHR11) ........................................... 487

15.2.15 Memory Fine Base Address High Register 12 (MFBAHR12) ........................................... 488

15.2.16 Memory Fine Base Address High Register 13 (MFBAHR13) ........................................... 489

15.2.17 Memory Fine Base Address High Register 14 (MFBAHR14) ........................................... 490

15.2.18 Memory Fine Base Address High Register 15 (MFBAHR15) ........................................... 491

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15.2.19 Memory Fine Base Address High Register 16 (MFBAHR16) ........................................... 492

15.2.20 Program Flash Control Register (PFLASHCTRL) ........................................................ 493

15.2.21 Data Flash Control Register (DFLASHCTRL)............................................................. 494

15.2.22 Flash Interlock Register (FLASHILOCK)................................................................... 495

16 Control System Module ..................................................................................................... 496

16.1 Address Decoder (DEC) ................................................................................................. 497

16.1.1 Memory Mapping Basics....................................................................................... 497

16.1.2 Why Change Memory Map? .................................................................................. 499

16.1.3 How do Memory Map Registers Work?...................................................................... 499

16.1.4 RONLY Bit....................................................................................................... 499

16.1.5 Boot ROM Memory Initialization .............................................................................. 499

16.1.6 Erasing the Programming Flash .............................................................................. 500

16.1.7 Waiting for Flash Operations to Finish....................................................................... 500

16.1.8 Flash Interlock Register........................................................................................ 501

16.1.9 Clearing RDONLY Bit.......................................................................................... 501

16.1.10 Switching from User Mode to Supervisor Mode........................................................... 501

16.1.11 Erasing Data Flash............................................................................................ 501

16.1.12 Writing to Data Flash ......................................................................................... 501

16.1.13 Erasing Program Flash....................................................................................... 502

16.1.14 Writing to Program Flash..................................................................................... 502

16.2 Memory Management Controller (MMC) .............................................................................. 502

16.3 System Management (SYS)............................................................................................. 502

16.4 Central Interrupt Module (CIM).......................................................................................... 502

16.4.1 Interrupt Handling by CPU..................................................................................... 504

16.4.2 Interrupt Generation at Peripheral............................................................................ 504

16.4.3 CIM Interrupt Management (CIM) ............................................................................ 504

16.4.4 CIM Input Channel Management............................................................................. 505

16.4.5 CIM Prioritization................................................................................................ 506

16.4.6 CIM Operation................................................................................................... 506

16.4.7 Register Map .................................................................................................... 508

16.5 SYS – System Module Registers Reference.......................................................................... 508

16.5.1 Clock Control Register (CLKCNTL) .......................................................................... 508

16.5.2 System Exception Control Register (SYSECR) ............................................................ 510

16.5.3 System Exception Status Register (SYSESR).............................................................. 511

16.5.4 Abort Exception Status Register (ABRTESR) .............................................................. 513

16.5.5 Global Status Register (GLBSTAT) .......................................................................... 514

16.5.6 Device Identification Register (DEV)......................................................................... 515

16.5.7 System Software Interrupt Flag Register (SSIF) ........................................................... 516

16.5.8 System Software Interrupt Request Register (SSIR) ...................................................... 517

16.5.9 References ...................................................................................................... 517

17 Flash Memory Programming, Integrity, and Security............................................................. 518

17.1 Quick Start Summary..................................................................................................... 519

17.1.1 ROM Bootstrap and Program Flash Checksum............................................................ 519

17.1.2 Firmware Development Setup ................................................................................ 519

17.1.3 Production Setup ............................................................................................... 519

17.2 Flash Memory Operations ............................................................................................... 519

17.2.1 UCD3138 Memory Maps ...................................................................................... 519

17.2.2 Flash Programming in ROM Mode ........................................................................... 520

17.2.3 Clearing the Flash .............................................................................................. 520

17.2.4 3138 Family Members with Multiple Flash Blocks.......................................................... 520

17.3 Flash Management for Firmware Development ...................................................................... 521

17.3.1 Best Practice for Firmware Development.................................................................... 521

17.3.2 Firmware Development with "Backdoors" ................................................................... 521

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17.3.3 I/O Line Based Backdoors..................................................................................... 521

17.3.4 Communications Backdoors................................................................................... 522

17.4 Flash Management in Production....................................................................................... 522

17.5 Firmware Examples ...................................................................................................... 523

17.5.1 Checksum Clearing............................................................................................. 523

17.5.2 Erasing Flash.................................................................................................... 524

17.5.3 Serial Port Based Backdoor................................................................................... 524

17.5.4 I/O Line Based Back Door..................................................................................... 524

18 CIM – Central Interrupt Module Registers Reference............................................................. 525

18.1 IRQ Index Offset Vector Register (IRQIVEC)......................................................................... 526

18.2 FIQ Index Offset Vector Register (FIQIVEC) ......................................................................... 527

18.3 FIQ/IRQ Program Control Register (FIRQPR)........................................................................ 528

18.4 Pending Interrupt Read Location Register (INTREQ)................................................................ 529

18.5 Interrupt Mask Register (REQMASK).................................................................................. 530

Revision History ........................................................................................................................ 531

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1-1. ................................................................................................................................ 31

2-1. Block Diagram of a DPWM Module...................................................................................... 35

2-2. Block Diagram of Timing Module in the DPWM module .............................................................. 36

2-3. DPWM Mode - Multi-mode, Open Loop................................................................................. 38

2-4. DPWM - Normal Mode .................................................................................................... 39

2-5. DPWM - Phase Shift Mode ............................................................................................... 41

2-6. DPWM – Multiple Output Mode (Multi Mode) .......................................................................... 42

2-7. DPWM – Resonant Mode................................................................................................. 44

2-8. DPWM – Triangular Mode ................................................................................................ 45

2-9. DPWM – Leading Edge Mode............................................................................................ 46

2-10. SyncFET IDE (Normal Mode)............................................................................................. 47

2-11. Resonant LLC implementation in UCD3138 with Automatic Mode Switching ..................................... 48

2-12. Mechanism for Automatic Mode Switching in UCD3138.............................................................. 49

2-13. UCD3138 Edge-Gen & Intra-Mux........................................................................................ 50

2-14. ................................................................................................................................ 55

2-15. Minimum Duty Mode 1..................................................................................................... 57

2-16. Minimum Duty Mode 2..................................................................................................... 57

2-17. DPWM Control Register 0 (DPWMCTRL0)............................................................................. 67

2-18. DPWM Control Register 1 (DPWMCTRL1)............................................................................. 70

2-19. DPWM Control Register 2 (DPWMCTRL2)............................................................................. 73

2-20. DPWM Period Register (DPWMPRD)................................................................................... 75

2-21. DPWM Event 1 Register (DPWMEV1) .................................................................................. 76

2-22. DPWM Event 2 Register (DPWMEV2) .................................................................................. 77

2-23. DPWM Event 3 Register (DPWMEV3) .................................................................................. 78

2-24. DPWM Event 4 Register (DPWMEV4) .................................................................................. 79

2-25. DPWM Sample Trigger 1 Register (DPWMSAMPTRIG1)............................................................ 80

2-26. DPWM Sample Trigger 2 Register (DPWMSAMPTRIG2)............................................................ 81

2-27. DPWM Phase Trigger Register (DPWMPHASETRIG)................................................................ 82

2-28. DPWM Cycle Adjust A Register (DPWMCYCADJA) .................................................................. 83

2-29. DPWM Cycle Adjust B Register (DPWMCYCADJB) .................................................................. 84

2-30. DPWM Resonant Duty Register (DPWMRESDUTY).................................................................. 85

2-31. DPWM Fault Control Register (DPWMFLTCTRL) ..................................................................... 86

2-32. DPWM Overflow Register (DPWMOVERFLOW) ...................................................................... 87

2-33. DPWM Interrupt Register (DPWMINT) .................................................................................. 88

2-34. DPWM Counter Preset Register (DPWMCNTPRE) ................................................................... 90

2-35. DPWM Blanking A Begin Register (DPWMBLKABEG) ............................................................... 91

2-36. DPWM Blanking A End Register (DPWMBLKAEND) ................................................................. 92

2-37. DPWM Blanking B Begin Register (DPWMBLKBBEG) ............................................................... 93

2-38. DPWM Blanking B End Register (DPWMBLKBEND) ................................................................. 94

2-39. DPWM Minimum Duty Cycle High Register (DPWMMINDUTYHI) .................................................. 95

2-40. DPWM Minimum Duty Cycle Low Register (DPWMMINDUTYLO).................................................. 96

2-41. DPWM Adaptive Sample Register (DPWMADAPTIVE)............................................................... 97

2-42. DPWM Fault Status (DPWMFLTSTAT) ................................................................................. 98

2-43. DPWM Auto Switch High Upper Thresh Register (DPWMAUTOSWHIUPTHRESH) ............................. 99

2-44. DPWM Auto Switch High Lower Thresh Register (DPWMAUTOSWHILOWTHRESH) ......................... 100

2-45. DPWM Auto Switch Low Upper Thresh Register (DPWMAUTOSWLOUPTHRESH) ........................... 101

2-46. DPWM Auto Switch Low Lower Thresh Register (DPWMAUTOSWLOLOWTHRESH)......................... 102

List of Figures

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2-47. DPWM Auto Config Max Register (DPWMAUTOMAX).............................................................. 103

2-48. DPWM Auto Config Mid Register (DPWMAUTOMID) ............................................................... 105

2-49. DPWM Edge PWM Generation Control Register (DPWMEDGEGEN) ............................................ 107

2-50. DPWM Filter Duty Read Register (DPWMFILTERDUTYREAD) ................................................... 109

2-51. DPWM BIST Status Register (DPWMBISTSTAT).................................................................... 110

3-1. Simplified Block Diagram of Front End in UCD3138 (Front End 2 recommended for Peak Current Mode

Control)..................................................................................................................... 111

3-2. .............................................................................................................................. 114

3-3. Consecutive Mode of Averaging by EADC............................................................................ 116

3-4. Spatial Mode of Averaging by EADC .................................................................................. 116

3-5. .............................................................................................................................. 118

3-6. DAC Dither................................................................................................................. 118

3-7. .............................................................................................................................. 120

3-8. Ideal Diode Emulation (IDE) Module in UCD3138 ................................................................... 122

3-9. Ramp Control Register (RAMPCTRL) ................................................................................ 124

3-10. Ramp Status Register (RAMPSTAT) .................................................................................. 126

3-11. Ramp Cycle Register (RAMPCYCLE) ................................................................................. 127

3-12. EADC DAC Value Register (EADCDAC).............................................................................. 128

3-13. Ramp DAC Ending Value Register (RAMPDACEND)............................................................... 129

3-14. DAC Step Register (DACSTEP) ........................................................................................ 130

3-15. DAC Saturation Step Register (DACSATSTEP)...................................................................... 131

3-16. EADC Trim Register (EADCTRIM) ..................................................................................... 132

3-17. EADC Control Register (EADCCTRL) ................................................................................. 133

3-18. Analog Control Register (ACTRL) ...................................................................................... 135

3-19. Pre-Bias Control Register 0 (PREBIASCTRL0) ...................................................................... 136

3-20. Pre-Bias Control Register 1 (PREBIASCTRL1) ...................................................................... 137

3-21. SAR Control Register (SARCTRL) ..................................................................................... 138

3-22. SAR Timing Register (SARTIMING) ................................................................................... 139

3-23. EADC Value Register (EADCVALUE) ................................................................................. 140

3-24. EADC Raw Value Register (EADCRAWVALUE)..................................................................... 141

3-25. DAC Status Register (DACSTAT) ...................................................................................... 142

4-1. .............................................................................................................................. 144

4-2. .............................................................................................................................. 146

4-3. .............................................................................................................................. 147

4-4. .............................................................................................................................. 153

4-5. .............................................................................................................................. 154

4-6. Filter Status Register (FILTERSTATUS) .............................................................................. 156

4-7. Filter Control Register (FILTERCTRL)................................................................................. 158

4-8. CPU XN Register (CPUXN) ............................................................................................. 160

4-9. Filter XN Read Register (FILTERXNREAD) .......................................................................... 161

4-10. Filter KI_YN Read Register (FILTERKIYNREAD).................................................................... 162

4-11. Filter KD_YN Read Register (FILTERKDYNREAD) ................................................................. 163

4-12. Filter YN Read Register (FILTERYNREAD) .......................................................................... 164

4-13. Coefficient Configuration Register (COEFCONFIG) ................................................................. 165

4-14. Filter KP Coefficient 0 Register (FILTERKPCOEF0)................................................................. 168

4-15. Filter KP Coefficient 1 Register (FILTERKPCOEF1)................................................................. 169

4-16. Filter KI Coefficient 0 Register (FILTERKICOEF0) .................................................................. 170

4-17. Filter KI Coefficient 1 Register (FILTERKICOEF1)................................................................... 171

4-18. Filter KD Coefficient 0 Register (FILTERKDCOEF0) ................................................................ 172

List of Figures

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4-19. Filter KD Coefficient 1 Register (FILTERKDCOEF1) ................................................................ 173

4-20. Filter KD Alpha Register (FILTERKDALPHA)......................................................................... 174

4-21. Filter Nonlinear Limit Register 0 (FILTERNL0) ....................................................................... 175

4-22. Filter Nonlinear Limit Register 1 (FILTERNL1) ....................................................................... 176

4-23. Filter Nonlinear Limit Register 2 (FILTERNL2) ....................................................................... 177

4-24. Filter KI Feedback Clamp High Register (FILTERKICLPHI) ........................................................ 178

4-25. Filter KI Feedback Clamp Low Register (FILTERKICLPLO)........................................................ 179

4-26. Filter YN Clamp High Register (FILTERYNCLPHI) .................................................................. 180

4-27. Filter YN Clamp Low Register (FILTERYNCLPLO).................................................................. 181

4-28. Filter Output Clamp High Register (FILTEROCLPHI)................................................................ 182

4-29. Filter Output Clamp Low Register (FILTEROCLPLO) ............................................................... 183

4-30. Filter Preset Register (FILTERPRESET) .............................................................................. 184

5-1. UCD3138 Flux Balancing Approach.................................................................................... 190

5-2. Front End Control 0 Mux Register (FECTRL0MUX) ................................................................. 191

5-3. Front End Control 1 Mux Register (FECTRL1MUX) ................................................................. 193

5-4. Front End Control 2 Mux Register (FECTRL2MUX) ................................................................. 195

5-5. Sample Trigger Control Register (SAMPTRIGCTRL)................................................................ 197

5-6. External DAC Control Register (EXTDACCTRL) .................................................................... 198

5-7. Filter Mux Register (FILTERMUX) ..................................................................................... 199

5-8. Filter KComp A Register (FILTERKCOMPA) ......................................................................... 201

5-9. Filter KComp B Register (FILTERKCOMPB) ......................................................................... 202

5-10. DPWM Mux Register (DPWMMUX) ................................................................................... 203

5-11. Constant Power Control Register (CPCTRL) ........................................................................ 205

5-12. Constant Power Nominal Threshold Register (CPNOM) ........................................................... 207

5-13. Constant Power Max Threshold Register (CPMAX) ................................................................ 208

5-14. Constant Power Configuration Register (CPCONFIG) .............................................................. 209

5-15. Constant Power Max Power Register (CPMAXPWR) ............................................................... 210

5-16. Constant Power Integrator Threshold Register (CPINTTHRESH) ................................................ 211

5-17. Constant Power Firmware Divisor Register (CPFWDIVISOR) ..................................................... 212

5-18. onstant Power Status Register (CPSTAT) ............................................................................ 213

5-19. Cycle Adjustment Control Register (CYCADJCTRL) ................................................................ 214

5-20. Cycle Adjustment Limit Register (CYCADJLIM) ..................................................................... 215

5-21. Cycle Adjustment Status Register (CYCADJSTAT) ................................................................. 216

5-22. Global Enable Register (GLBEN)....................................................................................... 217

5-23. PWM Global Period Register (PWMGLBPRD) ....................................................................... 218

5-24. Sync Control Register (SYNCCTRL)................................................................................... 219

5-25. Light Load Control Register (LLCTRL)................................................................................. 220

5-26. Light Load Enable Threshold Register (LLENTHRESH) ............................................................ 221

5-27. Light Load Disable Threshold Register (LLDISTHRESH)........................................................... 222

5-28. Peak Current Mode Control Register (PCMCTRL)................................................................... 223

5-29. Analog Peak Current Mode Control Register (APCMCTRL)........................................................ 224

5-30. Loop Mux Test Register (LOOPMUXTEST) (Test Use Only)....................................................... 225

6-1. UCD3138 Fault Handling System ...................................................................................... 226

6-2. UCD3138 Analog Comparator Control................................................................................. 228

6-3. UCD3138 DPWM Fault Action.......................................................................................... 231

6-4. .............................................................................................................................. 233

6-5. Analog Comparator Control 0 Register (ACOMPCTRL0) .......................................................... 235

6-6. Analog Comparator Control 1 Register (ACOMPCTRL1) .......................................................... 237

6-7. Analog Comparator Control 2 Register (ACOMPCTRL2) .......................................................... 239

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6-8. Analog Comparator Control 3 Register (ACOMPCTRL3) .......................................................... 241

6-9. External Fault Control Register (EXTFAULTCTRL) ................................................................. 242

6-10. Fault Mux Interrupt Status Register (FAULTMUXINTSTAT) ....................................................... 243

6-11. Fault Mux Raw Status Register (FAULTMUXRAWSTAT) .......................................................... 245

6-12. Comparator Ramp Control 0 Register (COMPRAMP0) ............................................................. 247

6-13. Digital Comparator Control 0 Register (DCOMPCTRL0)............................................................ 249

6-14. Digital Comparator Control 1 Register (DCOMPCTRL1)............................................................ 250

6-15. Digital Comparator Control 2 Register (DCOMPCTRL2)............................................................ 251

6-16. Digital Comparator Control 3 Register (DCOMPCTRL3)............................................................ 252

6-17. Digital Comparator Counter Status Register (DCOMPCNTSTAT)................................................. 253

6-18. DPWM 0 Current Limit Control Register (DPWM0CLIM)............................................................ 254

6-19. DPWM 0 Fault AB Detection Register (DPWM0FLTABDET)....................................................... 256

6-20. DPWM 0 Fault Detection Register (DPWM0FAULTDET)........................................................... 257

6-21. DPWM 1 Current Limit Control Register (DPWM1CLIM)............................................................ 260

6-22. DPWM 1 Fault AB Detection Register (DPWM1FLTABDET)....................................................... 262

6-23. DPWM 1 Fault Detection Register (DPWM1FAULTDET)........................................................... 264

6-24. DPWM 2 Current Limit Control Register (DPWM2CLIM)............................................................ 267

6-25. DPWM 2 Fault AB Detection Register (DPWM2FLTABDET)....................................................... 269

6-26. DPWM 2 Fault Detection Register (DPWM2FAULTDET)........................................................... 271

6-27. DPWM 3 Current Limit Control Register (DPWM3CLIM)............................................................ 274

6-28. DPWM 3 Fault AB Detection Register (DPWM3FLTABDET)....................................................... 276

6-29. DPWM 3 Fault Detection Register (DPWM3FAULTDET)........................................................... 278

6-30. HFO Fail Detect Register (HFOFAILDET)............................................................................. 281

6-31. LFO Fail Detect Register (LFOFAILDET) ............................................................................. 282

6-32. IDE Control Register (IDECTRL) ....................................................................................... 283

7-1. Fault IO Direction Register (FAULTDIR)............................................................................... 285

7-2. Fault Input Register (FAULTIN)......................................................................................... 286

7-3. Fault Output Register (FAULTOUT).................................................................................... 287

7-4. Fault Interrupt Enable Register (FAULTINTENA) .................................................................... 288

7-5. Fault Interrupt Polarity Register (FAULTINTPOL).................................................................... 289

7-6. Fault Interrupt Pending Register (FAULTINTPEND)................................................................. 290

7-7. External Interrupt Direction Register (EXTINTDIR) .................................................................. 291

7-8. External Interrupt Input Register (EXTINTIN)......................................................................... 292

7-9. External Interrupt Output Register (EXTINTOUT).................................................................... 293

7-10. External Interrupt Enable Register (EXTINTENA).................................................................... 294

7-11. External Interrupt Polarity Register (EXTTINTPOL).................................................................. 295

7-12. External Interrupt Pending Register (EXTINTPEND) ................................................................ 296

8-1. ADC12 Control Block Diagram.......................................................................................... 297

8-2. ADC12 Input Impedance Model ........................................................................................ 299

8-3. ADC Input Impedance Model Containing External Circuits ......................................................... 299

8-4. Impedance Test Setup ................................................................................................... 300

8-5. ADC12 Channel Impedance............................................................................................. 300

8-6. S/H Capacitor Charge vs. Settling Time............................................................................... 301

8-7. External Capacitance Makes Lower Source Impedance ............................................................ 301

8-8. Channel to Channel Crosstalk .......................................................................................... 301

8-9. ADC Control Register (ADCCTRL) .................................................................................... 302

8-10. UCS3138 Digital Comparators Control Block Diagram.............................................................. 304

8-11. Temp Sensor Control Register (TEMPSENCTRL) ................................................................... 306

8-12. PMBus Control Register 3 (PMBCTRL3).............................................................................. 307

List of Figures

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8-13. PMBus Addressing ....................................................................................................... 308

8-14. ADC Control Register (ADCCTRL)..................................................................................... 309

8-15. Dual Sample and Hold Circuitry in ADC12............................................................................ 310

8-16. ADC12 Dual Sample and Hold Configuration......................................................................... 310

8-17. .............................................................................................................................. 313

8-18. .............................................................................................................................. 315

8-19. ADC Control Register (ADCCTRL) .................................................................................... 316

8-20. ADC Status Register (ADCSTAT) ..................................................................................... 318

8-21. ADC Test Control Register (ADCTSTCTRL).......................................................................... 319

8-22. ADC Sequence Select Register 0 (ADCSEQSEL0).................................................................. 320

8-23. ADC Sequence Select Register 1 (ADCSEQSEL1).................................................................. 321

8-24. ADC Sequence Select Register 2 (ADCSEQSEL2).................................................................. 322

8-25. ADC Sequence Select Register 3 (ADCSEQSEL3).................................................................. 323

8-26. ADC Result Registers 0-15 (ADCRESULTx, x=0:15)................................................................ 324

8-27. ADC Averaged Result Registers 0-5 (ADCAVGRESULTx, x=0:15) ............................................... 325

8-28. ADC Digital Compare Limits Register 0-5 (ADCCOMPLIMx, x=0:5) .............................................. 326

8-29. ADC Digital Compare Enable Register (ADCCOMPEN) ............................................................ 327

8-30. ADC Digital Compare Results Register (ADCCOMPRESULT)..................................................... 329

8-31. ADC Averaging Control Register (ADCAVGCTRL) .................................................................. 331

9-1. .............................................................................................................................. 334

9-2. .............................................................................................................................. 335

9-3. .............................................................................................................................. 336

9-4. Package ID Register (PKGID) .......................................................................................... 336

9-5. Brownout Register (BROWNOUT) ..................................................................................... 337

9-6. Temp Sensor Control Register (TEMPSENCTRL)................................................................... 338

9-7. I/O Mux Control Register (IOMUX)..................................................................................... 339

9-8. Current Sharing Control Register (CSCTRL) ......................................................................... 340

9-9. Temperature Reference Register (TEMPREF) ....................................................................... 341

9-10. Power Disable Control Register (PWRDISCTRL) .................................................................... 342

9-11. Global I/O EN Register (GBIOEN)...................................................................................... 346

9-12. Global I/O OE Register (GLBIOOE).................................................................................... 347

9-13. Global I/O Open Drain Control Register (GLBIOOD) ................................................................ 348

9-14. Global I/O Value Register (GLBIOVAL)................................................................................ 349

9-15. Global I/O Read Register (GLBIOREAD).............................................................................. 350

9-16. Clock Trim Register (CLKTRIM) (For Factory Test Use Only, Except HFO_LN_FILTER_EN) ................ 351

10-1. .............................................................................................................................. 356

10-2. Command with PEC...................................................................................................... 357

10-3. Write Command and Byte - No PEC................................................................................... 357

10-4. Write Command and Byte - with PEC.................................................................................. 358

10-5. Write 2 Bytes with no PEC .............................................................................................. 358

10-6. Timing Diagram ........................................................................................................... 359

10-7. Write 4 Bytes + Command .............................................................................................. 359

10-8. Slave Address Manual ACK for Write.................................................................................. 360

10-9. Manual ACK Command.................................................................................................. 361

10-10. Simple Read with Full Automation...................................................................................... 362

10-11. Simple Read of 4 Bytes with Full Automation......................................................................... 363

10-12. Simple Read of 5 Bytes with Full Automation......................................................................... 363

10-13. Slave Address Manual ACK on a Read Address..................................................................... 364

10-14. Write/Read with Repeated Start ........................................................................................ 365

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10-15. Clock Stretch Timing for Read .......................................................................................... 367

10-16. Alert Response............................................................................................................ 368

10-17. Address Byte Timing ..................................................................................................... 369

10-18. Repeated Start Timing ................................................................................................... 369

10-19. Read Byte Timing......................................................................................................... 370

10-20. Write Byte Timing......................................................................................................... 370

10-21. Write Byte Stop Timing................................................................................................... 370

10-22. Quick Command Format................................................................................................. 373

10-23. Send Byte w/o PEC Byte ................................................................................................ 373

10-24. Send Byte with PEC Byte................................................................................................ 373

10-25. Receive Byte w/o PEC Byte............................................................................................. 373

10-26. Receive Byte with PEC Byte ............................................................................................ 373

10-27. Write Byte w/o PEC Byte ................................................................................................ 374

10-28. Write Byte with PEC Byte................................................................................................ 374

10-29. Write Word w/o PEC Byte ............................................................................................... 374

10-30. Write Word with PEC Byte............................................................................................... 374

10-31. Read Byte w/o PEC Byte ................................................................................................ 375

10-32. Read Byte with PEC Byte ............................................................................................... 375

10-33. Read Word w/o PEC Byte............................................................................................... 375

10-34. Read Word with PEC Byte .............................................................................................. 375

10-35. Process Call w/o PEC Byte ............................................................................................. 376

10-36. Process Call with PEC Byte............................................................................................. 376

10-37. Block Write w/o PEC Byte............................................................................................... 377

10-38. Block Write with PEC Byte .............................................................................................. 377

10-39. Block Read w/o PEC Byte............................................................................................... 378

10-40. Block Read with PEC Byte .............................................................................................. 378

10-41. Block Write-Block Read Process Call w/o PEC Byte ................................................................ 379

10-42. Block Write-Block Read Process Call with PEC Byte................................................................ 379

10-43. Alert Response............................................................................................................ 379

10-44. Extended Command Write Byte w/o PEC Byte....................................................................... 380

10-45. Extended Command Write Byte with PEC Byte ...................................................................... 380

10-46. Extended Command Write Word w/o PEC Byte...................................................................... 380

10-47. Extended Command Write Word with PEC Byte..................................................................... 380

10-48. Extended Command Read Byte w/o PEC Byte....................................................................... 380

10-49. Extended Command Read Byte with PEC Byte...................................................................... 380

10-50. Extended Command Read Word w/o PEC Byte...................................................................... 380

10-51. Extended Command Read Word with PEC Byte..................................................................... 380

10-52. .............................................................................................................................. 381

10-53. PMBUS Control Register 1 (PMBCTRL1)............................................................................. 382

10-54. PMBus Transmit Data Buffer (PMBTXBUF) .......................................................................... 384

10-55. PMBus Receive Data Register (PMBRXBUF) ........................................................................ 385

10-56. PMBus Acknowledge Register (PMBACK)............................................................................ 386

10-57. PMBus Status Register (PMBST) ...................................................................................... 387

10-58. PMBus Interrupt Mask Register (PMBINTM).......................................................................... 389

10-59. PMBus Control Register 2 (PMBCTRL2).............................................................................. 390

10-60. PMBus Hold Slave Address Register (PMBHSA) .................................................................... 392

10-61. PMBus Control Register 3 (PMBCTRL3).............................................................................. 393

11-1. .............................................................................................................................. 397

11-2. .............................................................................................................................. 400

List of Figures

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11-3. .............................................................................................................................. 402

11-4. 24-bit Counter Data Register (T24CNTDAT).......................................................................... 405

11-5. 24-bit Counter Control Register (T24CNTCTRL)..................................................................... 406

11-6. 24-bit Capture Channel Data Register (T24CAPDAT)............................................................... 407

11-7. 24-bit Capture Channel Control Register (T24CAPCTRL).......................................................... 408

11-8. 24-bit Capture I/O Control and Data Register (T24CAPIO)......................................................... 409

11-9. 24-bit Output Compare Channel 0 Data Register (T24CMPDAT0) ................................................ 410

11-10. 24-bit Output Compare Channel 1 Data Register (T24CMPDAT1) ................................................ 411

11-11. 24-bit Output Compare Channel 0 Control Register (T24CMPCTRL0) ........................................... 412

11-12. 24-bit Output Compare Channel 1 Control Register (T24CMPCTRL1) ........................................... 413

11-13. PWMx Counter Data Register (T16PWMxCNTDAT) ................................................................ 414

11-14. PWMx Counter Control Register (T16PWMxCNTCTRL)............................................................ 415

11-15. PWMx 16-bit Compare Channel 0-1 Data Register (T16PWMxCMPyDAT)...................................... 416

11-16. PWMx Compare Control Register (T16PWMxCMPCTRL).......................................................... 417

11-17. Watchdog Status (WDST) ............................................................................................... 419

11-18. Watchdog Control (WDCTRL) .......................................................................................... 420

12-1. .............................................................................................................................. 422

12-2. .............................................................................................................................. 423

12-3. UART Control Register 0 (UARTCTRL0) ............................................................................. 426

12-4. UART Receive Status Register (UARTRXST) ....................................................................... 427

12-5. UART Transmit Status Register (UARTTXST) ....................................................................... 428

12-6. UART Control Register 3 (UARTCTRL3) ............................................................................. 429

12-7. UART Interrupt Status Register (UARTINTST) ...................................................................... 430

12-8. UART Baud Divisor High Byte Register (UARTHBAUD) ........................................................... 431

12-9. UART Baud Divisor Middle Byte Register (UARTMBAUD) ........................................................ 432

12-10. UART Baud Divisor Low Byte Register (UARTLBAUD)............................................................. 433

12-11. UART Receive Buffer (UARTRXBUF) ................................................................................. 434

12-12. UART Transmit Buffer (UARTTXBUF)................................................................................. 435

12-13. UART I/O Control Register (UARTIOCTRLSCLK, UARTIOCTRLRX, UARTIOCTRLTX) ...................... 436

13-1. UCD3138 Boot ROM Execution After Power-On/Reset............................................................. 439

13-2. Boot Flash ................................................................................................................. 440

13-3. UCD3138064 Boot ROM Execution After Power-on/Reset ......................................................... 448

13-4. UCD3138A64 Boot ROM Execution After Power-on/Reset......................................................... 450

13-5. UCD3138128 Boot ROM Execution After Power-on/Reset ......................................................... 451

14-1. .............................................................................................................................. 462

14-2. .............................................................................................................................. 463

14-3. .............................................................................................................................. 464

15-1. Static Memory Control Register (SMCTRL)........................................................................... 468

15-2. Write Control Register (WCTRL) ....................................................................................... 470

15-3. Peripheral Control Register (PCTRL) .................................................................................. 471

15-4. Peripheral Location Register (PLOC) .................................................................................. 472

15-5. Peripheral Protection Register (PPROT) .............................................................................. 473

15-6. Memory Fine Base Address High Register 0 (MFBAHR0).......................................................... 474

15-7. Memory Fine Base Address Low Register 0 (MFBALR0)........................................................... 475

15-8. Memory Fine Base Address High Register 1-3,17-19 (MFBAHRx)................................................ 476

15-9. Memory Fine Base Address Low Register 1-3, 17-19 (MFBALRx) ................................................ 477

15-10. Memory Fine Base Address High Register 4 (MFBAHR4).......................................................... 479

15-11. Memory Fine Base Address Low Register 4-16 (MFBALRx) ....................................................... 480

15-12. Memory Fine Base Address High Register 5 (MFBAHR5).......................................................... 481

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15-13. Memory Fine Base Address High Register 6 (MFBAHR6).......................................................... 482

15-14. Memory Fine Base Address High Register 7 (MFBAHR7).......................................................... 483

15-15. Memory Fine Base Address High Register 8 (MFBAHR8).......................................................... 484

15-16. Memory Fine Base Address High Register 9 (MFBAHR9).......................................................... 485

15-17. Memory Fine Base Address High Register 10 (MFBAHR10)....................................................... 486

15-18. Memory Fine Base Address High Register 11 (MFBAHR11)....................................................... 487

15-19. Memory Fine Base Address High Register 12 (MFBAHR12)....................................................... 488

15-20. Memory Fine Base Address High Register 13 (MFBAHR13)....................................................... 489

15-21. Memory Fine Base Address High Register 14 (MFBAHR14)....................................................... 490

15-22. Memory Fine Base Address High Register 15 (MFBAHR15)....................................................... 491

15-23. Memory Fine Base Address High Register 16 (MFBAHR16)....................................................... 492

15-24. Program Flash Control Register (PFLASHCTRL) .................................................................... 493

15-25. Data Flash Control Register (DFLASHCTRL)......................................................................... 494

15-26. Flash Interlock Register (FLASHILOCK) .............................................................................. 495

16-1. .............................................................................................................................. 498

16-2. Base Address ............................................................................................................. 499

16-3. .............................................................................................................................. 505

16-4. Clock Control Register (CLKCNTL) .................................................................................... 508

16-5. System Exception Control Register (SYSECR)....................................................................... 510

16-6. System Exception Status Register (SYSESR)........................................................................ 511

16-7. Abort Exception Status Register (ABRTESR)......................................................................... 513

16-8. Global Status Register (GLBSTAT) .................................................................................... 514

16-9. Device Identification Register (DEV) ................................................................................... 515

16-10. System Software Interrupt Flag Register (SSIF) ..................................................................... 516

16-11. System Software Interrupt Request Register (SSIR) ................................................................ 517

18-1. IRQ Index Offset Vector Register (IRQIVEC)......................................................................... 526

18-2. FIQ Index Offset Vector Register (FIQIVEC) ......................................................................... 527

18-3. FIQ/IRQ Program Control Register (FIRQPR)........................................................................ 528

18-4. Pending Interrupt Read Location Register (INTREQ)................................................................ 529

18-5. Interrupt Mask Register (REQMASK) .................................................................................. 530

List of Figures

SNIU028A–February 2016–Revised April 2016

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2-1. DPWM Register Time Resolutions in UCD3138 ....................................................................... 51

2-2. DPWM Period Register (DPWMPRD) All other 4 ns registers with standard alignment are the same. ........ 52

2-3. DPWM Sample Trigger 1 Register (DPWMSAMPTRIG1) ............................................................ 52

2-4. DPWM Event 2 Register (DPWMEV2) Event 3 and 4 are the same, Cycle Adjust registers only go to bit 15 52

2-5. Truth Table.................................................................................................................. 55

2-6. DPWM Control Register 0 (DPWMCTRL0) Register Field Descriptions............................................ 67

2-7. DPWM Control Register 1 (DPWMCTRL1) Register Field Descriptions............................................ 70

2-8. DPWM Control Register 2 (DPWMCTRL2) Register Field Descriptions............................................ 73

2-9. DPWM Period Register (DPWMPRD) Register Field Descriptions.................................................. 75

2-10. DPWM Event 1 Register (DPWMEV1) Register Field Descriptions ................................................. 76

2-11. DPWM Event 2 Register (DPWMEV2) Register Field Descriptions ................................................. 77

2-12. DPWM Event 3 Register (DPWMEV3) Register Field Descriptions ................................................. 78

2-13. DPWM Event 4 Register (DPWMEV4) Register Field Descriptions ................................................. 79

2-14. DPWM Sample Trigger 1 Register (DPWMSAMPTRIG1) Register Field Descriptions........................... 80

2-15. DPWM Sample Trigger 2 Register (DPWMSAMPTRIG2) Register Field Descriptions........................... 81

2-16. DPWM Phase Trigger Register (DPWMPHASETRIG) Register Field Descriptions............................... 82

2-17. DPWM Cycle Adjust A Register (DPWMCYCADJA) Register Field Descriptions................................. 83

2-18. DPWM Cycle Adjust B Register (DPWMCYCADJB) Register Field Descriptions................................. 84

2-19. DPWM Resonant Duty Register (DPWMRESDUTY) Register Field Descriptions ................................ 85

2-20. DPWM Fault Control Register (DPWMFLTCTRL) Register Field Descriptions.................................... 86

2-21. DPWM Overflow Register (DPWMOVERFLOW) Register Field Descriptions ..................................... 87

2-22. DPWM Interrupt Register (DPWMINT) Register Field Descriptions................................................. 88

2-23. DPWM Counter Preset Register (DPWMCNTPRE) Register Field Descriptions .................................. 90

2-24. DPWM Blanking A Begin Register (DPWMBLKABEG) Register Field Descriptions.............................. 91

2-25. DPWM Blanking A End Register (DPWMBLKAEND) Register Field Descriptions................................ 92

2-26. DPWM Blanking B Begin Register (DPWMBLKBBEG) Register Field Descriptions.............................. 93

2-27. DPWM Blanking B End Register (DPWMBLKBEND) Register Field Descriptions................................ 94

2-28. DPWM Minimum Duty Cycle High Register (DPWMMINDUTYHI) Register Field Descriptions ................. 95

2-29. DPWM Minimum Duty Cycle Low Register (DPWMMINDUTYLO) Register Field Descriptions................. 96

2-30. DPWM Adaptive Sample Register (DPWMADAPTIVE) Register Field Descriptions ............................. 97

2-31. DPWM Fault Status (DPWMFLTSTAT) Register Field Descriptions................................................ 98

2-32. DPWM Auto Switch High Upper Thresh Register (DPWMAUTOSWHIUPTHRESH) Register Field

2-33. DPWM Auto Switch High Lower Thresh Register (DPWMAUTOSWHILOWTHRESH) Register Field

2-34. DPWM Auto Switch Low Upper Thresh Register (DPWMAUTOSWLOUPTHRESH) Register Field

2-35. DPWM Auto Switch Low Lower Thresh Register (DPWMAUTOSWLOLOWTHRESH) Register Field

2-36. DPWM Auto Config Max Register (DPWMAUTOMAX) Register Field Descriptions ............................ 103

2-37. DPWM Auto Config Mid Register (DPWMAUTOMID) Register Field Descriptions.............................. 105

2-38. DPWM Edge PWM Generation Control Register (DPWMEDGEGEN) Register Field Descriptions........... 107

2-39. DPWM Filter Duty Read Register (DPWMFILTERDUTYREAD) Register Field Descriptions.................. 109

2-40. DPWM BIST Status Register (DPWMBISTSTAT) Register Field Descriptions .................................. 110

3-1. .............................................................................................................................. 113

3-2. .............................................................................................................................. 120

3-3. Ramp Control Register (RAMPCTRL) Register Field Descriptions ................................................ 124

3-4. Ramp Status Register (RAMPSTAT) Register Field Descriptions ................................................. 126

List of Tables

Descriptions................................................................................................................. 99

Descriptions ............................................................................................................... 100

Descriptions ............................................................................................................... 101

Descriptions ............................................................................................................... 102

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3-5. Ramp Cycle Register (RAMPCYCLE) Register Field Descriptions ................................................ 127

3-6. EADC DAC Value Register (EADCDAC) Register Field Descriptions............................................. 128

3-7. Ramp DAC Ending Value Register (RAMPDACEND) Register Field Descriptions.............................. 129

3-8. DAC Step Register (DACSTEP) Register Field Descriptions....................................................... 130

3-9. DAC Saturation Step Register (DACSATSTEP) Register Field Descriptions .................................... 131

3-10. EADC Trim Register (EADCTRIM) Register Field Descriptions.................................................... 132

3-11. EADC Control Register (EADCCTRL) Register Field Descriptions ................................................ 133

3-12. Analog Control Register (ACTRL) Register Field Descriptions..................................................... 135

3-13. Pre-Bias Control Register 0 (PREBIASCTRL0) Register Field Descriptions ..................................... 136

3-14. Pre-Bias Control Register 1 (PREBIASCTRL1) Register Field Descriptions ..................................... 137

3-15. SAR Control Register (SARCTRL) Register Field Descriptions.................................................... 138

3-16. SAR Timing Register (SARTIMING) Register Field Descriptions .................................................. 139

3-17. EADC Value Register (EADCVALUE) Register Field Descriptions ................................................ 140

3-18. EADC Raw Value Register (EADCRAWVALUE) Register Field Descriptions.................................... 141

3-19. DAC Status Register (DACSTAT) Register Field Descriptions..................................................... 142

4-1. Filter Status Register (FILTERSTATUS) Register Field Descriptions ............................................. 157

4-2. Filter Control Register (FILTERCTRL) Register Field Descriptions................................................ 158

4-3. CPU XN Register (CPUXN) Register Field Descriptions............................................................ 160

4-4. Filter XN Read Register (FILTERXNREAD) Register Field Descriptions ......................................... 161

4-5. Filter KI_YN Read Register (FILTERKIYNREAD) Register Field Descriptions................................... 162

4-6. Filter KD_YN Read Register (FILTERKDYNREAD) Register Field Descriptions ................................ 163

4-7. 9.7 Filter YN Read Register (FILTERYNREAD) Register Field Descriptions..................................... 164

4-8. Coefficient Configuration Register (COEFCONFIG) Register Field Descriptions................................ 165

4-9. Filter KP Coefficient 0 Register (FILTERKPCOEF0) Register Field Descriptions ............................... 168

4-10. Filter KP Coefficient 1 Register (FILTERKPCOEF1) Register Field Descriptions ............................... 169

4-11. Filter KI Coefficient 0 Register (FILTERKICOEF0) Register Field Descriptions.................................. 170

4-12. Filter KI Coefficient 1 Register (FILTERKICOEF1) Register Field Descriptions.................................. 171

4-13. Filter KD Coefficient 0 Register (FILTERKDCOEF0) Register Field Descriptions ............................... 172

4-14. Filter KD Coefficient 1 Register (FILTERKDCOEF1) Register Field Descriptions ............................... 173

4-15. Filter KD Alpha Register (FILTERKDALPHA) Register Field Descriptions ....................................... 174

4-16. Filter Nonlinear Limit Register 0 (FILTERNL0) Register Field Descriptions ...................................... 175

4-17. Filter Nonlinear Limit Register 1 (FILTERNL1) Register Field Descriptions ...................................... 176

4-18. Filter Nonlinear Limit Register 2 (FILTERNL2) Register Field Descriptions ...................................... 177

4-19. Filter KI Feedback Clamp High Register (FILTERKICLPHI) Register Field Descriptions....................... 178

4-20. Filter KI Feedback Clamp Low Register (FILTERKICLPLO) Register Field Descriptions....................... 179

4-21. Filter YN Clamp High Register (FILTERYNCLPHI) Register Field Descriptions ................................. 180

4-22. Filter YN Clamp Low Register (FILTERYNCLPLO) Register Field Descriptions................................. 181

4-23. Filter Output Clamp High Register (FILTEROCLPHI) Register Field Descriptions .............................. 182

4-24. Filter Output Clamp Low Register (FILTEROCLPLO) Register Field Descriptions .............................. 183

4-25. Filter Preset Register (FILTERPRESET) Register Field Descriptions............................................. 184

5-1. .............................................................................................................................. 185

5-2. Front End Control 0 Mux Register (FECTRL0MUX) Register Field Descriptions................................ 191

5-3. Front End Control 1 Mux Register (FECTRL1MUX) Register Field Descriptions................................ 193

5-4. Front End Control 2 Mux Register (FECTRL2MUX) Register Field Descriptions................................ 195

5-5. Sample Trigger Control Register (SAMPTRIGCTRL) Register Field Descriptions............................... 197

5-6. External DAC Control Register (EXTDACCTRL) Register Field Descriptions.................................... 198

5-7. Filter Mux Register (FILTERMUX) Register Field Descriptions .................................................... 199

5-8. Filter KComp A Register (FILTERKCOMPA) Register Field Descriptions ........................................ 201

5-9. Filter KComp B Register (FILTERKCOMPB) Register Field Descriptions ........................................ 202

List of Tables

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5-10. DPWM Mux Register (DPWMMUX) Register Field Descriptions................................................... 203

5-11. Constant Power Control Register (CPCTRL) Register Field Descriptions ........................................ 205

5-12. Constant Power Nominal Threshold Register (CPNOM) Register Field Descriptions........................... 207

5-13. Constant Power Max Threshold Register (CPMAX) Register Field Descriptions................................ 208

5-14. Constant Power Configuration Register (CPCONFIG) Register Field Descriptions ............................. 209

5-15. Constant Power Max Power Register (CPMAXPWR)Register Field Descriptions ............................... 210

5-16. Constant Power Integrator Threshold Register (CPINTTHRESH) Register Field Descriptions................ 211

5-17. Constant Power Firmware Divisor Register (CPFWDIVISOR) Register Field Descriptions .................... 212

5-18. onstant Power Status Register (CPSTAT) Register Field Descriptions ........................................... 213

5-19. Cycle Adjustment Control Register (CYCADJCTRL) Register Field Descriptions ............................... 214

5-20. Cycle Adjustment Limit Register (CYCADJLIM) Register Field Descriptions..................................... 215

5-21. Cycle Adjustment Status Register (CYCADJSTAT) Register Field Descriptions ................................ 216

5-22. Global Enable Register (GLBEN)Register Field Descriptions ...................................................... 217

5-23. PWM Global Period Register (PWMGLBPRD) Register Field Descriptions ...................................... 218

5-24. Sync Control Register (SYNCCTRL) Register Field Descriptions.................................................. 219

5-25. Light Load Control Register (LLCTRL) Register Field Descriptions ............................................... 220

5-26. Light Load Enable Threshold Register (LLENTHRESH) Register Field Descriptions ........................... 221

5-27. Light Load Disable Threshold Register (LLDISTHRESH) Register Field Descriptions.......................... 222

5-28. Peak Current Mode Control Register (PCMCTRL) Register Field Descriptions.................................. 223

5-29. Analog Peak Current Mode Control Register (APCMCTRL)Register Field Descriptions ....................... 224

5-30. Loop Mux Test Register (LOOPMUXTEST) (Test Use Only) Register Field Descriptions ..................... 225

6-1. Analog Comparator Control 0 Register (ACOMPCTRL0) Register Field Descriptions .......................... 235

6-2. Analog Comparator Control 1 Register (ACOMPCTRL1) Register Field Descriptions .......................... 237

6-3. Analog Comparator Control 2 Register (ACOMPCTRL2) Register Field Descriptions .......................... 239

6-4. Analog Comparator Control 3 Register (ACOMPCTRL3) Register Field Descriptions .......................... 241

6-5. External Fault Control Register (EXTFAULTCTRL) Register Field Descriptions................................. 242

6-6. Fault Mux Interrupt Status Register (FAULTMUXINTSTAT) Register Field Descriptions....................... 243

6-7. Fault Mux Raw Status Register (FAULTMUXRAWSTAT) Register Field Descriptions ......................... 245

6-8. Comparator Ramp Control 0 Register (COMPRAMP0) Register Field Descriptions ............................ 247

6-9. Digital Comparator Control 0 Register (DCOMPCTRL0) Register Field Descriptions........................... 249

6-10. Digital Comparator Control 1 Register (DCOMPCTRL1) Register Field Descriptions........................... 250

6-11. Digital Comparator Control 2 Register (DCOMPCTRL2) Register Field Descriptions........................... 251

6-12. Digital Comparator Control 3 Register (DCOMPCTRL3) Register Field Descriptions........................... 252

6-13. Digital Comparator Counter Status Register (DCOMPCNTSTAT) Register Field Descriptions................ 253

6-14. DPWM 0 Current Limit Control Register (DPWM0CLIM) Register Field Descriptions .......................... 254

6-15. DPWM 0 Fault AB Detection Register (DPWM0FLTABDET) Register Field Descriptions...................... 256

6-16. DPWM 0 Fault Detection Register (DPWM0FAULTDET) Register Field Descriptions.......................... 257

6-17. DPWM 1 Current Limit Control Register (DPWM1CLIM) Register Field Descriptions .......................... 260

6-18. DPWM 1 Fault AB Detection Register (DPWM1FLTABDET) Register Field Descriptions...................... 262

6-19. DPWM 1 Fault Detection Register (DPWM1FAULTDET) Register Field Descriptions.......................... 264

6-20. DPWM 2 Current Limit Control Register (DPWM2CLIM) Register Field Descriptions .......................... 267

6-21. DPWM 2 Fault AB Detection Register (DPWM2FLTABDET) Register Field Descriptions...................... 269

6-22. DPWM 2 Fault Detection Register (DPWM2FAULTDET) Register Field Descriptions.......................... 271

6-23. DPWM 3 Current Limit Control Register (DPWM3CLIM) Register Field Descriptions .......................... 274

6-24. DPWM 3 Fault AB Detection Register (DPWM3FLTABDET) Register Field Descriptions...................... 276

6-25. DPWM 3 Fault Detection Register (DPWM3FAULTDET) Register Field Descriptions.......................... 278

6-26. HFO Fail Detect Register (HFOFAILDET) Register Field Descriptions ........................................... 281

6-27. LFO Fail Detect Register (LFOFAILDET) Register Field Descriptions ............................................ 282

6-28. IDE Control Register (IDECTRL) Register Field Descriptions ...................................................... 283

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7-1. Fault IO Direction Register (FAULTDIR) Register Field Descriptions ............................................. 285

7-2. Fault Input Register (FAULTIN) Register Field Descriptions........................................................ 286

7-3. Fault Output Register (FAULTOUT) Register Field Descriptions................................................... 287

7-4. Fault Interrupt Enable Register (FAULTINTENA) Register Field Descriptions ................................... 288

7-5. Fault Interrupt Polarity Register (FAULTINTPOL) Register Field Descriptions................................... 289

7-6. Fault Interrupt Pending Register (FAULTINTPEND) Register Field Descriptions................................ 290

7-7. External Interrupt Direction Register (EXTINTDIR) Register Field Descriptions ................................. 291

7-8. External Interrupt Input Register (EXTINTIN) Register Field Descriptions........................................ 292

7-9. External Interrupt Output Register (EXTINTOUT) Register Field Descriptions................................... 293

7-10. External Interrupt Enable Register (EXTINTENA) Register Field Descriptions................................... 294

7-11. External Interrupt Polarity Register (EXTTINTPOL) Register Field Descriptions ................................ 295

7-12. External Interrupt Pending Register (EXTINTPEND) Register Field Descriptions ............................... 296

8-1. Temp Sensor Control Register (TEMPSENCTRL) Register Field Descriptions.................................. 306

8-2. PMBus Control Register 3 (PMBCTRL3) Register Field Descriptions............................................. 307

8-3. Selection of “Dual Sample and Hold” Channel ....................................................................... 308

8-4. ADC Control Register (ADCCTRL) Register Field Descriptions.................................................... 309

8-5. ADC Control Register (ADCCTRL) Register Field Descriptions.................................................... 316

8-6. ADC Status Register (ADCSTAT) Register Field Descriptions..................................................... 318

8-7. ADC Test Control Register (ADCTSTCTRL) Register Field Descriptions......................................... 319

8-8. ADC Sequence Select Register 0 (ADCSEQSEL0) Register Field Descriptions ................................ 320

8-9. ADC Sequence Select Register 1 (ADCSEQSEL1) Register Field Descriptions ................................ 321

8-10. ADC Sequence Select Register 2 (ADCSEQSEL2) Register Field Descriptions ................................ 322

8-11. ADC Sequence Select Register 3 (ADCSEQSEL3) Register Field Descriptions ................................ 323

8-12. ADC Result Registers 0-15 (ADCRESULTx, x=0:15) Register Field Descriptions............................... 324

8-13. ADC Averaged Result Registers 0-5 (ADCAVGRESULTx, x=0:15) Register Field Descriptions.............. 325

8-14. ADC Digital Compare Limits Register 0-5 (ADCCOMPLIMx, x=0:5) Register Field Descriptions ............. 326

8-15. ADC Digital Compare Enable Register (ADCCOMPEN) Register Field Descriptions........................... 327

8-16. ADC Digital Compare Results Register (ADCCOMPRESULT) Register Field Descriptions.................... 329

8-17. ADC Averaging Control Register (ADCAVGCTRL) Register Field Descriptions ................................. 331

9-1. Tolerance .................................................................................................................. 335

9-2. .............................................................................................................................. 335

9-3. Package ID Register (PKGID) Register Field Descriptions ......................................................... 336

9-4. Brownout Register (BROWNOUT) Register Field Descriptions .................................................... 337

9-5. Temp Sensor Control Register (TEMPSENCTRL) Register Field Descriptions.................................. 338

9-6. Bits 9-8: EXT_TRIG_MUX_SEL – EXT_TRIG Pin Mux Select ..................................................... 339

9-7. Bits 7-6: JTAG_CLK_MUX_SEL – TCK Pin Mux Select ............................................................ 339

9-8. Bits 5-4: JTAG_DATA_MUX_SEL – TDO/TDI Pin Mux Select ..................................................... 339

9-9. Bits 3-2: SYNC_MUX_SEL – SYNC Pin Mux Select ................................................................ 339

9-10. Bit 1: UART_MUX_SEL – SCL/SDA Pins Mux Select............................................................... 339

9-11. Bit 0: PMBUS_MUX_SEL – SCL/SDA Pins Mux Select............................................................. 339

9-12. Current Sharing Control Register (CSCTRL) Register Field Descriptions ........................................ 340

9-13. .............................................................................................................................. 340

9-14. Temperature Reference Register (TEMPREF) Register Field Descriptions ...................................... 341

9-15. Power Disable Control Register (PWRDISCTRL) Register Field Descriptions................................... 342

9-16. ADC Control Register (ADCCTRL) Register Field Descriptions.................................................... 346

9-17. Global I/O OE Register (GLBIOOE) Register Field Descriptions................................................... 347

9-18. Global I/O Open Drain Control Register (GLBIOOD) Register Field Descriptions............................... 348

9-19. Global I/O Value Register (GLBIOVAL) Register Field Descriptions .............................................. 349

9-20. Global I/O Read Register (GLBIOREAD) Register Field Descriptions ............................................ 350

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9-21. Clock Trim Register (CLKTRIM) (For Factory Test Use Only, Except HFO_LN_FILTER_EN) Register

10-1. .............................................................................................................................. 354

10-2. Timing Parameters from Timing Diagrams ............................................................................ 371

10-3. .............................................................................................................................. 371

10-4. Simple Timing Parameters (No Timing Diagram) .................................................................... 371

10-5. PMBUS Control Register 1 (PMBCTRL1) Register Field Descriptions............................................ 382

10-6. PMBus Transmit Data Buffer (PMBTXBUF) Register Field Descriptions ......................................... 384

10-7. PMBus Receive Data Register (PMBRXBUF) Register Field Descriptions....................................... 385

10-8. PMBus Acknowledge Register (PMBACK) Register Field Descriptions........................................... 386

10-9. PMBus Status Register (PMBST) Register Field Descriptions ..................................................... 387

10-10. PMBus Interrupt Mask Register (PMBINTM) Register Field Descriptions ........................................ 389

10-11. PMBus Control Register 2 (PMBCTRL2) Register Field Descriptions............................................. 390

10-12. PMBus Hold Slave Address Register (PMBHSA) Register Field Descriptions ................................... 392

10-13. PMBus Control Register 3 (PMBCTRL3) Register Field Descriptions............................................. 393

11-1. 24-bit Counter Data Register (T24CNTDAT) Register Field Descriptions ........................................ 405

11-2. 24-bit Counter Control Register (T24CNTCTRL) Register Field Descriptions.................................... 406

11-3. 24-bit Capture Channel Data Register (T24CAPDAT) Register Field Descriptions.............................. 407

11-4. 24-bit Capture Channel Control Register (T24CAPCTRL) Register Field Descriptions......................... 408

11-5. 24-bit Capture I/O Control and Data Register (T24CAPIO) Register Field Descriptions........................ 409

11-6. 24-bit Output Compare Channel 0 Data Register (T24CMPDAT0) Register Field Descriptions............... 410

11-7. 24-bit Output Compare Channel 1 Data Register (T24CMPDAT1) Register Field Descriptions............... 411

11-8. 24-bit Output Compare Channel 0 Control Register (T24CMPCTRL0) Register Field Descriptions .......... 412

11-9. 24-bit Output Compare Channel 1 Control Register (T24CMPCTRL1) Register Field Descriptions .......... 413

11-10. PWMx Counter Data Register (T16PWMxCNTDAT) Register Field Descriptions ............................... 414

11-11. PWMx Counter Control Register (T16PWMxCNTCTRL) Register Field Descriptions........................... 415

11-12. PWMx 16-bit Compare Channel 0-1 Data Register (T16PWMxCMPyDAT) Register Field Descriptions..... 416

11-13. PWMx Compare Control Register (T16PWMxCMPCTRL) Register Field Descriptions......................... 417

11-14. Watchdog Status (WDST) Register Field Descriptions .............................................................. 419

11-15. Watchdog Control (WDCTRL) Register Field Descriptions ......................................................... 420

12-1. .............................................................................................................................. 423

12-2. UART Control Register 0 (UARTCTRL0) Register Field Descriptions............................................. 426

12-3. UART Receive Status Register (UARTRXST) Register Field Descriptions....................................... 427

12-4. UART Transmit Status Register (UARTTXST) Register Field Descriptions ...................................... 428

12-5. UART Control Register 3 (UARTCTRL3) Register Field Descriptions............................................. 429

12-6. UART Interrupt Status Register (UARTINTST) Register Field Descriptions...................................... 430

12-7. UART Baud Divisor High Byte Register (UARTHBAUD) Register Field Descriptions........................... 431

12-8. UART Baud Divisor Middle Byte Register (UARTMBAUD) Register Field Descriptions ........................ 432

12-9. UART Baud Divisor Low Byte Register (UARTLBAUD) Register Field Descriptions............................ 433

12-10. UART Receive Buffer (UARTRXBUF) Register Field Descriptions ................................................ 434

12-11. UART Transmit Buffer (UARTTXBUF) Register Field Descriptions................................................ 435

12-12. UART I/O Control Register (UARTIOCTRLSCLK, UARTIOCTRLRX, UARTIOCTRLTX) Register Field

13-1. ROM Version for the Other Members of the UCD3138 Family..................................................... 443

13-2. Boot ROM Mass Erase Data Byte Parameter Values ............................................................... 445

13-3. Boot ROM Execute Flash Command Byte, Valid Values ........................................................... 446

13-4. Checksums Used By UCD3138064 Boot ROM Program ........................................................... 448

13-5. Checksums Used by UCD3138A64 Boot ROM Program ........................................................... 449

13-6. Checksums Used by UCD3138128 Boot ROM Program............................................................ 450

Field Descriptions......................................................................................................... 351

Descriptions ............................................................................................................... 436

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14-1. ARM Processor Operating Modes...................................................................................... 453

14-2. General-Purpose Registers and Program Counter................................................................... 453

14-3. Current Program Status Register....................................................................................... 454

14-4. Bit Patterns in Different ARM Processor Operating Modes ........................................................ 454

14-5. ARM Processor Exceptions ............................................................................................. 455

15-1. ROM and Program Flash Memory Map (ROM Operation) .......................................................... 465

15-2. Memory Map (Flash Operation)......................................................................................... 466

15-3. RAM and Data Flash Memory Map (ROM and Flash Operation) .................................................. 466

15-4. Memory Map (System and Peripherals Blocks) ...................................................................... 466

15-5. Static Memory Control Register (SMCTRL) Register Field Descriptions.......................................... 468

15-6. Write Control Register (WCTRL) Register Field Descriptions ...................................................... 470

15-7. Peripheral Control Register (PCTRL) Register Field Descriptions................................................. 471

15-8. Peripheral Location Register (PLOC) Register Field Descriptions................................................. 472

15-9. Peripheral Protection Register (PPROT) Register Field Descriptions ............................................. 473

15-10. Memory Fine Base Address High Register 0 (MFBAHR0) Register Field Descriptions......................... 474

15-11. Memory Fine Base Address Low Register 0 (MFBALR0) Register Field Descriptions.......................... 475

15-12. Memory Fine Base Address High Register 1-3, 17-19 (MFBAHRx) Register Field Descriptions .............. 476

15-13. Memory Fine Base Address Low Register 1-3, 17-19 (MFBALRx) Register Field Descriptions ............... 477

15-14. Memory Fine Base Address High Register 4 (MFBAHR4) Register Field Descriptions......................... 479

15-15. Memory Fine Base Address Low Register 4-17 (MFBALRx) Register Field Descriptions...................... 480

15-16. Memory Fine Base Address High Register 5 (MFBAHR5) Register Field Descriptions......................... 481

15-17. Memory Fine Base Address High Register 6 (MFBAHR6) Register Field Descriptions......................... 482

15-18. Memory Fine Base Address High Register 7 (MFBAHR7) Register Field Descriptions......................... 483

15-19. Memory Fine Base Address High Register 8 (MFBAHR8) Register Field Descriptions......................... 484

15-20. Memory Fine Base Address High Register 9 (MFBAHR9) Register Field Descriptions......................... 485

15-21. Memory Fine Base Address High Register 10 (MFBAHR10) Register Field Descriptions...................... 486

15-22. Memory Fine Base Address High Register 11 (MFBAHR11) Register Field Descriptions...................... 487

15-23. Memory Fine Base Address High Register 12 (MFBAHR12) Register Field Descriptions...................... 488

15-24. Memory Fine Base Address High Register 13 (MFBAHR13) Register Field Descriptions...................... 489

15-25. Memory Fine Base Address High Register 14 (MFBAHR14) Register Field Descriptions...................... 490

15-26. Memory Fine Base Address High Register 15 (MFBAHR15) Register Field Descriptions...................... 491

15-27. Memory Fine Base Address High Register 16 (MFBAHR16) Register Field Descriptions...................... 492

15-28. PFLASHCTRL Addresses ............................................................................................... 493

15-29. Program Flash Control Register (PFLASHCTRL) Register Field Descriptions................................... 493

15-30. Data Flash Control Register (DFLASHCTRL) Register Field Descriptions ....................................... 494

15-31. Flash Interlock Register (FLASHILOCK) Register Field Descriptions ............................................. 495

16-1. .............................................................................................................................. 500

16-2. Interrupt Priority Table ................................................................................................... 503

16-3. .............................................................................................................................. 508

16-4. Clock Control Register (CLKCNTL) Register Field Descriptions ................................................... 508

16-5. System Exception Control Register (SYSECR) Register Field Descriptions ..................................... 510

16-6. System Exception Status Register (SYSESR) Register Field Descriptions....................................... 511

16-7. Abort Exception Status Register (ABRTESR) Register Field Descriptions ....................................... 513

16-8. Global Status Register (GLBSTAT) Register Field Descriptions ................................................... 514

16-9. Device Identification Register (DEV) Register Field Descriptions.................................................. 515

16-10. System Software Interrupt Flag Register (SSIF) Register Field Descriptions .................................... 516

16-11. System Software Interrupt Request Register (SSIR) Register Field Descriptions ............................... 517

18-1. IRQ Index Offset Vector Register (IRQIVEC) Register Field Descriptions........................................ 526

18-2. FIQ Index Offset Vector Register (FIQIVEC) Register Field Descriptions ........................................ 527

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18-3. FIQ/IRQ Program Control Register (FIRQPR) Register Field Descriptions....................................... 528

18-4. Pending Interrupt Read Location Register (INTREQ) Register Field Descriptions .............................. 529

18-5. Interrupt Mask Register (REQMASK) Register Field Descriptions................................................. 530

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UCD3138 is a digital power supply controller from Texas Instruments offering superior levels of integration and performance in a single chip solution targeting high-performance isolated power supply applications. At its core are the digital control loop peripherals, also known as Digital Power Peripherals (DPP) that are used for controlling the high-speed voltage/current loops, and a ARM7TDMI-S microcontroller (32-bit,

31.25MHz) that performs real-time monitoring, communication and configuration of peripherals. Each DPP is capable of implementing a high speed digital control loop by employing a dedicated, high-speed Error Analog to Digital Converter (EADC), a PID based 2 pole–2 zero digital compensator and digital pulse width modulator (DPWM) outputs with 250-ps pulse width resolution. The device also contains 12-bit, 267ksps general purpose ADC with up to 14 channels, timers, interrupt control, JTAG debug and PMBus & UART communications ports. In terms of memory, UCD3138 offers 32KB of program flash, 2kB of data flash, 4KB RAM and 4KB of ROM.

1.1 Scope of This Document

For the most up to date product specifications please consult the UCD3138 Device datasheet (SLUSAP2) available at www.ti.com.

Chapter 1

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Introduction

1.2 A Guide to Other Documentation for all Members of UCD3138 Family of Products

All members of UCD3138 family of Controllers share the same core functions and features. But each one of these devices also offers some unique abilities that may not exist in the other members of the family. The following table is arranged in order to direct you to the right manual for a specific device of your interest.

A downloading link is provided at the intersection only if the specific manual is needed for certain device.

Device\Manual

UCD3138 UCD3138A UCD3138064 SLUUAD8 UCD3138064A UCD3138A64 SLUUB54 UCD3138A64A UCD3138128 SLUUB54 UCD3138128A

UCD3138 Digital Power Peripherals

Programmer’s Manual

The description of modules and peripherals in UCD3138 family of controllers are explained in 3 major manuals and several complimentary/migration manuals.

The following table is arranged in order to direct you to the right manual for detailed information regarding a specific module, peripheral or function that you are seeking.

Migration Guide, Device Enhancement

Summary

Introduction

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Error ADC

(Front End)

Filter

Digital

PWM

EAP

EAN

DPWMA

DPWMB

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A Guide to Other Documentation for all Members of UCD3138 Family of Products

Module Function\Manual

Loop Mux

Fault Mux

DPWM

Filter (CLA)

Front End UART SLUU996

ADC12 (GP ADC) Dual Sample and Hold, Averaging SLUU996

Miscellaneous Analog

GIO FAULT pin, EXT interrupt SLUU996 PMBus/ I2C SLUU996 SLUUAD8 SLUUB54 SPI SLUUAD8

Timers Central Interrupt

Module ARM Core SLUU994 ROM bootloader SLUU994 SLUUAD8 SLUUB54

Flash MMC

(Memory Controller) DEC

(Address Manager) SYS

(System Module)

CPCC, DTC, GLBEN, Light load, PCM

Analog Comp, Digital Comp, IDE, Fault Det

Dead-times, Sample trigger, Frequency and Phase Setting, Mode Switching, Blanking

PID Compensation, Coefficients, Clamps, Non Linear control, Filter Preset

EADC, AFE, RAMP, SAR, Reference DAC, DAC-Dither, PCM

GLBIO(Global IO), IOMUX, Current Sharing, temperature sensor, PKG_ID (Package identification)

Low res. PWM, Watchdog, capture, compare

CIM SLUU994 SLUUB54

Flash Interlock key, PFLASH, DFLASH

Software reset, Exception status, Clock Control (M_DIV_RATIO), DEV (device identification)

Programmer’s

Manual

SLUU995

SLUU995 SLUUB54

SLUU995

SLUU995 SLUUAD8 SLUUB54

SLUU996 SLUUAD8 SLUUB54

SLUU996

SLUU994 SLUUAD8 SLUUB54

SLUU994

SLUU994 SLUUAD8 SLUUB54

UCD3138064

Programmer's

Manual

UCD3138A64/

UCD3138128

Programmer’s

Manual

UCD3138A

Programmer's

Manual

The simplest configuration of the Digital Power Peripherals highlighting the key blocks involved in loop control is shown below:

The Error ADC (in the Front End) accepts a differential voltage signal as an input. It measures the difference between this input and a digitally controlled reference voltage and generates a digital error output. It passes this digital error information to the Filter. The Error ADC (or EADC) is a specialized high speed, high resolution ADC with a small dynamic range, optimized for power supply error measurement.

The Filter takes the error signal and passes it through a PID based digital filter which compensates for the characteristics of the external loop. This filter can be dynamically reprogrammed for changing power load source, and circuit characteristics. It also offers non-linear response capability for better handling of transients.

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Figure 1-1.

Introduction

A Guide to Other Documentation for all Members of UCD3138 Family of Products

The output of the compensator is passed to a Digital PWM (DPWM) generator. The DPWM has two outputs, which can be used in many different ways. There are modes for synchronous rectification, multiple phases, various bridge topologies, and LLC configurations. In addition to the 2 DPWM outputs, the DPWM has other signals which are used externally and internally. These include:

• Frame start – start of a switching cycle

• Sample Trigger – signals Front end to take a sample

• Sync out – signals another DPWM to start a frame

• Sync in – a signal to this DPWM to start a frame

• Fault signals – signal the DPWM to take various fault actions These signals will be covered in much more detail in Chapter 2. The peripherals can be run tied together as shown above, or they can be used in different groupings and

interconnections, not shown in the picture above. For example, the DPWM can be used to trigger the Error ADC, which will trigger the Filter at the end of its conversion.

The UCD3138 device supports multiple sets of the Digital Power Peripherals affording the ability to control upto 3 feedback loops (voltage or current) and drive 8 outputs simultaneously. To inter-connect all the DPPs, there is a large module called the Loop Mux. This permits a high degree of flexibility in DPP configuration. Any Front End can be connected to any Filter, and any Filter output can be connected to any DPWM. Additionally, information can be passed between the peripherals. For example, the output of one Filter (eg. controlling a slow Voltage loop), can contribute to the reference of another Front End (eg. monitoring a fast current loop) and enable implementation of nested loops (such as in Average Current mode control).

In addition, the DPPs in UCD3138 provide other modules and functions for power supply and control. These include:

• Fault Handling

• Cycle by Cycle Current Limit

• Constant Power/Constant Current

• Ramp up/Ramp Down

• Peak Current Mode control and so on.

There is also a module called Fault Mux which connects fault detection circuitry outputs to control inputs, primarily on the DPWMs, to customize fault handling and recovery.

This documentation provides information about the DPP modules in UCD3138, starting with a detailed description, continuing with some configuration examples, and ending with a reference section which lists each bit field in each DPP module.

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Chapter 2

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Digital Pulse Width Modulator (DPWM)

The DPWM Module is probably the most complex and central of the DPPs. It takes the output of the Filter and converts it into the correct PWM output for many power supply topologies. Each DPWM module has two output pins – DPWMxA and DPWMxB (x=0, 1, 2 & 3). The DPWM provides for programmable dead times and cycle adjustments for current balancing between phases. It controls the triggering of the EADC. It can synchronize to other DPWMs or to external sources. Alternately, it can provide synchronization information to other DPWMs or to external recipients. The DPWM can also be synchronized to external devices using the SYNC pin as either an input or an output. In addition, it interfaces to several fault detection circuits. The response to these faults is part of the DPWM function.

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Digital Pulse Width Modulator (DPWM)

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Topic ........................................................................................................................... Page

2.1 DPWM Block Diagram......................................................................................... 35

2.2 Introduction to DPWM (DPWM Multi-Mode, Open Loop).......................................... 37

2.3 DPWM Normal Mode........................................................................................... 39

2.4 DPWM Phase Shift Mode..................................................................................... 41

2.5 DPWM Multiple Output Mode (Multi Mode) ............................................................ 42

2.6 DPWM Resonant Mode ....................................................................................... 43

2.7 Triangular Mode................................................................................................. 45

2.8 DPWM Leading Edge Mode ................................................................................. 46

2.9 Sync FET Ramp and IDE Calculation .................................................................... 47

2.10 Automatic Mode Switching.................................................................................. 48

2.11 DPWMC, Edge Generation, IntraMax..................................................................... 50

2.12 Time Resolution of Various DPWM Registers ........................................................ 51

2.13 PWM Counter and Clocks.................................................................................... 53

2.14 DPWM Registers - Overview ................................................................................ 53

2.15 DPWM Control Register 0 (DPWMCTRL0).............................................................. 53

2.16 DPWM Control Register 1.................................................................................... 59

2.17 DPWM Control Register 2.................................................................................... 62

2.18 Period and Event Registers ................................................................................. 64

2.19 Phase Trigger Registers...................................................................................... 64

2.20 Cycle Adjust Registers ....................................................................................... 64

2.21 Resonant Duty Register ...................................................................................... 64

2.22 DPWM Fault Control Register .............................................................................. 64

2.23 DPWM Overflow Register .................................................................................... 64

2.24 DPWM Interrupt Register..................................................................................... 65

2.25 DPWM Counter Preset Register ........................................................................... 65

2.26 Blanking Registers ............................................................................................. 65

2.27 DPWM Adaptive Sample Register......................................................................... 66

2.28 DPWM Fault Status Register................................................................................ 66

2.29 DPWM Auto Switch Registers.............................................................................. 66

2.30 DPWM Edge PWM Generation Register................................................................. 66

2.31 DPWM 0-3 Registers Reference............................................................................ 66

Digital Pulse Width Modulator (DPWM)

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Timing Generation

Fault Handling

High Resolution Information

Edge Generation

Many Signals

Faults

Intra Mux

High Resolution Timing

Polarity/Protection

DPWMA_T DPWMC_TDPWMB_T

DPWMA_F DPWMC_FDPWMB_F

To Other

DPWMs

DPWMA_E DPWMC_EDPWMB_E

DPWMx_F

From Other

DPWMs

DPWMA_I

DPWMB_I

DPWMA_H DPWMB_H

DPWMA DPWMB

Many Signals

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2.1 DPWM Block Diagram

The picture below illustrates an overall view of a single DPWM block, which is composed of many different individual modules, through which the signals propagate:

DPWM Block Diagram

• The Timing Generation Module outputs 3 DPWM signals (DPWMx_T, x=A, B, C), as well as many

other signals for other modules. It is the section where the filter output is translated into pulse widths and sometimes into the period.

• The Fault Handling Module is next. It shuts off the DPWM signals if a fault occurs. After the DPWM

signals come from the Fault Module (DPWMx_F, x=A, B, C), they are sent to other DPWM Modules.

• The Edge Generation and Intra Mux modules can combine signals from several DPWMs to generate

new signals (DWMx_E, DPWMx_I, x=A, B, C).

The notation of DPWMx_T, DPWMx_F (where x=A, B, C) etc is very useful here to understand the origin and relationship between the signals. For example DPWM2A_F may have no relationship at all to DPWM2A_I.

Many topologies use neither the DPWMC signal nor Edge Generation and Intra Mux modules. The default is for these modules to just pass signals through unchanged. However certain topologies such as Phase Shifted Full Bridge (PSFB) use both modules as well as DPWMC signal.

These diagrams merely illustrate the signal propagation through the various modules in the DPWM and do not show the configuration logic which controls how each module works and which can dynamically reconfigure the DPWM between switching cycles.

Figure 2-2 shows a block diagram of just the Timing Module illustrating the data, signals and main

elements involved (once again, the real logic of the Timing Module is not illustrated here).

Figure 2-1. Block Diagram of a DPWM Module

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Figure 2-2. Block Diagram of Timing Module in the DPWM module

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Introduction to DPWM (DPWM Multi-Mode, Open Loop)

2.2 Introduction to DPWM (DPWM Multi-Mode, Open Loop)

The DPWM is based on a DPWM counter, which counts up from 0 to a period value, and then is reset and starts over again. The counter can also be reset by a sync signal, either from the SYNC pin, or from another DPWM.

The DPWM logic causes transitions in many digital signals when the period counter hits the target value for that signal. In the Timing Module block diagram shown above, this is functionality is represented by a digital comparator.

The DPWM has a basic 250 MHz clock, giving a resolution of 4 nanoseconds. 15 other 250 MHz clocks are generated spaced 250 picoseconds apart. Output pulse widths and pulse spacing are controlled by these clocks, giving a resolution of 250 picoseconds. The edges generated by these clocks are hence referred to as “High Resolution” in the illustrations throughout this section.

Most of the signals out of the DPWM are fairly simple. The only complex signals are DPWMA and DPWMB. These vary depending upon the power supply topology and are the most important signals coming out of the DPWM.

The DPWM has many modes to support different topologies. These are selected by a mode bit field in a DPWM control register. The “Multi mode, Open loop” mode is used to introduce the DPWM here, while the other DPWM modes are described in subsequent sections.

Figure 2-3 illustrates most of the signals involved in the DPWM in a mode known as “Multi mode, Open

loop”. Open loop means that the DPWM is controlled entirely by its own registers, not by the filter output. In other words, the power supply control loop is not closed. This mode is used for introducing the DPWM because there is a very simple correlation between DPWM register values and signal timing.

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Introduction to DPWM (DPWM Multi-Mode, Open Loop)

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Figure 2-3. DPWM Mode - Multi-mode, Open Loop

The Sample Trigger signals are used to trigger the Front End to sample input signals. The Blanking signals are used to blank fault measurements during noisy events, such as FET turn on and turn off. This prevents false detection of faults caused by noise. They only affect the Cycle By Cycle (CBC) module. Other faults are not blanked.

Note that Sample Trigger 1 and 2, Blanking A and B, and Phase Trigger are shown at logical locations for this specific mode, but they can be placed anywhere within the period.

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2.3 DPWM Normal Mode

Note that Sample Trigger 1 and 2, Blanking A and B, and Phase Trigger are shown at logical locations for this specific mode, but they can be placed anywhere within the period.

DPWM Normal Mode

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Figure 2-4. DPWM - Normal Mode

Digital Pulse Width Modulator (DPWM)

DPWM Normal Mode

Cycle Adjust A can be used to adjust pulse widths on individual phases of a multi-phase system. This can be used if current balancing is necessary, for example. The Adaptive Sample Triggers can be used to sample in the middle of the on-time (Adaptive Sample Trigger B - for an average output during on-time), or at the end of the on-time (Adaptive Sample Trigger A - to minimize phase delay). The Adaptive Sample Register provides an offset from the center or end of the on-time for DPWM signal from the chip. This can compensate for external delays, such as FET and gate driver turn-on times.

The Blanking signals are used to disable the CBC fault signal during noise. Generally the noise is caused by DPWM edges. The Blanking registers hold fixed values, so they are easiest to use with fixed edges, rather than with edges that change dynamically. So in this case, the rising edge of DPWM A and the falling edge of DPWM B are easy to provide blanking for. In this mode, both blanking times act on the falling edge of A, since this is what the Cycle By Cycle logic works on.

Cycle Adjust B has no effect in Normal Mode.

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CAUTION

In Normal Mode, the DPWM calculated rising edge of DPWMB must not be permitted to exceed DPWM Event 4. This can be done either with a clamp on the filter output, or by using an appropriate KCOMP value in the filter output multiply operation. If this is not done, the DPWMB on time may overlap the DPWMA on time, causing shoot through

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Phase Shift

DPWM0 Start of Period

Period Counter

DPWM0 Start of Period

Period

DPWM0 Output A

DPWM0 Output B

DPWM0 Phase Trigger

DPWM1 Start of Period

Period Counter

DPWM1 Start of Period

Period

DPWM1 Output A

DPWM1 Output B

DPWM1 Phase Trigger

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2.4 DPWM Phase Shift Mode

In most modes, it is possible to synchronize multiple DPWM modules using the phase shift signal. The phase shift signal has two possible sources. It can come from the Phase Shift Register or from the Filter Duty value.

The Phase Shift Register provides a fixed value, which is useful in simple multiphase systems such as interleaved PFC.

When the Filter Duty is the source, the changes in the filter output cause changes in the phase relationship of two DPWM modules. This is useful for phase shifted full bridge topologies if voltage mode control is desired rather than peak current mode.

Figure 2-5 shows the mechanism of phase shift:

DPWM Phase Shift Mode

Figure 2-5. DPWM - Phase Shift Mode

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DPWM Multiple Output Mode (Multi Mode)

2.5 DPWM Multiple Output Mode (Multi Mode)

Multi Mode is used for systems where each phase has only one driver signal requirement. In this mode, each DPWM peripheral can drive two phases with the same pulse width, but with a time offset between the phases, and with different cycle adjusts for each phase.

Here is a diagram for Multi mode:

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Figure 2-6. DPWM – Multiple Output Mode (Multi Mode)

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Event 2 and Event 4 are not relevant in Multi mode. As shown in the illustration, DPWMA is designed to turn on close to the start of the period. It can turn off

any time until the end of the period, achieving essentially 100% on-time. DPWMB is designed to start later in the period to support a multi-phase system. Therefore DPWMB is designed to cross over the period boundary safely, so long as it does not ever move into or out of an event update window. This makes 100% pulse width operation possible for DPWMB as well.

Since the rising edge on DPWMB is also fixed, Blanking B Begin and End can be used for blanking this rising edge. In this mode, Blanking A works only on the falling edge of A, and Blanking B works only on the falling edge of B.

And, of course, Cycle Adjust B is usable on DPWM B. There is no restriction preventing the two signals from overlapping each other. The diagram shows the two

signals 180 degrees out of phase, but this is not required. They could be 90 degrees, 60 degrees or whatever offset is desired.

2.6 DPWM Resonant Mode

The resonant mode operation depends on the status of the RESON_DEADTIME_COMP_EN bit. Setting the RESON_DEADTIME_COMP_EN bit provides for a symmetrical waveform where DPWMA and DPWMB have the same pulse width. As the switching frequency changes, the dead times between the pulses remain the same. This mode is ideal for the LLC topology.

Clearing the RESON_DEADTIME_COMP_EN bit provides a mode where the pulse widths are the same and the duty cycle percentage is constant as the period changes. This means that as the frequency increases, the dead times shrink proportionally.

The equations for this mode are designed for a smooth transition from PWM mode to Resonant mode, as described in Section 2.10.1. Here is a diagram of this mode:

DPWM Resonant Mode

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Start of Period

Period Counter

Start of Period

Filter Period

Adaptive Sample Trigger A

Sample Trigger 1

DPWM Output A

Filter Duty – Average Dead Time

Event 1

Event 3 - Event 2

Period Register – Event 4

DPWM Output B

Blanking A Begin

Blanking A End

Blanking B Begin

Blanking B End

Phase Trigger

Sample Trigger 2

To Other

Modules

To Other

Modules

Resonant Symmetrical Closed Loop

Events which change with DPWM mode:

Dead Time 1 = Event 3 – Event 2 Dead Time 2 = Event 1 + Period Register – Event 4) Average Dead Time = (Dead Time 1 + Dead Time 2)/2

DPWM A Rising Edge = Event 1 DPWM A Falling Edge = Event 1 + Filter Duty – Average Dead Time Adaptive Sample Trigger A = Event 1 + Filter Duty + Adaptive Sample Register Adaptive Sample Trigger B = Event 1 + Filter Duty/2 + Adaptive Sample Register DPWM B Rising Edge = Event 1 + Filter Duty – Average Dead Time + (Event 3 – Event 2) DPWM B Falling Edge = Filter Period – (Period Register – Event 4) Phase Trigger = Phase Trigger Register value or Filter Duty

Events always set by their registers, regardless of mode:

Sample Trigger 1, Sample Trigger 2, Blanking A Begin, Blanking A End, Blanking B Begin, Blanking B End

Filter controlled edge

Adaptive Sample Trigger B

DPWM Resonant Mode

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Figure 2-7. DPWM – Resonant Mode

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As seen later, the Filter module has two outputs, Filter Duty and Filter Period. In the Resonant mode, the Filter is configured so that the Filter Period is twice the Filter Duty. With zero dead times, each DPWM pin would be On for half of the period. For dead time handling, the average of the two dead times is subtracted from the Filter Duty for both DPWM pins. Therefore both pins will have the same on-time, and the dead times will be fixed regardless of the period. The only edge which is fixed relative to the start of the period is the rising edge of DPWM A. Blanking A and Blanking B both work only on DPWMA.

2.7 Triangular Mode

Triangular mode provides a very stable phase shift in interleaved PFC and similar topologies. In this case, the PWM pulse is centered in the middle of the period, rather than starting at one end or the other. In Triangular Mode, only DPWM B is available. Here is a diagram for Triangular Mode:

Triangular Mode

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Figure 2-8. DPWM – Triangular Mode

Digital Pulse Width Modulator (DPWM)

DPWM Leading Edge Mode

All edges are dynamic in triangular mode, so fixed blanking is not that useful. The adaptive sample trigger is not needed. It is very easy to put a fixed sample trigger exactly in the center of the On-time, because the center of the on-time does not move in this mode. Both Blanking A and Blanking B are applied to DPWMB.

2.8 DPWM Leading Edge Mode

Leading edge mode is very similar to Normal mode, reversed in time. The DPWM A falling edge is fixed, and the rising edge moves to the left, or backwards in time, as the filter output increases. The DPWMB falling edge stays ahead of the DPWMA rising edge by a fixed dead time. Here is a diagram of the Leading Edge Mode:

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Figure 2-9. DPWM – Leading Edge Mode

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Normal Mode with Sync FET IDE and/or Ramp

DPWM0 Start of Period

Period Counter

DPWM0 Start of Period

Period

DPWM0 Output A

Sync FET edge on DPWM B controlled by Ramp logic and/or Integrated Diode equation

Stays within dead time limits for Normal Mode

DaDa

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As in the Normal mode, the two edges in the middle of the period are dynamic, so the fixed blanking intervals are mainly useful for the edges at the beginning and end of the period.

2.9 Sync FET Ramp and IDE Calculation

For many topologies, it is useful to replace diodes with synchronous rectification (SR), a concept also known as Ideal Diode Emulation (IDE). In continuous conduction mode, the SR FET control is simple, because it can be turned on for the entire off time of the primary FET, minus a dead time. This is handled perfectly by Normal mode. The Sync FET Ramp and IDE calculation are only available in Normal mode. They are not compatible with the Cycle by Cycle Fault module.

However, in discontinuous mode, the SR FET needs to be turned off before the end of the period. The UCD3138 hardware provides an automatic function to make this easier. In this case, the falling edge of DPWMB is adjusted, as shown below:

Sync FET Ramp and IDE Calculation

Figure 2-10. SyncFET IDE (Normal Mode)

The digital hardware implements the equation Db= Da* Kd. The firmware measures Vin and Vout and calculates Kd. For example, for a Buck topology, Kd= (Vin- V FET, Dbis duty cycle of SR FET, Vinis input voltage and V measures the slowly changing Vinand V

, and puts the calculated result into the Kdregister. The DPWM

out

is output voltage. The firmware periodically

out

hardware adjusts Dbevery switching cycle, maintaining proper IDE even during transients which cause rapid changes in Da.

When starting up in prebias mode i.e. with a voltage already present on the outputs, it is difficult to accomplish precise diode emulation (IDE). One solution to this issue is to ramp the voltage up to the target without synchronous rectification (SR), and then to activate SR after the voltage is regulated. When activating or de-activating SR, in order to avoid glitches in the regulated voltage, it is best to gradually increase/decrease the Sync FET on-time. The UCD3138 provides what is termed as Sync FET SoftOn/Soft-Off (ramp) logic to accomplish this. This is documented in Section 3.3.8. The Ramp module in the Front End is used for this function. It will ramp up to either the limits imposed by normal mode, or to the limits imposed by the IDE logic.

With digital IDE enabled, as the system transitions from discontinuous mode into continuous conduction Mode (sync FET is on until end of the period) the IDE will stop reducing the Sync FET pulse width. This is because the reverse conduction through the Sync FET will keep Da and Db the same. It is necessary to detect DCM (Discontinuous Conduction Mode) current levels in the IDE approach. Once these levels are detected, the Sync FET should be ramped down, and then ramped back up with IDE enabled.

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)/V

, where Dais duty cycle of the control

out

Digital Pulse Width Modulator (DPWM)

fs < fr

fs > fr

fs = fr_max

PWM Mode

LLC Mode

Tr = 1/fr

SynFET

Primary

Automatic Mode Switching

2.10 Automatic Mode Switching

Automatic Mode switching enables the DPWM module to switch between modes automatically, with no firmware intervention. This is useful to increase efficiency and power range and also to achieve smooth system performance (such as monotonic start-up) in certain topologies. An example of mode switching in LLC topology is provided next.

2.10.1 Resonant LLC Example

In Resonant LLC topology, three modes are used. At the lowest power, a pulse width modulated mode (Multi Mode) is used. As power increases and frequency decreases, Resonant mode is used. As the frequency gets still lower, resonant mode is still used, however the Sync FET driver changes so that the on-time is fixed and does not increase (SR Pulse Width is clamped). Here are the waveforms for the LLC:

Figure 2-11. Resonant LLC implementation in UCD3138 with Automatic Mode Switching

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2.10.2 Mechanism for Automatic Mode Switching

Many of the configuration parameters for the DPWM, including the mode, are in DPWM Control Register

1. For automatic mode switching, some of these parameters are duplicated in the Auto Config Mid and Auto Config High registers.

If automatic mode switching is enabled, the Filter Duty signal is used to select which of these three registers is used. There are 4 registers which are used to select the points at which the mode switching takes place. They are used as shown below:

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Filter Duty

Low – Lower Threshold

High – Lower Threshold

Control

Auto Config High

Auto Config Mid

High – Upper Threshold

Low – Upper Threshold

Full Range

Automatic Mode Switching

With Hysteresis

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Automatic Mode Switching

As shown, the registers are used in pairs for hysteresis. The transition from Control Register 1 to Auto Config Mid only takes place when the Filter Duty goes above the Low Upper threshold. It does not go back to Control Register 1 until the Low Lower Threshold is passed. This prevents oscillation between modes if the filter duty is close to a mode switching point. In some applications it is necessary to make the values the same, disabling hysteresis. This has to be done to make the DPWM signals from the two modes match properly at the mode switching point.

Figure 2-12. Mechanism for Automatic Mode Switching in UCD3138

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A ON SELECT A OFF SELECT B ON SELECT B OFF SELECT

EGEN A

EGEN B

EDGE GEN

PWM A

PWM B

B SELECT

A SELECT

INTRAMUX

A/B/C (N) A/B/C (N+1) C (N+2) C (N+3)

A(N) B(N) A(N+1) B(N+1)

DPWMC, Edge Generation, IntraMax

2.11 DPWMC, Edge Generation, IntraMax

The UCD3138 has sophisticated hardware for generating complex waveforms beyond the simple DPWMA and DPWMB waveforms already discussed. The DPWMC, the Edge Generation Module, and the IntraMux play a key role in delivering this capability.

DPWMC is a signal inside the DPWM logic. It goes high at the Blanking B begin time, and low at the Blanking B end time.

The Edge Gen module takes DPWMA and DPWMB from its own DPWM module, and the next one, and uses them to generate edges for two outputs. For DPWM3, the DPWM0 is considered to be the next DPWM. Each edge (rising and falling for DPWMA and DPWMB) has 8 options which can cause it. The options are:

• 0 = DPWM(n) A Rising edge

• 1 = DPWM(n) A Falling edge

• 2 = DPWM(n) B Rising edge

• 3 = DPWM(n) B Falling edge

• 4 = DPWM(n+1) A Rising edge

• 5 = DPWM(n+1) A Falling edge

• 6 = DPWM(n+1) B Rising edge

• 7 = DPWM(n+1) B Falling edge The Edge Gen is controlled by the DPWMEDGEGEN register. It also has an enable/disable bit. The IntraMux is controlled by the Auto Config registers. The IntraMux takes signals from multiple DPWMs

and from the Edge Gen. It can be programmed to route these signals to the DPWMA and DPWMB outputs. This is useful for complex topologies like Phase Shifted Full Bridge, especially when they are controlled with automatic mode switching. It is disabled by setting the Intramux to Pass Through mode for each of the DPWM signals, A and B. If the Intra Mux is enabled, high resolution must be disabled.

Here is a drawing of the Edge Gen/Intra Mux:

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Figure 2-13. UCD3138 Edge-Gen & Intra-Mux

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Here is a list of the IntraMux modes for DPWMA:

• 0 = DPWMA(n) pass through (default)

• 1 = Edge-gen output, DPWMA(n)

• 2 = DPWNC(n)

• 3 = DPWMB(n) (Crossover)

• 4 = DPWMA(n+1)

• 5 = DPWMB(n+1)

• 6 = DPWMC(n+1)

• 7 = DPWMC(n+2)

• 8 = DPWMC(n+3) Here is a list of the IntraMux modes for DPWMB:

• 0 = DPWMB(n) pass through (default)

• 1 = Edge-gen output, DPWMB(n)

• 2 = DPWNC(n)

• 3 = DPWMA(n) (Crossover)

• 4 = DPWMA(n+1)

• 5 = DPWMB(n+1)

• 6 = DPWMC(n+1)

• 7 = DPWMC(n+2)

• 8 = DPWMC(n+3) The DPWM number wraps around just like the Edge Gen unit. For DPWM4, DPWM(n+1) is DPWM0,

DPWM(n+2) is DPWM1, and so on. Note that the Fault logic affects the Fault module, which is before the Edge Gen and IntraMux units (refer

to Figure 2-1). The effect of a fault must be calculated taking into account the impact of the Edge Gen and IntraMux units.

Also the GPIO_A_EN & GPIO_B_EN bits inside the DPWMCTRL1 register affect the signal state before the IntraMux unit. So if these bits are meant to be used to turn the DPWM output off, the bits in the original DPWM are supposed to be altered. And not the bits in the DPWM module that the outputs are redirected through.

Time Resolution of Various DPWM Registers

2.12 Time Resolution of Various DPWM Registers

Different registers in the DPWM block have different time resolutions. Pulse widths are generally adjustable in nominal 250 picosecond steps, while period and phase shift are adjustable in 4 nanosecond steps. The sample trigger is adjustable in 16 nanosecond steps.

Table 2-1. DPWM Register Time Resolutions in UCD3138

Phase Trigger, Period, Event1, Blanking A and B Begin Blanking A and B End Minimum Duty Cycle Low Minimum Duty Cycle High Counter Preset

Sample Trigger 1 and 2 16 ns 12 Standard Event2,3,4 250 ps 18 Standard Cycle Adjust A and B 250 ps 16 (signed) Standard Adaptive Sample 16 ns 12 (signed) 16 ns LSbit

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4 ns. 14 Standard

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Time Resolution of Various DPWM Registers

Table 2-1. DPWM Register Time Resolutions in UCD3138 (continued)

Resonant Duty 4 ns.

On the UCD3138, all these registers are aligned so that their bit fields match the scaling, except for the Resonant Duty and Adaptive Sample register. All the registers are unsigned, except for the 2 adjust registers, Resonant Duty and Adaptive Sample register, which are signed to permit positive or negative adjustment.

The Resonant Duty register is used in the UCD3138 LLC reference firmware (implemented in UCD3138LLCEVM-028 EVM) as a 14 bit unsigned register. It can also be used as a 16 bit signed register. See Section 2.21.

This means that the Phase Trigger, Period, and Event1 registers ignore the 4 least significant bits, as shown below:

Table 2-2. DPWM Period Register (DPWMPRD)

All other 4 ns registers with standard alignment are the same.

Bit Number 17:4 3:0

Bit Name PRD RESERVED Access R/W Default 00_0011_0100_0001 0000

16 (signed) or 14 (unsigned)

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4 ns LSbit

The Sample Trigger registers ignore the 6 least significant bits, as shown here:

Table 2-3. DPWM Sample Trigger 1 Register (DPWMSAMPTRIG1)

Bit Number 17:6 5:0

Bit Name SAMPLE_TRIGGER RESERVED Access R/W Default 0000_0010_0000 00_0000

Only the Event 2, 3, and 4 registers use all 18 bits of the field, as shown below.

Table 2-4. DPWM Event 2 Register (DPWMEV2)

Event 3 and 4 are the same, Cycle Adjust registers

only go to bit 15

Bit Number 17:0

Bit Name EVENT2 Access R/W Default 00_0000_0001_0110_0011

This means that in all these registers, each bit has the same weight in terms of time. This makes configuration simpler, since all register loads can use the same time base.

To use this feature, use the .all extension on the register structure. The bit fields do not include the ignored bits.

All of these C statements put 10 microseconds into the respective registers. Note that the “Low” resolution clock is at 4 nanoseconds, and “High” resolution is at 250 picoseconds So the corresponding numbers for the registers are 2,500 and 40,000 respectively.

Dpwm0Regs.DPWMPRD.all = 40000; //includes 4 unused least significant bits Dpwm0Regs.DPWMPRD.bit.PRD = 2500; //only puts in PRD bit field = 40000/16 Dpwm0Regs.DPWMEV1.all = 40000; //includes 4 unused bits Dpwm0Regs.DPWMEV1.bit.EVENT1 = 2500; //EV1 is the only low resolution event register Dpwm0Regs.DPWMEV2.all = 40000; //EV2 is high resolution, so

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Dpwm0Regs.DPWMEV2.bit.EVENT2 = 40000; //both forms are the same Dpwm0Regs.DPWMSAMPTRIG1.all = 40000; //includes 6 unused lsbs Dpwm0Regs.DPWMSAMPTRIG1.bit.SAMPLE_TRIGGER = 625; //needs to be divided by 64 for 6 bits

The adaptive sample and resonant duty registers do not follow the standard bit alignment. Their least significant bits are worth 16 nanoseconds and 4 nanoseconds respectively.

2.13 PWM Counter and Clocks

The PWM counter is the center of the DPWM logic. There is no register that can be read to give the value of the PWM counter, but most events are triggered by it. In all modes it is allowed to count up to the period value, and then restarted at zero. Since it restarts at zero, the period is technically equal to PERIOD + 1. So in the example above, the number should really be 2499. Generally the error is unimportant. In all modes but the resonant modes, the period is a fixed value. In the resonant modes, the period comes from the output of a Filter.

The PWM counter is also restarted by the receipt of a sync signal (if sync is enabled), as shown above in

Section 2.4.

Sync signals received exactly at the end of the period run very smoothly. Sync signals received at other times during the period will restart the counter and the period. The effects of this should be taken into consideration for each application.

Even though the period register has only 14 bits, the PWM counter effectively has 18 bits. Each 4 nanosecond period is subdivided into 16 intervals, nominally 250 picoseconds long. The extra 4 bits representing these intervals are called “high resolution bits”.

PWM Counter and Clocks

2.14 DPWM Registers - Overview

This section discusses each DPWM register, with examples of their use where appropriate. In addition, it interacts with many other peripherals, parts of which are also described below.

2.15 DPWM Control Register 0 (DPWMCTRL0)

The DPWM Control Register 0 is one of 3 DPWM control registers which configure the DPWM. All 3 registers control a variety of DPWM functions. It is not possible to draw a clear dividing line between the 3 registers.

2.15.1 DPWM Auto Config Mid and Max Registers

There are two other registers – DPWMAUTOMAX and DPWMAUTOMID, which have many of the same bits as control register 0.

These two Auto Mode Switching (AMS) registers are used in topologies where the DPWM mode changes automatically as the filter output changes, such as resonant and phase shifted full bridge. See

Section 2.10.2 on the auto switch level registers for more information on mode switching.

Not all bits in DPWMCTRL0 are duplicated in the auto registers. The bits that occur only in DPWMCTRL0 are used for all modes. Bits were selected based on mode switching needs for LLC and PSFB topologies. The following bitfield descriptions tell whether each field occurs in the auto mode switching registers.

2.15.2 Intra Mux

The Intra Mux bit fields, PWM_A_INTRA_MUX, and PWM_B_INTRA_MUX, enable signals from different sources to be multiplexed into the 2 DPWM outputs, A and B. This functionality is used in full and half bridge topologies. The default value for this bit field, 0, causes normal functionality, with the standard DPWM waveforms as described in the mode descriptions above section to appear on the DPWMA and DPWMB pins. For details of the Intra Mux, see Section 2.11.

These fields also occur in the AMS registers.

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DPWM Control Register 0 (DPWMCTRL0)

2.15.3 Cycle by Cycle Current Limit Enable

There are several enable bits related to cycle by cycle current limit: DPWMCTRL0 contains: CBC_PWM_C_EN CBC_PWM_AB_EN CBC_ADV_CNT_EN CBC_SYNC_CUR_LIMIT_EN CBC_BSIDE_ACTIVE_EN All of these bits, except for CBC_BSIDE_ACTIVE_EN also occur in the AMS registers. The first two, CBC_PWM_C_EN and CBC_PWM_AB_EN simply enable cycle by cycle current limit for

their respective signals. In all modes, CBC_PWM_EN has an independent effect on DPWMC. The other bits have no effect on DPWMC The other three bits have different effects in different modes.

Here are the effects:

Normal Mode

In normal mode, a CBC event will cause DPWMA to go low before the time dictated by the CLA. The dead time for DPWMB will be preserved, so the rising edge of DPWMB will be moved forward by the same amount as the falling edge of DPWMA.

There are only two options for setting the CBC bits in normal mode:

1. All cleared, no CBC.

2. Set both CBC_PWM_AB_EN and CBC_ADV_CNT_EN to get CBC CBC_BSIDE_ACTIVE_EN has no effect. Normal mode has some support for negative dead times, as

does the CBC logic. Even negative dead times will be preserved. As seen in Figure 2-14, if there is a negative dead time, the minimum pulse width on DPWMA will be equivalent to the dead time. To preserve a negative dead time, the CBC will trigger a rising edge on DPWMB. After the dead time is expired, then DPWMA will fall.

With a positive dead time, of course, DPWMA will fall with the CBC event, and DPWMB will rise after the dead time:

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CBC Triggered

Positive Dead Time

Negative Dead Time

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DPWM Control Register 0 (DPWMCTRL0)

Figure 2-14.

Even if DPWMB is being used as a GPIO, it is important to program Event 3 for dead times with CBC.

Resonant/Multi Mode

In resonant/multi mode, the systems are often symmetrical. In this case, DPWMB may need to be controlled by the Cycle by Cycle Fault logic as well. Sometimes a shortened on time on one DPWM pin needs to be followed by an equal length on time on the other DPWM pin to prevent an offset from building up in a capacitor or inductor. In this case, it is possible to enable duty cycle matching in these two modes. If DPWMA or DPWMB is cut short by a CBC event, the next pulse, on the other DPWM pin, will also be shortened to the same length.

Here are the states for resonant and multi modes:

• All cleared - no CBC

• Only CBC_PWM_AB_EN set - CBC on A and B, no duty cycle matching

• CBC_PWM_AB_EN and CBC_ADV_CNT_EN set, CBC_BSIDE_ACTIVE_EN not set - CBC on A only

and B duty cycle matches to A

• All three set - CBC on A and B, duty cycle matching both ways

Table 2-5. Truth Table

CBC_PWM_AB_EN CBC_ADV_CNT_EN CBC_BSIDE_ACTIVE_EN CBC A CBC B Duty Match

0 x x 0 0 0 1 0 0 1 1 0 1 1 0 1 M B matches A 1 1 1 1 1 both match

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CBC_SYNC_CUR_LIM_EN is used to control the slave sync. If this bit is set, the slave sync is advanced during current limit. This is not used in any topology configuration at this time. If this bit is set, the sync out pulse from the DPWM will occur if the CBC fault occurs. If the CBC fault does not occur during a period, the sync pulse will occur according to the normal setting of the sync control bit fields.

For more information on cycle by cycle current limit, refer to Chapter 6.

2.15.4 Multi Mode On/Off

The MULTI_MODE_CLA_A_OFF and MULTI_MODE_CLA_B_OFF bits dictate which calculation is used for each DPWM pin in multi mode only. In other modes they should not be set. If the bit is cleared, the ontime of the DPWM pin is controlled by the Filter output. If the bit is set, then the on-time is controlled by the Event registers.

The AMS registers only have MULTI_MODE_CLA_B_OFF, they do not have MULTI_MODE_CLA_A_OFF.

2.15.5 Minimum Duty Mode

The MIN_DUTY_MODE bits select how the DPWM handles minimum duty cycle limits.

• 0 Default - Filter output is passed directly through to the DPWM

• 1 - Filter value passed through if above minimum. If below minimum, no pulse from DPWM

• 2 - Filter value passed through if above minimum. If below minimum, DPWM pulse width = minimum

value There are two registers setting minimum duty and hysteresis: DPWMMINDUTYLOW DPWMMINDUTYHI The Low register sets the point at which the minimum duty mode will take effect as the duty drops. In

mode 2, it also sets the minimum duty. The High register sets the point at which minimum duty mode is exited as the duty goes up. These bits are not duplicated in the AMS registers. These two graphs show modes 1 and 2 with PMMINDUTYLOW at 30, and DPWMMINDUTYHI at 70.

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Min duty mode 2 with hysteresis

100

120

0 10 20 30 40 50 60 70 80 90 100

Filter duty

Output Duty

Duty on way down

duty on way up

Min duty mode 1 with hysteresis

100

120

0 10 20 30 40 50 60 70 80 90 100

Filter Duty

Output Duty

going down to zero

coming up from zero

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DPWM Control Register 0 (DPWMCTRL0)

Figure 2-15. Minimum Duty Mode 1

Figure 2-16. Minimum Duty Mode 2

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DPWM Control Register 0 (DPWMCTRL0)

2.15.6 Master Sync Control Select

The MASTER_SYNC_CNTL_SEL bit selects where the sync output of the DPWM channel comes from. The default value, 0, causes the sync delay to come from the Phase Trigger register. This is useful for

systems that have fixed intervals between phases, such as interleaved PFC and hard switching full bridge. See Section 2.4.

Putting a 1 into this bit causes the master sync output to be controlled by the Filter output. This bit is duplicated in the AMS registers.

2.15.7 Master Sync Slave Enable

Setting the MSYNC_SLAVE_EN bit enables the DPWM channel to be slaved to the sync output of another DPWM channel. This bit works together with the DPWMx_SYNC_SEL bits in the DPWMMUX register in

Chapter 5. The sample code below makes DPWM1 a slave to DPWM0:

LoopMuxRegs.DPWMMUX.bit.DPWM1_SYNC_SEL = 0; //DPWM1 is slave to DPWM0 Dpwm1Regs.DPWMCTRL0.bit.MSYNC_SLAVE_EN = 1; //enable slave mode for DPWM1

This bit is not duplicated in the AMS registers.

2.15.8 D Enable

Normally, the Filter Duty (D) is used to set the on-time of DPWM pins directly. In other words, OnTime = D. The D_ENABLE bit can be used to make the OnTime = 1-D instead.

A default value (0) causes the output of the Filter to be used directly for DPWM output calculations. So in multi mode, for example, the DPWMA and B on-times would increase as the Filter Duty increases.

If the D_ENABLE bit is set, however, the Filter Duty is subtracted from the period register. In this case, as the Filter Duty increases from zero to full range, the on-time will decrease from 100% of the period to 0% of the period.

This bit is not duplicated in the AMS registers.

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2.15.9 Resonant Mode Fixed Duty Enable

The RESON_MODE_FIXED_DUTY_EN bit only controls the duty cycle width in the resonant modes. With the default (0) value, the duty cycle comes from the filter directly. This is for use above the lower resonant frequency, Fmin, and provides a duty cycle that fills half the period minus a fixed dead time.

Setting this bit causes the pulse width to be derived from the Auto Switch High Upper Threshold Register. This bit is generally only set for LLC for the Sync FETs in the mode where the output frequency is below

the lowest resonant frequency of the circuit. At this point any increases in pulse width are not beneficial, so they are stopped. There is also a waveform showing the modes in Section 2.10.1.

This bit is duplicated in the AMS registers.

2.15.10 DPWM A and B Fault Priority

The PWM_A_FLT_POL and PWM_B_FLT_POL bits increase the flexibility of the DPWM by permitting arbitrary output states for the DPWM pins in case of a fault. The values in these bits will also appear on these pins when the DPWM is disabled. These values actually appear on the output of the Fault Module in the DPWM. Therefore, if the IntraMux or Edge Generation units are used, the same value may not appear on the output of the DPWM.

These bits do not affect the DPWM status after device reset. After reset, all DPWM pins are configured as outputs and actively driven low.

These bits are not duplicated in the AMS registers.

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2.15.11 Blank Enable

The BLANK_A_EN and BLANK_B_EN bits are used for fault detection. They work with the blanking registers – See Section 2.26 – to enable blanking for current limit detection. Without blanking, noise may cause false Cycle By Cycle (CBC) fault detection.

These bits are not duplicated in the AMS registers.

2.15.12 DPWM Mode

The PWM_MODE bits select the mode for the DPWM. See Section 2.31 for the mode numbers, and sections above for the descriptions of the various modes.

These bits are duplicated in the AMS registers.

2.15.13 DPWM Invert

The PWM_A_INV and PWM_B_INV bits invert the output of the DPWMA and DPWMB pins. These bits do not affect the DPWM status after device reset however. After reset, all DPWM pins

configured as outputs which are actively driving low. These bits are not duplicated in the AMS registers.

2.15.14 1.15.14 Filter Enable (CLA_EN)

In the past, the filter was called a Control Law Accelerator, so for historical reasons, the Filter Enable bit is called CLA_EN. This bit, when set, causes the DPWM to take its input from a Filter. Otherwise, the DPWM output comes from the DPWM registers only.

This bit is duplicated in the AMS registers. The filter which controls each DPWM is selected by the DPWMx_FILTER_SEL bit in the DPWMMUX

DPWM Control Register 0 (DPWMCTRL0)

2.15.15 DPWM Enable

The PWM_EN bit, when set enables the DPWM channel. If it is 0 (default), the DPWM outputs are set to the value in the DPWM Fault Polarity bits (Section 2.15.10).

Note that if edge generation is enabled, the bits will be controlled by the edge gen logic. To make the bits go to the desired values, it will be necessary to clear the EDGE_EN bit in DPWMEDGEGEN.

This bit occurs only in the Control 0 register, not in the AMS registers.

2.16 DPWM Control Register 1

Like DPWMCRTL0, the DPWMCTRL1 register contains a wide assortment of control bits for the DPWM.

2.16.1 Period Counter Preset Enable

The PRESET_EN bit adds flexibility for systems with multiple DPWM modules that have different period starting times. It can be used to start up all DPWMs simultaneously, even if their periods do not start at the same times. It can also be used for synchronizing these DPWMs.

Normally, the period counter is reset to zero by three events

1. DPWM ENABLE

2. Sync Received (slave mode enabled)

3. Counter reaches Period Register value If PRESET_EN is enabled, this changes:

1. DPWM_ENABLE – Period Counter set to preset value

2. Sync Received (slave mode enabled) – Period Counter set to preset value

3. Counter reaches Period Register value – Period counter set to zero

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2.16.2 Sync FET Ramp Enable

The SYNC_FET_EN bit enables the Sync FET Ramp logic to take control of DPWM B. For more on the Ramp logic, see Section 3.3.8. The Front End which provides the Ramp data is selected in the DPWMMUX register in the Loop Mux. The following code enables Sync FET Ramp for DPWM0, and sets up Front End 0’s Ramp Engine to provide the ramp source.

LoopMuxRegs.DPWMMUX.bit.DPWM0_SYNC_FET_SEL = 0;

//use ramp engine on Front End 03

Dpwm0Regs.DPWMCTRL1.bit.SYNC_FET_EN = 1; //enable sync FET ramp

The Sync FET Ramp logic ramps the pulse width of DPWMB up from a starting point to a width controlled by Normal mode, or by the IDE function, if enabled. It only works in Normal mode.

2.16.3 Burst Mode Enable

Setting the BURST_EN bit enables burst (light load) mode for this DPWM. For more information on Light load mode, see the light load section.

2.16.4 Current/Flux Balancing Duty Adjust

Setting the CLA_DUTY_ADJ_EN bit enables the Current Balancing logic to modify the input to the DPWM so that current controlled by this DPWM can be balanced with the current controlled by another DPWM in the same UCD3138. For more information, see the Current Balancing section.

2.16.5 1.16.5 Sync Out Divisor Selection

The SYNC_OUT_DIV_SEL bit field selects a divisor generating the sync out pulse on the external sync out pin. It is only effective on the sync out, not on internal chip sync signals sent to other DPWMs.

The divisor has 4 bits, and a range from 1 to 16 for the divisor. The divisor = SYNC_OUT_DIV_SEL + 1. So 0 in the bit field would give a divisor of 1, 1 gives a divisor of 2, and so on.

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2.16.6 FIlter Scale

The CLA_SCALE bits control shifting of the Filter Duty output before it is used by the DPWM. Shifts available range from a 3 bit right shift to a 3 bit left shift. The Filter Period is not scaled by these bits.

The default value, 0, causes no shift. For the shift table, see Section 2.31.2. This can be used in complex topologies where the same filter output is needed for different circuits at

different frequencies. It can also be used to change the overall gain of the Filter.

2.16.7 External Sync Enable

Setting the EXT_SYNC_EN bit causes the DPWM to use the Sync In pin as a source for Sync.

2.16.8 Cycle By Cycle B Side Active Enable

Setting the EXT_SYNC_EN bit causes the DPWM to use the Sync In pin as a source for Sync.

2.16.9 Auto Mode Switching Enable

The AUTO_MODE_SEL bit, when set, enables auto mode switching.

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2.16.10 1.16.10 Event Update Select

The EVENT_UP_SEL enables 4 different modes of DPWM Event Updating. The DPWM needs a period of 72 nanoseconds (nominal) to update its timing for the next period. During this period, it takes the latest Filter outputs and any firmware changes to register values and recalculates the timing of the DPWM signals. The time selected for update should NOT have any DPWM edges moving in or out of the

window.

If DPWM edges move in or out of the Event Update Window, those transitions may be missed, leading to DPWM pulses longer or shorter than expected.

The modes are:

• 0 - As soon as Filter calculation is done

• 1 - At end of period (starts at end of period, and extends 72ns into start of new period)

• 2 - At time set by sample trigger 2

• 3 - At both End of Period and at time set by sample trigger 2 Note that all modes except for mode 1 make the Event Update timing dependent on the position of the

sample trigger. For most topologies, mode 1 is used, and dead times or minimum pulse widths are used to keep moving edges out of the first 72nsec of the DPWM period. Please refer to the reference firmware code provided with UCD3138 EVMs for specific guidance regarding each topology.

DPWM Control Register 1

CAUTION

2.16.11 Check Override

The CHECK_OVERRIDE bit, when set, overrides the internal DPWM checking. The DPWM checking will prevent invalid placement of Event settings/period settings or invalid configurations.

Setting this bit may be necessary for some topologies.

2.16.12 Global Period Enable

The GLOBAL_PERIOD_EN bit, if set, enables the use of the Global Period register to provide the period for this DPWM. It is intended for use with systems which use multiple DPWMs and have need for frequency dithering. This makes it possible to change the frequency of multiple DPWMs at one location.

For more information, see 5.8 PWM Global Period Register (PWMGLBPRD).

2.16.13 Using DPWM Pins as General Purpose I/O

There are 6 bits in DPWMCTRL1 which can be used to make the DPWM pins into general purpose I/O pins:

These bits take effect immediately.

• PWM_A_OE – 0 makes DPWMA into an output if enabled as a GPIO, 1 makes it an input

• PWM_B_OE – 0 makes DPWMB into an output if enabled as a GPIO, 1 makes it an input

• GPIO_A_VAL – Value put on DPWMA if it is an output

• GPIO_B_VAL – Value put on DPWMA if it is an output GPIO_A_EN – 1 enables DPWMA as a GPIO GPIO_B_EN – 1 enables DPWMB as a GPIO In addition, there are 2 bits in the DPWMOVERFLOW register which are also used for GPIO:

• GPIO_A_IN – reports level on DPWM_A pin if used as input

• GPIO_B_IN – reports level on DPWM_B pin if used as input

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2.16.14 High Resolution enable/disable

There are 5 bits which all enable/disable High Resolution Mode in some way or another

• PWM_HR_MULT_OUT_EN – Set only for multi mode

• HIRES_SCALE (2 bits) – Sets resolution of DPWM high res block

• ALL_PHASE_CLK_ENA – enables all phases or only needed phases

• HIRES_DIS – disables high res logic As a general rule, all can be disabled when high resolution is not possible, and all should be enabled

when high resolution is possible and required.

2.16.15 Asynchronous Protection Disable

The PWM_A_PROT_DIS and PWM_B_PROT_DIS bits disable asynchronous protection on their respective pins. Please consult to the reference firmware code provided with UCD3138 EVMs for specific guidance on whether to set these bits or not in the desired topology.

2.16.16 Single Frame Enable

The SFRAME_EN bit enables a single frame to be output from the DPWM. It is useful for putting out a single pulse on the DPWM, and triggering a single Front End and Filter cycle. It can be used, for example, when measuring input voltage on an isolated supply. To use Single Frame enable, first initialize the DPWM module and set the SFRAME_EN bit, and enable the DPWM globally. To actually start the single frame, set the PWM_EN bit. This will trigger a single frame.

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2.17 DPWM Control Register 2

The DPWMCTRL2 register, like the other 2 control registers, has a wide selection of bit fields.

2.17.1 External Synchronization Input Divide Ratio

The SYNC_IN_DIV_RATIO bit field has 4 bits, which are initialized to zero at reset. They set the divide ratio for the synchronization both from the outside and from another DPWM. The divide ratio is the bit field value plus 1. So 0 is divide by 1, 1 divide by 2, and so on.

2.17.2 Resonant Deadtime Compensation Enable

Setting the RESON_DEADTIME_COMP_EN bit enables a dead time adjustment to the CLA Duty signal from the Filter. This compensation, which only has an effect in resonant mode, makes it possible to have constant, fixed, symmetrical dead time in resonant mode for the full range of frequencies. Generally this is the best configuration for LLC. If the bit is not set, the CLA Duty Signal is used without adjustment. This leads to DPWMA putting out 50% Duty + Cycle Adjust A, and DPWMB putting 50% - dead time + Cycle Adjust B, which cannot be made to yield a symmetrical signal on A and B over the frequency range for LLC.

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2.17.3 Filter Duty Select

The FILTER_DUTY_SEL bit field has 2 bits, selecting from 3 modes. These modes select what value is sent to the Resonant Duty input of the Filter Duty multiplicand multiplexer. For example, if LoopMux.FILTERMUX.FILTER0_PER_SEL is set to 0, and the OUTPUT_MULT_SEL bits for Filter 0 are set to 3, then the FILTER_DUTY_SEL will select the Filter Duty multiplicand. This value will be multiplied by the output of the filter to scale it appropriately for the DPWM.

Bit Value Multiplier for Filter Value Result

0 DPWM Period Maximum Filter output gives 100% duty cycle 1 Event 2 Maximum Filter output gives Event 2 duty cycle 2 Resonant Duty Register Maximum Filter output gives value of Resonant Duty Register 3 Not applicable

Mode 2 is used for LLC with Resonant Mode.

2.17.4 IDeal Diode Emulation (IDE) Enable for PWMB

Setting the IDE_DUTY_B_EN bit enables the digital IDE logic to take control of DPWM B. The IDE logic is used to make sync FETs turn off at the perfect times, emulating an ideal diode (one with lower voltage drop). See Section 2.9 for more details.

2.17.5 Sample Trigger 1 Oversampling

As mentioned earlier, the DPWM module generates signals to generate a sample trigger in the Error ADC in the Front End. The DPWMs can also provide oversampling function in co-ordination with the sample triggers. The SAMP_TRIG1_OVERSAMPLE bit field permits oversampling of 2, 4, and 8 samples in the Front End. The samples are equally distributed in time, starting at the start of the period, and with the last sample at the Sample Trigger 1 point.

The values are:

• 0 – 1 sample at the sample trigger time.

• 1 – 1 sample at 1/2 of the sample trigger time, and one at the sample trigger time

• 2 – 4 samples at 1/4, 1/2, 3/4, and full sample trigger time

• 3 – 8 samples at 1/8, 1/4, 3/8, 1/2, 5/8, 3/4, 7/8 and full sample trigger Sample trigger 1 can be used either to trigger a complete cycle with Front End and Filter, or it can be used

for spatial averaging. See Chapter 3, especially Section 3.1.5.

DPWM Control Register 2

2.17.6 Sample Trigger 1 Mode

In addition to oversampling, Sample Trigger 1 offers several modes of calculation. The SAMPLE_TRIG1_MODE bit field selects from 4 of these:

• 0 – Sample Trigger is set using Sample Trigger register (DPWMSAMPTRIG1)

• 1 – Sample Trigger = Event 1 + (DUTY/2) + Adaptive Offset where Duty is most recent Filter Duty

• 2 – Sample Trigger = Event 1 + (DUTY/2) + Adaptive Offset where Duty is Filter Duty from last cycle

• 3 – Sample Trigger = Event 1 + DUTY + Adaptive Offset + Fixed Offset where Filter Duty is from last

cycle On the diagrams earlier in this chapter, option 1 is called Adaptive Sample Trigger B, and option 3 is

called Adaptive Sample Trigger A. The Adaptive Offset comes from the DPWMADAPTIVE register, which is an 11 bit signed register. Without

the Adaptive Offset, the sample trigger will be in the middle of the on-time for DPWMA in Normal and Multi Modes. The Adaptive Offset is used to correct for system delays in gate drivers, FET turn-on times and voltage and current sensing circuits. Using the Adaptive Offset properly can put the sample trigger in the middle of the voltage or current on-time. The adaptive offset register has the same resolution as the Sample Trigger Register – 16 nanoseconds. The adaptive register, though is not mapped the same. Bit 0 is the first usable bit. See Section 2.31 for more information.

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DPWM Control Register 2

Note that using adaptive offset will cause the phase delay of the control loop to change somewhat as the duty cycle changes.

The Fixed Offset in mode 3 is a value of 4. This is added to the DPWMADAPTIVE Register and to the Event 1 and Duty Terms.

2.17.7 Sample Trigger Enable Bits

Sample Trigger 2 is only driven by the Sample Trigger 2 Register - DPWMSAMPTRIG2. Setting the SAMPLE_TRIG_2_EN bit enables it.

SAMPLE_TRIG_1_EN enables Sample Trigger 1.

2.18 Period and Event Registers

The period and event registers DPWMPRD, DPWMEV1, DPWMEV2, DPWMEV3, and DPWMEV4 have different effects in different modes. See DPWM Modes below for more information about each mode. Generally the registers work somewhat as described above in Section 2.2. Often, the pulse widths are controlled by the filter, and the differences between Event Registers are used as dead times.

2.19 Phase Trigger Registers

The DPWMPHASETRIG register is a low resolution (4 ns.) register. It dictates the number of 4 ns. steps between the start of the period and the output of a sync pulse for synchronizing a slave DPWM. See

Section 2.4.

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2.20 Cycle Adjust Registers

DPWMCYCADJA and DPWMCYCADJB are registers that are added to the Filter Duty before the DPWM pulse width is calculated. They have different effects in different modes, see the DPWM Mode sections above. They are signed high resolution registers so that the duty can be increased or decreased from the Filter value. They only have 16 bits, so they cannot adjust the full 18 bit range of the DPWM. But their range is still +-8 milliseconds, which is typically more than a whole switching period

High resolution is 250 picosec, and the range of a signed 16 bit value is ±215. So

215x 250 psec = 8.192 msec (1)

2.21 Resonant Duty Register

This register is used in LLC topologies to produce the correct Filter Duty output. The Filter output is multiplied by this register to calculate Filter Duty. In the LLC reference firmware (UCD3138LLCEVM-028) it is set to 1/2 of the maximum desired period. In this case, bits 13-0 are used as an unsigned number. To enable this mode, the DPWM must be in Resonant Mode, and the FILTER_DUTY_SEL field in DPWMCTRL2 must be set to a 2.

If FILTER_DUTY_SEL is set to 0 or 1 and the DPWM is in resonant mode, the 16 bit signed contents of the register are added to the Filter Period value, and the result is used for the DPWM Period. This is another option for adjusting the resonant mode timing to match other modes across a mode shift. This mode is not currently used in any topologies.

2.22 DPWM Fault Control Register

See Chapter 6 for information on the DPWMFLTCTRL register.

2.23 DPWM Overflow Register

The DPWMOVERFLOW register has, as already mentioned, 2 bits which give the input status of the DPWM pins when they are used as general purpose I/O.

It also has 6 bits which indicate that the protection logic for the DPWM has detected overflows.

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2.24 DPWM Interrupt Register

The DPWMINT register has interrupt enable bits, interrupt flags, one interrupt flag clear bit, and one interrupt scale register.

For more information on the enable bits and flags related to faults, see Section 6.11.

2.24.1 DPWM Period Interrupt Bits

There are three bit fields related to the Period interrupt. PRD is the flag which indicates that there is a period interrupt occurring. It is only a strobed signal, so it is

very unlikely that it will ever be read as set. If the interrupt bit is set, and no other bits are set, this means it is the period bit which has set it.

PRD_INT_EN enables the period interrupt. PRD_INT_SCALE programs a divider for the period interrupt. The selections range from an interrupt every

period to an interrupt every 256 periods. See the DPWM Reference section for the table. Note that if the DPWM is disabled, under most circumstances, it will generate a period interrupt

continuously, if the interrupt is enabled.

2.24.2 Mode Switching Interrupt Bits

There are three bit fields related to the Mode Switching Interrupt. See Section 2.29 DPWM Auto Switch Registers, for more detail on Mode Switching. MODE_SWITCH goes high when the DPWM has switched modes. MODE_SWITCH_INT_EN enables this interrupt. A rising edge on MODE_SWITCH_FLAG_CLR clears the MODE_SWITCH bit. This bit is not auto cleared,

so it will be necessary to clear it with firmware before the next rising edge.

DPWM Interrupt Register

2.24.3 INT Bit

The INT bit shows that one or more of the interrupt flags is set and enabled, and the DPWM is sending an interrupt to the Central Interrupt Module (CIM). When the interrupt bits are cleared, so is the INT bit.

2.25 DPWM Counter Preset Register

If enabled, the DPWMCNTPRE register is loaded into the Period Counter at DPWM startup or on a rising sync edge. This is used for applications requiring complex synchronization and phase shifting between DPWMs. See 2.16.1 Period Counter Preset Enable for more information.

2.26 Blanking Registers

There are 4 Blanking Registers in each DPWM: DPWMBLKABEG DPWMBLKBBEG DPWMBLKAEND DPWMBLKBEND There are two blanking periods, A and B, which both have a beginning and an end, measured in 4

nanosecond steps of the period counter. These registers are used to blank out CBC signals during noisy times of the signal, for example around

hard switching. See the Fault Mux section for more information. They can also be used to align current limit response times between multiple DPWMs with different dead times.

The Blank B values are also used to generate the DPWMC signal for the IntraMux for complex topologies. See Section 2.15.2.

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DPWM Adaptive Sample Register

2.27 DPWM Adaptive Sample Register

The DPWMADAPTIVE register is used in adaptive sample trigger modes. See Figure 9-11 for more information.

2.28 DPWM Fault Status Register

The DPWMFLTSTAT Register has bits which indicate faults, IDE detection, and Burst mode detection. See Chapter 6 for Faults, Section 6.9 for IDE, and Section 5.10 for Burst mode.

2.29 DPWM Auto Switch Registers

For an overview of what these registers do, see Section 2.10. There are 4 Auto Switch threshold registers: DPWMAUTOSWIHIUPTHRESH DPWMAUTOSWIHILOWTHRESH DPWMAUTOSWILOUPTHRESH DPWMAUTOSWILOLOWTHRESH These registers are used in topologies which dynamically switch from one DPWM mode to another, such

as Phase Shifted Full Bridge and LLC. They control which one of three registers sets many of the DPWM control bits. There are 4 registers so that each of the 2 dividing lines can have hysteresis.

The three registers are: DPWMCTRL0 AUTOCONFIGMID AUTOCONFIGMAX If the Filter input to the DPWM goes above DLWMAUTOSWIHIUPTHRESH, then the AUTOCONFIGMAX

register is used until the Filter input goes below the DPWMAUTOSWIHILOWTHRESH register value. Below this value the AUTOCINFIGMID control bits are used, until the Filter value goes below

DPWMAUTOSWILOLOWTHRESH. Below this value, DPWMCTRL0 is used. Mode switching is enabled by setting the AUTO_MODE_SEL bit in DPWMCTRL1. Making the waveforms

transition smoothly across the mode switching boundary can be complex.

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2.30 DPWM Edge PWM Generation Register

DPWMEDGEGEN is used for complex systems like phase shifted full bridge, in conjunction with the IntraMux. It enables each edge to be generated from a wide selection of sources in a very flexible manner. The options are described in Section 2.11. Section 2.31 shows the specific bit assignments.

High Resolution should also be disabled if the Edge Generator is enabled.

2.31 DPWM 0-3 Registers Reference

2.31.1 DPWM Control Register 0 (DPWMCTRL0)

Address 00050000 – DPWM 3Control Register 0 Address 00070000 – DPWM 2 Control Register 0 Address 000A0000 – DPWM 1 Control Register 0 Address 000D0000 – DPWM 0 Control Register 0

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DPWM 0-3 Registers Reference

Figure 2-17. DPWM Control Register 0 (DPWMCTRL0)

31 28 27 24

PWM_B_INTRA_MUX PWM_A_INTR4_MUX

R/W-0000 R/W-0000

23 22 21 20 19 18 17 16

CBC_PWM_C

_EN

R/W-000 R/W-0 R/W-0 R/W-0 R/W-0 R/W-00 R/W-0

15 14 13 12 11 10 9 8

MSYNC

_SLAVE_EN

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

7 4 3 2 1 0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

MULTI_MODE

_CLA_B_OFF

D_ENABLE CBC_SYNC

MULTI_MODE

_CLA_A_OFF

_CUR_LIMIT

_EN

PWM_MODE PWM_B_INV PWM_A_INV CLA_EN PWM_EN

R/W-0010 R/W-0 R/W-0 R/W-1 R/W-0

CBC_PWM_AB

_EN

RESON_MODE

_FIXED

_DUTY_EN

CBC_ADV

_CNT_EN

PWM_B_FLT

_POL

MIN_DUTY_MODE MASTER

PWM_A_FLT

_POL

BLANK_B_EN BLANK_A_EN

Table 2-6. DPWM Control Register 0 (DPWMCTRL0) Register Field Descriptions

Bit Field Type Reset Description

31-28 PWM_B_INTRA

_MUX

27-24 PWM_A_INTR4

_MUX

23 CBC_PWM_C_EN R/W 000

22 MULTI_MODE

_CLA_B_OFF

21 MULTI_MODE

_CLA_A_OFF

R/W 0000

R/W 0

Interchanges DPWM signals post edge generation 0 = Pass-through (Default) 1 = Edge-gen output, this module 2 = PWM-C, this module 3 = Crossover, this module 4 = Pass-through below A 5 = Pass-through below B 6 = Pass-through below C 7 = Pass-through below level-2 C 8 = Pass-through below level-3 C

Combines DPWM signals are prior to HR module 0 = Pass-through (Default) 1 = Edge-gen output, this module 2 = PWM-C, this module 3 = Crossover, this module 4 = Pass-through below A 5 = Pass-through below B 6 = Pass-through below C 6 = Pass-through below C 7 = Pass-through below level-2 C 8 = Pass-through below level-3 C

Sets if Fault CBC changes output waveform for PWM-C 0 = PWM-C unaffected by Fault CBC (Default) 1 = PWM-C affected by Fault CBC

Configures control of PWM B output in Multi-Output Mode when CLA_ENABLE is asserted

0 = PWM B pulse width controlled by Filter Calculation (Default) 1 = PWM B pulse width controlled by Event3 and Event4 registers

Configures control of PWM A output in Multi-Output Mode when CLA_ENABLE is asserted

0 = PWM A pulse width controlled by Filter Calculation (Default) 1 = PWM A pulse width controlled by Event1 and Event2 registers

_SYNC_CNTL

_SEL

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Table 2-6. DPWM Control Register 0 (DPWMCTRL0) Register Field Descriptions (continued)

Bit Field Type Reset Description

20 CBC_PWM_AB

_EN

19 CBC_ADV_CNT

_EN

18-17 MIN_DUTY

_MODE

16 MASTER_SYNC

_CNTL_SEL

15 MSYNC_SLAVE

_EN

14 D_ENABLE R/W 0

13 CBC_SYNC_CUR

_LIMIT_EN

12 RESON_MODE

_FIXED_DUTY _EN

11 PWM_B_FLT_POL R/W 0

10 PWM_A_FLT_POL R/W 0

9 BLANK_B_EN R/W 0

8 BLANK_A_EN R/W 0

7-4 PWM_MODE R/W 0010

R/W 0

R/W 00

R/W 0

Sets if Fault CBC changes output waveform for PWM-A and PWM-B 0 = PWM-A and PWM-B unaffected by Fault CBC (Default) 1 = PWM-A and PWM-B affected by Fault CBC

Selects cycle-by-cycle of operation

Normal Mode

0 = CBC disabled (Default) 1 = CBC enabled

Multi and Resonant Modes

0 = PWM-A and PWM-B operate independently (Default) 1 = PWM-A and PWM-B pulse matching enabled

Minimum Duty Cycle Mode 00 = Suppression of minimum duty cycles is disabled (Default) 01 = CLA value is clamped to zero when below input value is less than

MIN_DUTY_LOW 10 = CLA value is clamped to MIN_DUTY_LOW register value when input value is

less than MIN_DUTY_LOW Configures master sync location

0 = Master Sync controlled by Phase Trigger Register (Default) 1 = Master Sync controlled by CLA value

Multi-Sync Slave Mode Control 0 = PWM not synchronized to another PWM channel (Default) 1 = Enable Multi-Sync Slave Mode, current channel will be slaved from

corresponding channel Converts CLA duty value to DPWM as period-CLA duty value

0 = Value used for event calculations if CLA Duty (Default) 1 = Value used for event calculations is period minus CLA duty value

Sets how current limit affects slave sync 0 = Slave sync is unaffected during current limit (Default) 1 = Slave sync is advanced during current limit.

Configures how duty cycle is controlled in Resonance Mode 0 = Resonant mode duty cycle set by Filter duty (Default) 1 = Resonant mode duty cycle set by Auto Switch High Register

Sets the fault output polarity during a disable condition (i.e. fault or module disabled) 0 = PWM B fault output polarity is set to low (Default) 1 = PWM B fault output polarity is set to high

Sets the fault output polarity during a disable condition (i.e. fault or module disabled) 0 = PWM A fault output polarity is set to low (Default) 1 = PWM A fault output polarity is set to high

Comparator Blanking Window B Enable 0 = Comparator Blanking Window for PWM-B Disabled (Default) 1 = Comparator Blanking Window for PWM-B Enabled

Comparator Blanking Window A Enable 0 = Comparator Blanking Window for PWM-A Disabled (Default) 1 = Comparator Blanking Window for PWM-B Enabled

DPWM Mode 0 = Normal Mode 1 = Resonant Mode 2 = Multi-Output Mode (Default) 3 = Triangular Mode 4 = Leading Mode

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Table 2-6. DPWM Control Register 0 (DPWMCTRL0) Register Field Descriptions (continued)

Bit Field Type Reset Description

3 PWM_B_INV R/W 0

2 PWM_A_INV R/W 0

1 CLA_EN R/W 1

0 PWM_EN R/W 0

PWM B Output Polarity Control 0 = Non-inverted PWM B output (Default) 1 = Inverts PWM B output

PWM A Output Polarity Control 0 = Non-inverted PWM A output (Default) 1 = Inverted PWM A output

CLA Processing Enable 0 = Generate PWM waveforms from PWM Register values 1 = Enable CLA input (Default)

PWM Processing Enable 0 = Disable PWM module, outputs zero (Default) 1 = Enable PWM operation

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2.31.2 DPWM Control Register 1 (DPWMCTRL1)

Address 00050004 – DPWM 3 Control Register 1 Address 00070004 – DPWM 2 Control Register 1 Address 000A0004 – DPWM 1 Control Register 1 Address 000D0004 – DPWM 0 Control Register 1

Figure 2-18. DPWM Control Register 1 (DPWMCTRL1)

31 30 29 28 27 24

PRESET_EN SYNC_FET

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0000

23 21 20 19 18 17 16

15 14 13 12 11 10 9 8

CHECK

_OVERRIDE

R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

7 6 5 4 3 2 1 0

PWM_HR

_MULTI_OUT

_EN

R/W-0 R/W-0 R/W-0 R/W-0 R/W-00 R/W-1 R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

_EN

CLA_SCALE EXT_SYNC

R/W-000 R/W-0 R/W-0 R/W-0 R/W-01

GLOBAL

_PERIOD_EN

SFRAME_EN PWM_B_PROT

BURST_EN CLA_DUTY

PWM_B_OE PWM_A_OE GPIO_B_VAL GPIO_B_EN GPIO_A_VAL GPIO_A_EN

_DIS

_ADJ_EN

_EN

PWM_A_PROT

_DIS

CBC_BSIDE

_ACTIVE EN

HIRES_SCALE ALL_PHASE

SYNC_OUT_DIV_SEL

AUTO_MODE

_SEL

EVENT_UP_SEL

_CLK_ENA

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HIRES_DIS

Table 2-7. DPWM Control Register 1 (DPWMCTRL1) Register Field Descriptions

Bit Field Type Reset Description

31 PRESET_EN R/W 0

30 SYNC_FET_EN R/W 0

29 BURST_EN R/W 0

28 CLA_DUTY_ADJ

_EN

27-24 SYNC_OUT_DIV

_SEL

R/W 0

R/W 0000

Counter Preset Enable 0 = Counter reset to 0 upon detection of sync (Default) 1 = Counter preset to Preset Count Value upon detection of sync

SyncFET Mode Enabled 0 = SyncFET Mode Disabled (Default) 1 = SyncFET Mode Enabled (Default)

Burst (Light Load) Mode Detection Enable 0 = Burst Mode (Light Load) Detection disabled (Default) 1 = Burst Mode (Light Load) Detection enabled

Enables CLA Duty Adjust from Current/Flux Balancing 0 = CLA Duty Adjust not enabled (Default) 1 = CLA Duty Adjust enabled

Sets the divider for generating the Sync Out pulse. 0000 = Sync Out generated on every switching cycle (Default) 0001 = Sync Out generated once every 2 switching cycles 0010 = Sync Out generated once every 3 switching cycles ………. 1111 = Sync Out generated once every 16 switching cycles

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Table 2-7. DPWM Control Register 1 (DPWMCTRL1) Register Field Descriptions (continued)

Bit Field Type Reset Description

23-21 CLA_SCALE R/W 000

20 EXT_SYNC_EN R/W 0

19 CBC_BSIDE

_ACTIVE_EN

18 AUTO_MODE

_SEL

17-16 EVENT_UP_SEL R/W 01

15 CHECK

_OVERRIDE

14 GLOBAL_PERIOD

_ENGLOBAL _PERIOD_EN

13 PWM_B_OE R/W 0

12 PWM_A_OE R/W 0

11 GPIO_B_VAL R/W 0

10 GPIO_B_EN R/W 0

9 GPIO_A_VAL R/W 0

8 GPIO_A_EN R/W 0

R/W 0

Scaling for CLA Input Data 000 = CLA Value (Default) 001 = CLA Value multiplied by 2 010 = CLA Value divided by 2 011 = CLA Value multiplied by 4 100 = CLA Value divided by 4 101 = CLA Value multiplied by 8 110 = CLA Value divided by 8 111 = CLA Value

Slave DPWM to external sync 0 = DPWM not synchronized to external sync (Default) 1 = Slave DPWM to external sync

Sets if CBC responds to Fault CBC when PWM-B is active, only available in Multi and Reson modes

0 = Response to Fault CBC when PWM-A active (Default) 1 = Response to Fault CBC when PWM-A or PWM-B active

Auto Switching Mode Select 0 = Auto Switching Mode disabled (Default) 1 = Auto Switching Mode enabled

Update End Period Mode 00 = Events updated anytime 01 = Events updated at End of Period (Default) 10 = Events updated at count value equal to Sample Trigger 2 register 11 = Events updated at End of Period and Sample Trigger 2 position

PWM Check Override 0 = DPWM checks mathematical settings within module, correct placement of Event

settings/period settings. Invalid configurations are not allowed. 1 = Overrides checking for invalid configurations and turns off PWM mathematical

checking functions (Default) 0 = Event calculations use DPWM Period register (Default)

1 = Event calculations use Global Period register

Direction for PWM B pin 0 = PWM B configured as output (Default) 1 = PWM B configured as input

Direction for PWM A pin 0 = PWM A configured as output (Default) 1 = PWM A configured as input

Sets value of PWM B output in GPIO mode 0 = PWM B driven low in GPIO mode (Default) 1 = PWM B driven high in GPIO mode

Enables GPIO mode for PWM B output 0 = PWM B in DPWM mode (Default) 1 = PWM B in GPIO mode

Sets value of PWM A output in GPIO mode 0 = PWM A driven low in GPIO mode (Default) 1 = PWM A driven high in GPIO mode

Enables GPIO mode for PWM A output 0 = PWM A in DPWM mode (Default) 1 = PWM A in GPIO mode

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Table 2-7. DPWM Control Register 1 (DPWMCTRL1) Register Field Descriptions (continued)

Bit Field Type Reset Description

7 PWM_HR_MULTI

_OUT_EN

6 SFRAME_EN R/W 0

5 PWM_B_PROT

_DIS

4 PWM_A_PROT

_DIS

3-2 HIRES_SCALE R/W 00

1 ALL_PHASE_CLK

_ENA

0 HIRES_DIS R/W 0

R/W 0

R/W 1

Control bit for Hi-Res Block 0 = Disabled (Default) 1 = Enabled

PWM Single Step Frame Mode Enable 0 = Disable Single Frame Mode (Default) 1 = Enable Single Step Frame Mode. One EADC sample is requested, CLA then

Filters, then one PWM duty cycle performed, then wait on Single Frame Trigger toggle before advancing to next frame.

PWM B Asynchronous Protection Disable 0 = Allows asynchronous protection to turn off PWM B Output (Default) 1 = Disables asynchronous protection from turning off PWM B Output

PWM A Asynchronous Protection Disable 0 = Allows asynchronous protection to turn off PWM A Output (Default) 1 = Disables asynchronous protection from turning off PWM A Output

Determines resolution of high resolution steps 00 = Resolution of 16 phases. Full resolution enabled. Resolution step = PCLK/16

(Default) 11 = Resolution of 2 phases. Resolution step = PCLK/2 10 = Resolution of 4 phases. Resolution step = PCLK/4 01 = Resolution of 8 phases. Resolution step = PCLK/8 00 = Resolution of 16 phases. Full Resolution enabled. Resolution step = PCLK/16

High Speed Oscillator Phase Enable 0 = Enables only required phases of clock when needed 1 = Enables all phases of high resolution clock from oscillator (Default)

PWM High Resolution Disable 0 = Enable High Resolution logic (Default) 1 = Disable High Resolution logic

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2.31.3 DPWM Control Register 2 (DPWMCTRL2)

Address 00050008 – DPWM 3 Control Register 2 Address 00070008 – DPWM 2 Control Register 2 Address 000A0008 – DPWM 1 Control Register 2 Address 000D0008 – DPWM 0 Control Register 2

Figure 2-19. DPWM Control Register 2 (DPWMCTRL2)

15 14 13 12 11 10 9 8

SYNC_IN_DIV_RATIO Reserved RESON_DEAD

R/W-0000 R-0 R/W-0 R/W-00

7 6 5 4 3 2 1 0

IDE_DUTY_B

_EN

R/W-0 R-0 R/W-00 R/W-00 R/W-0 R/W-1

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Reserved SAMPLE_TRIG1

_OVERSAMPLE

SAMPLE_TRIG1_MODE SAMPLE_TRIG

TIME_COMP

_EN

Table 2-8. DPWM Control Register 2 (DPWMCTRL2) Register Field Descriptions

Bit Field Type Reset Description

15-12 SYNC_IN_DIV

_RATIO 11 Reserved R 0 10 RESON_DEAD

TIME_COMP_EN

9-8 FILTER_DUTY

_SEL

7 IDE_DUTY_B_EN R/W 0

6 Reserved R 0 5-4 SAMPLE_TRIG1

_OVERSAMPLE

3-2 SAMPLE_TRIG1

_MODE

R/W 0000

R/W 0

R/W 00

Sets the number of syncs to be masked before a resync

Sets the method at which High Side CLA-Duty is used in calculations 0 = CLA Duty from Filter (Default)

1 = CLA Duty from Filter minus deadtime adjustment Sets which register is sent to the Resonant Duty input of the Filter. Settings of 0 and

1 enable the 16 bit signed value of the Resonant Duty register to be added to the Filter Period value for period adjustment in resonant mode.

0 = PWM Period Register (Default) 1 = Event 2 2 = DPWM Resonant Duty Register (Bits 13:0)

IDE Duty Cycle Side B Enable 0 = Disabled (Default) 1 = Enabled

Oversample Select for Sample Trigger 1 00 = Trigger an EADC Sample at PWM Sample Trig Register value (Default) 01 = Trigger an EADC Sample at PWM Sample Trig Register value and at PWM

Sample Trig Register value divided by 2 10 = Trigger a EADC Sample at PWM Sample Trig Register value, at PWM Sample

Trig Register value divided by 2 and at PWM Sample Trig Register value divided by 4

11 = Trigger a EADC Sample at PWM Sample Trig Register value, at PWM Sample Trig Register value divided by 2, at PWM Sample Trig Register value divided by 4 and at PWM Sample Trig Register value divided by 8

Mode select for Sample Trigger 1 00 = Trigger value is set using PWM Sample Trig Register value (Default) 01 = Trigger value is adaptive midpoint (EV1+CLA_DUTY/2 + Adaptive Offset) and

uses current CLA value at update event 10 = Trigger value is adaptive midpoint (EV1+CLA_DUTY/2 + Adaptive Offset) and

uses previous CLA value at update event 11 = Trigger value is adaptive midpoint (EV1+CLA_DUTY + Fixed offset + Adaptive

Offset) and uses current CLA value at update event

FILTER_DUTY_SEL

_2_EN

SAMPLE_TRIG

_1_EN

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Table 2-8. DPWM Control Register 2 (DPWMCTRL2) Register Field Descriptions (continued)

Bit Field Type Reset Description

1 SAMPLE_TRIG_2

_EN

0 SAMPLE_TRIG_1

_EN

R/W 0

R/W 1

Sample Trigger 2 Enable 0 = Disable Sample Trigger 2 (Default) 1 = Enable Sample Trigger 2

Sample Trigger 1 Enable 0 = Disable Sample Trigger 1 1 = Enable Sample Trigger 1 (Default)

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2.31.4 DPWM Period Register (DPWMPRD)

Address 0005000C – DPWM 3 Period Register Address 0007000C – DPWM 2 Period Register Address 000A000C – DPWM 1 Period Register Address 000D000C – DPWM 0 Period Register

Figure 2-20. DPWM Period Register (DPWMPRD)

17 4 3 0

PRD Reserved

R/W-00 0011 0100 0001 R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 2-9. DPWM Period Register (DPWMPRD) Register Field Descriptions

Bit Field Type Reset Description

17-4 PRD R/W 00 0011

0100 0001

3-0 Reserved R 0

PWM Period. Low resolution register, last 4 bits are read-only.

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2.31.5 DPWM Event 1 Register (DPWMEV1)

Address 00050010 – DPWM 3 Event 1 Register Address 00070010 – DPWM 2 Event 1 Register Address 000A0010 – DPWM 1 Event 1 Register Address 000D0010 – DPWM 0 Event 1 Register

Figure 2-21. DPWM Event 1 Register (DPWMEV1)

17 4 3 0

EVENT1 Reserved

R/W-00 0000 0001 0100 R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 2-10. DPWM Event 1 Register (DPWMEV1) Register Field Descriptions

Bit Field Type Reset Description

17-4 EVENT1 R/W 00 0000

0001 0100

3-0 Reserved R 0

Configures the location of Event 1. Low resolution register, last 4 bits are unused.

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2.31.6 DPWM Event 2 Register (DPWMEV2)

Address 00050014 – DPWM 3 Event 2 Register Address 00070014 – DPWM 2 Event 2 Register Address 000A0014 – DPWM 1 Event 2 Register Address 000D0014 – DPWM 0 Event 2 Register

Figure 2-22. DPWM Event 2 Register (DPWMEV2)

17 0

EVENT2

R/W-0 0000 0011 0000 0000

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 2-11. DPWM Event 2 Register (DPWMEV2) Register Field Descriptions

Bit Field Type Reset Description

17-0 EVENT2 R/W 0 0000

0011 0000 0000

Configures the location of Event 2. Value equals number of PCLK clock periods in Bits 17:4 and number of high resolution clock phases of PCL in Bits 3:0 (dependent on Bits 3:2 of DPWM Control Register 2).

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2.31.7 DPWM Event 3 Register (DPWMEV3)

Address 00050018 – Loop 4 DPWM Event 3 Register Address 00070018 – Loop 3 DPWM Event 3 Register Address 000A0018 – Loop 2 DPWM Event 3 Register Address 000D0018 – Loop 1 DPWM Event 3 Register

Figure 2-23. DPWM Event 3 Register (DPWMEV3)

17 0

EVENT3

R/W-00 0000 0011 1110 0000

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 2-12. DPWM Event 3 Register (DPWMEV3) Register Field Descriptions

Bit Field Type Reset Description

17-0 EVENT3 R/W 00 0000

0011 1110 0000

Configures the location of Event 3. Value equals number of PCLK clock periods in Bits 17:4 and number of high resolution clock phases of PCL in Bits 3:0.

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2.31.8 DPWM Event 4 Register (DPWMEV4)

Address 0005001C – Loop 4 DPWM Event 4 Register Address 0007001C – Loop 3 DPWM Event 4 Register Address 000A001C – Loop 2 DPWM Event 4 Register Address 000D001C – Loop 1 DPWM Event 4 Register

Figure 2-24. DPWM Event 4 Register (DPWMEV4)

17 0

EVENT4

R/W-00 0000 0111 0000 0000

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 2-13. DPWM Event 4 Register (DPWMEV4) Register Field Descriptions

Bit Field Type Reset Description

17-0 EVENT4 R/W 00 0000

0111 0000 0000

Configures the location of Event 4. Value equals number of PCLK clock periods in Bits 17:4 and number of high resolution clock phases of PCL in Bits 3:0.

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2.31.9 DPWM Sample Trigger 1 Register (DPWMSAMPTRIG1)

Address 00050020 – DPWM 3 Sample Trigger 1 Register Address 00070020 – DPWM 2 Sample Trigger 1 Register Address 000A0020 – DPWM 1 Sample Trigger 1 Register Address 000D0020 – DPWM 0 Sample Trigger 1 Register

Figure 2-25. DPWM Sample Trigger 1 Register (DPWMSAMPTRIG1)

17 6 5 0

SAMPLE_TRIGGER Reserved

R/W-0000 0010 0000 R-00 0000

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 2-14. DPWM Sample Trigger 1 Register (DPWMSAMPTRIG1) Register Field Descriptions

Bit Field Type Reset Description

17-6 SAMPLE_

TRIGGER

5-0 Reserved R 00 0000

R/W 0000

0010 0000

Configures the location of the sample trigger within a PWM period. Value equals the number of PCLK clock periods. Enables start of conversion for EADC. Low resolution register, last 6 bits are read-only.

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2.31.10 DPWM Sample Trigger 2 Register (DPWMSAMPTRIG2)

Address 00050024 – DPWM 3 Sample Trigger 1 Register Address 00070024 – DPWM 2 Sample Trigger 1 Register Address 000A0024 – DPWM 1 Sample Trigger 1 Register Address 000D0024 – DPWM 0 Sample Trigger 1 Register

Figure 2-26. DPWM Sample Trigger 2 Register (DPWMSAMPTRIG2)

17 6 5 0

SAMPLE_TRIGGER Reserved

R/W-0000 0010 0000 R-00 0000

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 2-15. DPWM Sample Trigger 2 Register (DPWMSAMPTRIG2) Register Field Descriptions

Bit Field Type Reset Description

17-6 SAMPLE_

TRIGGER

5-0 Reserved R 00 0000

R/W 0000

0010 0000

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2.31.11 DPWM Phase Trigger Register (DPWMPHASETRIG)

Address 00050028 – DPWM 3 Phase Trigger Register Address 00070028 – DPWM 2 Phase Trigger Register Address 000A0028 – DPWM 1 Phase Trigger Register Address 000D0028 – DPWM 0 Phase Trigger Register

Figure 2-27. DPWM Phase Trigger Register (DPWMPHASETRIG)

17 4 3 0

PHASE_TRIGGER Reserved

R/W-00 0000 0000 0000 R-0000

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 2-16. DPWM Phase Trigger Register (DPWMPHASETRIG) Register Field Descriptions

Bit Field Type Reset Description

17-4 PHASE_TRIGGER R/W 00 0000

0000 0000

3-0 Reserved R 0000

Configures the phase trigger delay within multi-output mode. Value equals the number of PCLK clock periods. Low resolution register, last 4 bits are read-only.

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2.31.12 DPWM Cycle Adjust A Register (DPWMCYCADJA)

Address 0005002C – DPWM 3 Cycle Adjust A Register Address 0007002C – DPWM 2 Cycle Adjust A Register Address 000A002C – DPWM 1 Cycle Adjust A Register Address 000D002C – DPWM 0 Cycle Adjust A Register

Figure 2-28. DPWM Cycle Adjust A Register (DPWMCYCADJA)

15 0

CYCLE_ADJUST_A

R/W-0000 0000 0000 0000

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 2-17. DPWM Cycle Adjust A Register (DPWMCYCADJA) Register Field Descriptions

Bit Field Type Reset Description

15-0 CYCLE_ADJUST_AR/W 0000

0000 0000 0000

Adjusts PWM A output signal. 16-bit signed number allows output signal to be delayed or sped up.

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2.31.13 DPWM Cycle Adjust B Register (DPWMCYCADJB)

Address 00050030 – DPWM 3 Cycle Adjust B Register Address 00070030 – DPWM 2 Cycle Adjust B Register Address 000A0030 – DPWM 1 Cycle Adjust B Register Address 000D0030 – DPWM 0 Cycle Adjust B Register

Figure 2-29. DPWM Cycle Adjust B Register (DPWMCYCADJB)

15 0

CYCLE_ADJUST_B

R/W-0000 0000 0000 0000

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 2-18. DPWM Cycle Adjust B Register (DPWMCYCADJB) Register Field Descriptions

Bit Field Type Reset Description

15-0 CYCLE_ADJUST_BR/W 0000

0000 0000 0000

Adjusts the PWM B output signal. 16-bit signed number allows output signal to be delayed or sped up.

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2.31.14 DPWM Resonant Duty Register (DPWMRESDUTY)

Address 00050034 – DPWM 3 Resonant Duty Register Address 00070034 – DPWM 2 Resonant Duty Register Address 000A0034 – DPWM 1 Resonant Duty Register Address 000D0034 – DPWM 0 Resonant Duty Register

Figure 2-30. DPWM Resonant Duty Register (DPWMRESDUTY)

15 0

RESONANT_DUTY

R/W-0000 0000 0000 0000

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 2-19. DPWM Resonant Duty Register (DPWMRESDUTY) Register Field Descriptions

Bit Field Type Reset Description

15-0 RESONANT

_DUTY

R/W 0000

0000 0000 0000

Controls the DPWM duty. 16-bit signed number is used as a Filter Output Multiplier in Resonant Mode.

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2.31.15 DPWM Fault Control Register (DPWMFLTCTRL)

Figure 2-31. DPWM Fault Control Register (DPWMFLTCTRL)

31 30 29 28 24

ALL_FAULT

_EN

R/W-0 R/W-0 R-0 R/W-0 0000

23 22 21 20 16

15 13 12 8

7 6 5 4 3 2 1 0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Bit Field Type Reset Description

31 ALL_FAULT_EN R/W 0

30 CBC_FAULT_EN R/W 0

29 Reserved R 0 28-24 CBC_MAX

23-21 Reserved R 000 20-16 AB_MAX_COUNT R/W 0 0000

15-13 Reserved R 000 12-8 A_MAX_COUNT R/W 0 0000

7-5 Reserved R 000 4-0 B_MAX_COUNT R/W 0 0000

CBC_FAULT

_EN

Reserved AB_MAX_COUNT

R-000 R/W-0 0000

Reserved A_MAX_COUNT

R-000 R/W-0 0000

Reserved B_MAX_COUNT

R-000 R/W-0 0000

Reserved CBC_MAX_COUNT

Table 2-20. DPWM Fault Control Register (DPWMFLTCTRL) Register Field Descriptions

DPWM Fault Module enable 0 = All DPWM Fault Modules disabled (Default) 1 = All DPWM Fault Modules enabled

Cycle by cycle Fault Enable 0 = Cycle by cycle just shortens DPWM pulses 1 = Consecutive cycle by cycle events beyond CBC_MAX_COUNT will cause the

DPWM to shut off as with any other fault.

_COUNT

R/W 0 0000

Cycle-by-Cycle Fault Count, sets the number of received sequential faults on Cycleby-Cycle Fault input before asserting the fault

Fault AB Count, sets the number of received sequential faults on Fault AB input before asserting the fault

Fault A Count, sets the number of received sequential faults on Fault A input before asserting the fault

Fault B Count, sets the number of received sequential faults on Fault B input before asserting the fault

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2.31.16 DPWM Overflow Register (DPWMOVERFLOW)

Address 0005003C – DPWM 3 Overflow Register Address 0007003C – DPWM 2 Overflow Register Address 000A003C – DPWM 1 Overflow Register Address 000D003C – DPWM 0 Overflow Register

Figure 2-32. DPWM Overflow Register (DPWMOVERFLOW)

7 6 5 4 3 0

PWM_B

_CHECK

R-0 R-0 R-0 R-0 R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Bit Field Type Reset Description

7 PWM_B_CHECK R 0

6 PWM_A_CHECK R 0

5 GPIO_B_IN R 0

4 GPIO_A_IN R 0

3-0 OVERFLOW R 0

PWM_A

_CHECK

GPIO_B_IN GPIO_A_IN OVERFLOW

Table 2-21. DPWM Overflow Register (DPWMOVERFLOW) Register Field Descriptions

Value of PWM B internal check 0 = Passed checks 1 = Failed checks (override required to enable output)

Value of PWM B input 0 = Passed check 1 = Failed check (override required to enable output)

Value of PWM B input 0 = Low signal on PWM B 1 = High signal on PWM B

Value of PWM A input 0 = Low signal on PWM A 1 = High value on PWM A

PWM Event 4 Overflow Status 0 = CLA Event 4 has not overflowed 1 = Overflow condition found on CLA Event 4 OVERFLOW[2] – CLA Event 4 Overflow Status 0 = PWM Event 4 has not overflowed 1 = Overflow condition found on PWM Event 4 OVERFLOW[1] – CLA Event 3 Overflow Status 0 = CLA Event 3 has not overflowed 1 = Overflow condition found on CLA Event 3 OVERFLOW[0] – CLA Event 2 Overflow Status 0 = CLA Event 2 has not overflowed 1 = Overflow condition found on CLA Event 2

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2.31.17 DPWM Interrupt Register (DPWMINT)

Address 00050040 – DPWM 3 Interrupt Register Address 00070040 – DPWM 2 Interrupt Register Address 000A0040 – DPWM 1 Interrupt Register Address 000D0040 – DPWM 0 Interrupt Register

Figure 2-33. DPWM Interrupt Register (DPWMINT)

22 21 20 19 18 17 16

MODE_SWITCH FLT_A FLT_B FLT_AB FLT_CBC PRD INT

R-0 R-0 R-0 R-0 R-0 R-0 R-0

15 12 11 10 9 8

Reserved MODE_

R/W-0000 R/W-0 R/W-0 R/W-0 R/W-0

7 6 5 4 3 0

FLT_B_INT_EN FLT_AB_INT_ENFLT_CBC_INT

_EN

R/W-0 R/W-0 R/W-0 R/W-0 R/W-1111

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

PRD_INT_EN PRD_INT_SCALE

SWITCH_FLAG

_CLR

Table 2-22. DPWM Interrupt Register (DPWMINT) Register Field Descriptions

MODE_

SWITCH_FLAG

_EN

MODE_

SWITCH_INT

_EN

FLT_A_INT_EN

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Bit Field Type Reset Description

22 MODE_SWITCH R 0

21 FLT_A R 0

20 FLT_B R 0

19 FLT_AB R 0

18 FLT_CBC R 0

17 PRD R 0

16 INT R 0

15-12 Reserved R 0000 11 MODE_SWITCH_

FLAG_CLR

10 MODE_SWITCH_

FLAG_EN

R/W 0

Mode Switching Flag 0 = Flag is not asserted 1 = Flag is set

Fault A Flag 0 = Flag is not asserted 1 = Flag is set

Fault B Flag 0 = Flag is not asserted 1 = Flag is set

Fault AB Flag 0 = Flag is not asserted 1 = Flag is set

Fault Cycle-by-Cycle Flag 0 = Flag is not asserted 1 = Flag is set

PWM Period Interrupt Flag 0 = PWM Period Interrupt Flag is not asserted 1 = PWM Period Interrupt Flag is set

Interrupt Out 0 = INT is not asserted 1 = INT is set

Mode Switching Flag Clear 0 = (Default) 1 = Risedge 0-1 clears flag generated.

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Table 2-22. DPWM Interrupt Register (DPWMINT) Register Field Descriptions (continued)

Bit Field Type Reset Description

9 MODE_SWITCH

_INT_EN

8 FLT_A_INT_EN R/W 0

7 FLT_B_INT_EN R/W 0

6 FLT_AB_INT_EN R/W 0

5 FLT_CBC_INT_EN R/W 0

4 PRD_INT_EN R/W 0

3-0 PRD_INT_SCALE R/W 1111

R/W 0

Mode Switching Interrupt Enable 0 = Interrupt is not enabled (Default) 1 = Interrupt is enabled

Fault A Flag Interrupt Enable 0 = Interrupt is not enabled (Default) 1 = Interrupt is enabled

Fault B Flag Interrupt Enable 0 = Interrupt is not enabled (Default) 1 = Interrupt is enabled

Fault AB Flag Interrupt Enable 0 = Interrupt is not enabled (Default) 1 = Interrupt is enabled

Fault Cycle-by-Cycle Flag Interrupt Enable 0 = Interrupt is not enabled (Default) 1 = Interrupt is enabled

PWM Period Interrupt Enable 0 = Disables generation of periodic PWM interrupt (Default) 1 = Enables generation of periodic PWM interrupt

This value scales the period interrupt signal from an interrupt every switching cycle to 16 switching cycles

0000 = Period Interrupt generated every switching cycle (Default) 0001 = Period Interrupt generated once every 2 switching cycles 0010 = Period Interrupt generated once every 4 switching cycles 0011 = Period Interrupt generated once every 6 switching cycles 0100 = Period Interrupt generated once every 8 switching cycles 0101 = Period Interrupt generated once every 16 switching cycles 0110 = Period Interrupt generated once every 32 switching cycles 0111 = Period Interrupt generated once every 48 switching cycles 1000 = Period Interrupt generated once every 64 switching cycles 1001 = Period Interrupt generated once every 80 switching cycles 1010 = Period Interrupt generated once every 96 switching cycles 1011 = Period Interrupt generated once every 128 switching cycles 1100 = Period Interrupt generated once every 160 switching cycles 1101 = Period Interrupt generated once every 192 switching cycles 1110 = Period Interrupt generated once every 224 switching cycles 1111 = Period Interrupt generated once every 256 switching cycles

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2.31.18 DPWM Counter Preset Register (DPWMCNTPRE)

Address 00050044 – DPWM 3 Counter Preset Register Address 00070044 – DPWM 2 Counter Preset Register Address 000A0044 – DPWM 1 Counter Preset Register Address 000D0044 – DPWM 0 Counter Preset Register

Figure 2-34. DPWM Counter Preset Register (DPWMCNTPRE)

17 4 3 0

PRESET Reserved

R/W-00 0000 0000 0000 R-0000

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 2-23. DPWM Counter Preset Register (DPWMCNTPRE) Register Field Descriptions

Bit Field Type Reset Description

17-4 PRESET R/W 00 0000

0000 0000

3-0 Reserved R 0000

Counter preset value, counter reset to this value upon detection of sync when PRESET_EN bit in DPWMCTRL2 is enabled. Low resolution register, last 4 bits are read-only.

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2.31.19 DPWM Blanking A Begin Register (DPWMBLKABEG)

Address 00050048 – DPWM 3 Blanking A Begin Register Address 00070048 – DPWM 2 Blanking A Begin Register Address 000A0048 – DPWM 1 Blanking A Begin Register Address 000D0048 – DPWM 0 Blanking A Begin Register

Figure 2-35. DPWM Blanking A Begin Register (DPWMBLKABEG)

17 4 3 0

BLANK_A_BEGIN Reserved

R/W-00 0000 0000 0000 R-0000

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 2-24. DPWM Blanking A Begin Register (DPWMBLKABEG) Register Field Descriptions

Bit Field Type Reset Description

17-4 BLANK_A_BEGIN R/W 00 0000

0000 0000

3-0 Reserved R 0000

Configures start of Comparator Blanking Window for PWM A. Low resolution register, last 4 bits are read-only.

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2.31.20 DPWM Blanking A End Register (DPWMBLKAEND)

Address 0005004C – DPWM 3 Blanking A End Register Address 0007004C – DPWM 2 Blanking A End Register Address 000A004C – DPWM 1 Blanking A End Register Address 000D004C – DPWM 0 Blanking A End Register

Figure 2-36. DPWM Blanking A End Register (DPWMBLKAEND)

17 4 3 0

BLANK_A_END Reserved

R/W-00 0000 0000 0000 R-0000

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 2-25. DPWM Blanking A End Register (DPWMBLKAEND) Register Field Descriptions

Bit Field Type Reset Description

17-4 BLANK_A_END R/W 00 0000

0000 0000

3-0 Reserved R 0000

Configures end of Comparator Blanking Window for PWM A. Low resolution register, last 4 bits are read-only.

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2.31.21 DPWM Blanking B Begin Register (DPWMBLKBBEG)

Address 00050050 – DPWM 3 Blanking B Begin Register Address 00070050 – DPWM 2 Blanking B Begin Register Address 000A0050 – DPWM 1 Blanking B Begin Register Address 000D0050 – DPWM 0 Blanking B Begin Register

Figure 2-37. DPWM Blanking B Begin Register (DPWMBLKBBEG)

17 4 3 0

BLANK_B_BEGIN Reserved

R/W-00 0000 0000 0000 R-0000

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 2-26. DPWM Blanking B Begin Register (DPWMBLKBBEG) Register Field Descriptions

Bit Field Type Reset Description

17-4 BLANK_B_BEGIN R/W 00 0000

0000 0000

3-0 Reserved R 0000

Configures start of Comparator Blanking Window for PWM B. Low resolution register, last 4 bits are read-only.

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2.31.22 DPWM Blanking B End Register (DPWMBLKBEND)

Address 00050054 – DPWM 3 Blanking B End Register Address 00070054 – DPWM 2 Blanking B End Register Address 000A0054 – DPWM 1 Blanking B End Register Address 000D0054 – DPWM 0 Blanking B End Register

Figure 2-38. DPWM Blanking B End Register (DPWMBLKBEND)

17 4 3 0

BLANK_B_END Reserved

R/W-00 0000 0000 0000 R-0000

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 2-27. DPWM Blanking B End Register (DPWMBLKBEND) Register Field Descriptions

Bit Field Type Reset Description

17-4 BLANK_B_END R/W 00 0000

0000 0000

3-0 Reserved R 0000

Configures end of Comparator Blanking Window for PWM B. Low resolution register, last 4 bits are read-only.

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2.31.23 DPWM Minimum Duty Cycle High Register (DPWMMINDUTYHI)

Address 00050058 – DPWM 3 Minimum Duty Cycle High Register Address 00070058 – DPWM 2 Minimum Duty Cycle High Register Address 000A0058 – DPWM 1 Minimum Duty Cycle High Register Address 000D0058 – DPWM 0 Minimum Duty Cycle High Register

Figure 2-39. DPWM Minimum Duty Cycle High Register (DPWMMINDUTYHI)

17 4 3 0

MIN_DUTY_HIGH Reserved

R/W-00 0000 0000 0000 R-0000

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 2-28. DPWM Minimum Duty Cycle High Register (DPWMMINDUTYHI) Register Field

Descriptions

Bit Field Type Reset Description

17-4 MIN_DUTY_HIGH R/W 00 0000

0000 0000

3-0 Reserved R 0000

Configures upper threshold for minimum duty cycle logic. Low resolution register, last 4 bits are read-only.

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2.31.24 DPWM Minimum Duty Cycle Low Register (DPWMMINDUTYLO)

Address 0005005C – DPWM 3 Minimum Duty Cycle Low Register Address 0007005C – DPWM 2 Minimum Duty Cycle Low Register Address 000A005C – DPWM 1 Minimum Duty Cycle Low Register Address 000D005C – DPWM 0 Minimum Duty Cycle Low Register

Figure 2-40. DPWM Minimum Duty Cycle Low Register (DPWMMINDUTYLO)

17 4 3 0

MIN_DUTY_LOW Reserved

R/W-00 0000 0000 0000 R-0000

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 2-29. DPWM Minimum Duty Cycle Low Register (DPWMMINDUTYLO) Register Field

Descriptions

Bit Field Type Reset Description

17-4 MIN_DUTY_LOW R/W 00 0000

0000 0000

3-0 Reserved R 0000

Configures lower threshold for minimum duty cycle logic. Low resolution register, last 4 bits are read-only.

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2.31.25 DPWM Adaptive Sample Register (DPWMADAPTIVE)

Address 00050060 – DPWM 3 Adaptive Sample Register Address 00070060 – DPWM 2 Adaptive Sample Register Address 000A0060 – DPWM 1 Adaptive Sample Register Address 000D0060 – DPWM 0 Adaptive Sample Register

Figure 2-41. DPWM Adaptive Sample Register (DPWMADAPTIVE)

11 0

ADAPT_SAMP

R/W-0000 0000 0000

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 2-30. DPWM Adaptive Sample Register (DPWMADAPTIVE) Register Field Descriptions

Bit Field Type Reset Description

11-0 ADAPT_SAMP R/W 0000

0000 0000

Configures Adaptive Sample Adjust

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2.31.26 DPWM Fault Status (DPWMFLTSTAT)

Address 00050064 – DPWM 3 Fault Input Status Register Address 00070064 – DPWM 2 Fault Input Status Register Address 000A0064 – DPWM 1 Fault Input Status Register Address 000D0064 – DPWM 0 Fault Input Status Register

Figure 2-42. DPWM Fault Status (DPWMFLTSTAT)

5 4 3 2 1 0

BURST IDE_DETECT FLT_A FLT_B FLT_AB FLT_CBC

R-0 R-0 R-0 R-0 R-0 R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 2-31. DPWM Fault Status (DPWMFLTSTAT) Register Field Descriptions

Bit Field Type Reset Description

5 BURST R 0

4 IDE_DETECT R 0

3 FLT_A R 0

2 FLT_B R 0

1 FLT_AB R 0

0 FLT_CBC R 0

Burst Mode Detection Status 0 = Burst Mode Detection is not asserted 1 = Burst Mode Detection is set

IDE Detection Status (from Analog Comparators) 0 = IDE Detection is not asserted 1 = IDE Detection is set

Fault A Detection Statu 0 = Fault A Detection is not asserted 1 = Fault A Detection is set

Fault B Detection Status 0 = Fault B Detection is not asserted 1 = Fault B Detection is set

Fault AB Detection Statu 0 = Fault AB Detection is not asserted 1 = Fault AB Detection is set

Current Limit Detection Status 0 = Current Limit Detection is not asserted 1 = Current Limit Detection is set

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2.31.27 DPWM Auto Switch High Upper Thresh Register (DPWMAUTOSWHIUPTHRESH)

Address 00050068 – DPWM 3 Auto Switch High Upper Thresh Register Address 00070068 – DPWM 2 Auto Switch High Upper Thresh Register Address 000A0068 – DPWM 1 Auto Switch High Upper Thresh Register Address 000D0068 – DPWM 0 Auto Switch High Upper Thresh Register

Figure 2-43. DPWM Auto Switch High Upper Thresh Register (DPWMAUTOSWHIUPTHRESH)

17 4 3 0

AUTO_SWITCH_HIGH_UPPER Reserved

R/W-00 0000 0000 0000 R-0000

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 2-32. DPWM Auto Switch High Upper Thresh Register (DPWMAUTOSWHIUPTHRESH)

Bit Field Type Reset Description

17-4 AUTO_SWITCH

_HIGH_UPPER

3-0 Reserved R 0000

R/W 00 0000

0000 0000

Configures upper threshold for Auto Switch Mode High operation. Mode switching does not occur between Auto Switch High Upper and Auto Switch High Lower thresholds. Low resolution register, last 4 bits are read-only.

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2.31.28 DPWM Auto Switch High Lower Thresh Register (DPWMAUTOSWHILOWTHRESH)

Address 0005006C – DPWM 3 Auto Switch High Lower Thresh Register Address 0007006C – DPWM 2 Auto Switch High Lower Thresh Register Address 000A006C – DPWM 1 Auto Switch High Lower Thresh Register Address 000D006C – DPWM 0 Auto Switch High Lower Thresh Register

Figure 2-44. DPWM Auto Switch High Lower Thresh Register (DPWMAUTOSWHILOWTHRESH)

17 4 3 0

AUTO_SWITCH_HIGH_LOWER Reserved

R/W-00 0000 0000 0000 R-0000

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 2-33. DPWM Auto Switch High Lower Thresh Register (DPWMAUTOSWHILOWTHRESH)

Bit Field Type Reset Description

17-4 AUTO_SWITCH

_HIGH_UPPER

3-0 Reserved R 0000

R/W 00 0000

0000 0000

Configures lower threshold for Auto Switch Mode High operation. Mode switching does not occur between Auto Switch High Upper and Auto Switch High Lower thresholds. Low resolution register, last 4 bits are read-only.

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Texas Instruments UCD3138 Technical Reference Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

1.1 Scope of This Document

Introduction

1.2 A Guide to Other Documentation for all Members of UCD3138 Family of Products

Digital Pulse Width Modulator (DPWM)

2.1 DPWM Block Diagram

2.2 Introduction to DPWM (DPWM Multi-Mode, Open Loop)

2.3 DPWM Normal Mode

2.4 DPWM Phase Shift Mode

2.5 DPWM Multiple Output Mode (Multi Mode)

2.6 DPWM Resonant Mode

2.7 Triangular Mode

2.8 DPWM Leading Edge Mode

2.9 Sync FET Ramp and IDE Calculation

2.10 Automatic Mode Switching

2.10.1 Resonant LLC Example

2.10.2 Mechanism for Automatic Mode Switching

2.11 DPWMC, Edge Generation, IntraMax

2.12 Time Resolution of Various DPWM Registers

2.13 PWM Counter and Clocks

2.14 DPWM Registers - Overview

2.15 DPWM Control Register 0 (DPWMCTRL0)

2.15.1 DPWM Auto Config Mid and Max Registers

2.15.2 Intra Mux

2.15.3 Cycle by Cycle Current Limit Enable

2.15.4 Multi Mode On/Off

2.15.5 Minimum Duty Mode

2.15.6 Master Sync Control Select

2.15.7 Master Sync Slave Enable

2.15.8 D Enable

2.15.9 Resonant Mode Fixed Duty Enable

2.15.10 DPWM A and B Fault Priority

2.15.11 Blank Enable

2.15.12 DPWM Mode

2.15.13 DPWM Invert

2.15.14 1.15.14 Filter Enable (CLA_EN)

2.15.15 DPWM Enable

2.16 DPWM Control Register 1

2.16.1 Period Counter Preset Enable

2.16.2 Sync FET Ramp Enable

2.16.3 Burst Mode Enable

2.16.4 Current/Flux Balancing Duty Adjust

2.16.5 1.16.5 Sync Out Divisor Selection

2.16.6 FIlter Scale

2.16.7 External Sync Enable

2.16.8 Cycle By Cycle B Side Active Enable

2.16.9 Auto Mode Switching Enable

2.16.10 1.16.10 Event Update Select

2.16.11 Check Override

2.16.12 Global Period Enable

2.16.13 Using DPWM Pins as General Purpose I/O

2.16.14 High Resolution enable/disable

2.16.15 Asynchronous Protection Disable

2.16.16 Single Frame Enable

2.17 DPWM Control Register 2

2.17.1 External Synchronization Input Divide Ratio

2.17.2 Resonant Deadtime Compensation Enable

2.17.3 Filter Duty Select

2.17.4 IDeal Diode Emulation (IDE) Enable for PWMB

2.17.5 Sample Trigger 1 Oversampling

2.17.6 Sample Trigger 1 Mode

2.17.7 Sample Trigger Enable Bits

2.18 Period and Event Registers

2.19 Phase Trigger Registers

2.20 Cycle Adjust Registers

2.21 Resonant Duty Register

2.22 DPWM Fault Control Register

2.23 DPWM Overflow Register

2.24 DPWM Interrupt Register

2.24.1 DPWM Period Interrupt Bits

2.24.2 Mode Switching Interrupt Bits

2.24.3 INT Bit

2.25 DPWM Counter Preset Register

2.26 Blanking Registers

2.27 DPWM Adaptive Sample Register

2.28 DPWM Fault Status Register

2.29 DPWM Auto Switch Registers