TEXAS INSTRUMENTS TVP7002 Technical data

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TRIPLE 8-/10-BIT 165-/110-MSPS,

VIDEO AND GRAPHICS DIGITIZER WITH HORIZONTAL PLL

FEATURES

• Analog Channels • Horizontal PLL

– –6-dB to 6-dB Analog Gain – Fully Integrated Horizontal PLL for Pixel – Analog Input Multiplexers (MUXs) – Automatic Video Clamp – Three Digitizing Channels, Each With

Independently Controllable Clamp, Gain, Offset, and Analog-to-Digital Converter (ADC) – 5-Bit Programmable Subpixel Accurate

– Clamping: Selectable Clamping Between

Bottom Level and Mid-Level • Output Formatter

– Offset: 1024-Step Programmable RGB or – Supports 20-bit 4:2:2 Outputs With

YPbPr Offset Control Embedded Syncs – Gain: 8-Bit Programmable Gain Control – Support for RGB/YCbCr 4:4:4 and YCbCr – ADC: 8-/10-Bit 165-/110-MSPS ADC – Automatic Level Control (ALC) Circuit – Composite Sync: Integrated

Sync-on-Green Extraction From

Green/Luminance Channel – Support for DC- and AC-Coupled Input

Signals – Supports Component Video Standards

480i, 576i, 480p, 576p, 720p, 1080i, and

1080p – Supports PC Graphics Inputs up to UXGA

– Programmable RGB-to-YCbCr Color

Space Conversion

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TVP7002

SLES206 – MAY 2007

Clock Generation

– 12-MHz to 165-MHz Pixel Clock Generation

From HSYNC Input

– Adjustable Horizontal PLL Loop Bandwidth

for Minimum Jitter

Positioning of Sampling Phase

4:2:2 Output Modes to Reduce Board Traces

– Dedicated DATACLK Output With

Programmable Output Polarity for Easy Latching of Output Data

• System

– Industry-Standard Normal/Fast I2C

Interface With Register Readback

Capability – Space-Saving 100-Pin TQFP Package – Thermally-Enhanced PowerPAD™ Package

for Better Heat Dissipation – Glueless Interface to TVP9000/9001 Video

Processor Back-End Devices

APPLICATIONS

• LCD TV/Monitors/Projectors • Digital Image Processing

• DLP TV/Projectors • Video Capture/Video Editing

• PDP TV/Monitors • Scan Rate/Image Resolution Converters

• LCOS TV/Monitors • Video Conferencing

• PCTV Set-Top Boxes • Video/Graphics Digitizing Equipment

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPAD is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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TVP7002

SLES206 – MAY 2007

DESCRIPTION

TVP7002 is a complete solution for digitizing video and graphic signals in RGB or YPbPr color spaces. The device supports pixel rates up to 165 MHz. Therefore, it can be used for PC graphics digitizing up to the VESA standard of UXGA (1600 × 1200) resolution at 60-Hz screen refresh rate, and in video environments for the digitizing of digital TV formats, including HDTV up to 1080p.

The TVP7002 is powered from 3.3-V and 1.9-V supply and integrates a triple high-performance analog-to-digital (A/D) converter with clamping functions and variable gain, independently programmable for each channel. The clamp timing window is provided by an external pulse or can be generated internally. The TVP7002 includes analog slicing circuitry on the SOG inputs to support sync-on-luminance or sync-on-green extraction. In addition, TVP7002 can extract discrete HSYNC and VSYNC from composite sync using a sync slicer.

TVP7002 also contains a complete horizontal PLL block to generate a pixel clock from the HSYNC input. Pixel clock output frequencies range from 12 MHz to 165 MHz.

All programming of the part is done via an industry-standard I2C interface, which supports both reading and writing of register settings. The TVP7002 is available in a space-saving 100-pin TQFP PowerPAD package.

ORDERING INFORMATION

0 ° C to 70 ° C

100-PIN PLASTIC FLATPACK PowerPAD™

PACKAGED DEVICES

TVP7002PZP Tray

TVP7002PZPR Reel

PACKAGE OPTION

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Output

Formatter

ROUT[9:0]

GOUT[9:0]

Host

Interface

Timing Processor

and

Clock Generation

RIN_1

SCL

SDA

I2CA

GIN_1

BIN_1

Clamp

Gain and

Offset

10-bit

ADC

HSYNC_A

VSYN C_A

COAST

CLAMP

FILT1

SOGIN_1

RESETB

PWDN

BOUT[9:0]

SOGOUT

HSOUT

VSOUT

DATACLK

RIN_2

GIN_2

BIN_2

EXT_CLK

SOGIN_2

HSYNC_B

VSYN C_B

FILT2

RIN_3

GIN_3 GIN_4

SOGIN_3

BIN_3

FIDOUT

Color Space

Conversion

and

4:4:4 to 4:2:2

Conversion

Gain and

Offset

Gain and

Offset

10-bit

ADC

10-bit

ADC

FUNCTIONAL BLOCK DIAGRAM

TVP7002

SLES206 – MAY 2007

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TVP7002

100-Pin TQFP Package

(TopView)

1 00

GIN_299SOGIN_2

GIN_397SOGIN_3

GIN_495A33GND

A33VDD

A33VDD92A33GND

NSUB90PLL_AGND89PLL_F88FIL

FIL

PLL_AGND85PLL_AVDD84PLL_AVDD83PLL_AGND82HSYNC_B

HSYNC_A

EXT_CLK

VSYNC_B

VSYNC_A

COAST76CLAMP

IOVDD

IOGND

ATACLK

B_9

B_8

B_7

B_6

B_5

B_4

B_3

B_2

B_1

B_0

DVDD

GND

IOVDD

IOGND

G_9

G_8

G_7

G_6

G_5

G_4

G_3

G_2

SDA

SCL

I2CA

TMS

RESETB

PWDN

DVDD

GND

IOGND

IOVDD

R_0

R_1

R_2

R_3

R_4

IOGND

R_5

R_6

R_7

R_8

R_9

IOGND

IOVDD

G_0

G_1

SOGIN_1

GIN_1

AGND

AVDD

A DGN

AVDD

AGND

RI _N 3

RIN_2

RIN_1

A33GND

A33VDD

A33GND

BIN_3

BIN_2

BIN_1

AV DD

AGND

NSUB

FIDOUT

VSOUT

HSOUT

SOGOUT

TVP7002

SLES206 – MAY 2007

TERMINAL ASSIGNMENTS

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TVP7002

SLES206 – MAY 2007

TERMINAL FUNCTIONS

TERMINAL

NAME NO.

ANALOG VIDEO

RIN_1 11 I Analog video input for R/Pr 1 RIN_2 10 I Analog video input for R/Pr 2 RIN_3 9 I Analog video input for R/Pr 3 GIN_1 2 I Analog video input for G/Y 1 GIN_2 100 I Analog video input for G/Y 2 GIN_3 98 I Analog video input for G/Y 3 GIN_4 96 I Analog video input for G/Y 4 BIN_1 18 I Analog video input for B/Pb 1 BIN_2 17 I Analog video input for B/Pb 2 BIN_3 16 I Analog video input for B/Pb 3

CLOCK SIGNALS

DATACLK 28 O Data clock output EXT_CLK 80 I External clock input. May be used as a timing reference for the mode detection block instead of

DIGITAL VIDEO

ROUT[9:0] 55–59, 61–65 O Digital video output of R/Cr, ROUT[9] is the most-significant bit (MSB). GOUT[9:0] 43-52 O Digital video output of G/Y, GOUT[9] is the MSB. BOUT[9:0] 29-38 O Digital video output of B/Cb, BOUT[9] is the MSB.

MISCELLANEOUS SIGNALS

PWDN 70 I Power down input

RESETB 71 I Reset input, active low. Outputs are placed in a high-impedance mode during reset (see

TMS 72 I Test mode select input, active high. Used to enable scan test mode. For normal operation,

FILT1 87 O External filter connection for the horizontal PLL. A 0.1- µ F capacitor in series with a 1.5-k Ω

FILT2 88 O External filter connection for the horizontal PLL. A 4.7-nF capacitor should be connected from

PLL_F 89 I Horizontal PLL filter internal supply connection

HOST INTERFACE

I2CA 73 I I2C slave address input. Has internal pulldown resistor (see Table 7 ).

SCL 74 I I2C clock input SDA 75 I/O I2C data bus

I/O DESCRIPTION

The inputs must be AC coupled. The recommended coupling capacitor is 0.1 µ F. Unused analog inputs should be connected to ground using a 10-nF capacitor.

the internal clock reference. May also be used as the ADC sample clock instead of the H-PLL generated clock.

For 4:2:2 mode, multiplexed CbCr data is output on BOUT[9:0]. Unused outputs can be left unconnected.

0 = Normal mode 1 = Power down

Table 8 ).

connect to ground.

resistor should be connected from this pin to pin 89 (see Figure 4 ).

this pin to pin 89 (see Figure 4 ).

0 = Slave address = B8h 1 = Slave address = BAh

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TVP7002

SLES206 – MAY 2007

TERMINAL FUNCTIONS (continued)

TERMINAL

NAME NO.

POWER SUPPLIES

NSUB 21, 91 I Substrate ground. Connect to analog ground. A33VDD 13, 14, 93, 94 I Analog power. Connect to 3.3 V. A33GND 12, 15, 92, 95 I Analog 3.3-V return. Connect to ground. AGND 3, 5, 8, 20 I Analog 1.9-V return. Connect to ground. AVDD 4, 6, 7, 19 I Analog power. Connect to 1.9 V. PLL_AVDD 84, 85 I PLL analog power. Connect to 1.9 V. PLL_AGND 83, 86, 90 I PLL analog power return. Connect to ground. DGND 40, 68 I Digital return. Connect to ground. DVDD 39, 69 I Digital power. Connect to 1.9 V. IOGND 27, 42, 54, 60, I Digital power return. Connect to ground.

IOVDD 26, 41, 53, 66 I Digital power. Connect to 3.3 V or less for reduced noise.

SYNC SIGNALS

CLAMP 76 I External Clamp input. Unused inputs can be connected to ground. COAST 77 I External PLL COAST signal input. Unused inputs can be connected to ground. VSYNC_A 78 I Vertical sync input A

VSYNC_B 79 I Vertical sync input B

HSYNC_A 81 I Horizontal sync input A HSYNC_B 82 I Horizontal sync input B

SOGIN1 1 I Sync-on-green input 1 SOGIN2 99 I Sync-on-green input 2 SOGIN3 97 I Sync-on-green input 3

FIDOUT 22 O Field ID output. Using bits 2 and 3 of register 16h, this pin may also be programmed to be the

VSOUT 23 O Vertical sync output HSOUT 24 O Horizontal sync output SOGOUT 25 O Sync-on-green slicer output

I/O DESCRIPTION

Unused inputs can be connected to ground.

Unused inputs should be connected to ground using a 1-nF capacitor.

internal sync processing clock output, coast output, clamp pulse output, or data enable.

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TVP7002

SLES206 – MAY 2007

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

IOVDD to IOGND –0.5 V to 4.5 V

Supply voltage range

DVDD to DGND –0.5 V to 2.3 V PLL_AVDD to PLL_AGND and AVDD to AGND –0.5 V to 2.3 V

A33VDD to A33GND – 0.5 V to 4.5 V Digital input voltage range VIto DGND –0.5 V to 4.5 V Analog input voltage range AIto A33GND –0.2 V to 2.3 V Digital output voltage range VOto DGND –0.5 V to 4.5 V

stg

Operating free-air temperature range 0 ° C to 70 ° C Storage temperature range –65 ° C to 150 ° C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS

IOVDD Digital I/O supply voltage 3 3.3 3.6 V DVDD Digital supply voltage 1.8 1.9 2 V PLL_AVDD Analog supply voltage for horizontal PLL 1.8 1.9 2 V AVDD Analog supply voltage 1.8 1.9 2 V A33VDD Analog supply voltage 3 3.3 3.6 V V

I(P-P)

OH_DATACLK

OL_DATACLK

Analog input voltage (ac-coupling necessary) 0.5 2 V Digital input voltage high 0.7 IOVDD V Digital input voltage low 0.3 IOVDD V High-level output current 2 mA Low-level output current –2 mA DATACLK high-level output current 4 mA DATACLK low-level output current –4 mA ADC conversion rate 12 162 MHz Operating free-air temperature 0 70 ° C

(1)

MIN NOM MAX UNIT

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TVP7002

SLES206 – MAY 2007

ELECTRICAL CHARACTERISTICS

IOVDD = 3.3 V, DVDD = 1.9 V, PLL_AVDD = 1.9 V, AVDD = 1.9 V, A33VDD = 3.3 V, TA= 25 ° C

PARAMETER TEST CONDITIONS

POWER SUPPLY

A33VDD

IOVDD

AVDD

PLL_VDD

DVDD

TOT

A33VDD

IOVDD

AVDD

PLL_VDD

DVDD

TOT

DOWN

3.3-V supply current 78.75 MHz, BC = 5 67 67 mA

3.3-V supply current 78.75 MHz, BC = 5 21 56 mA

1.9-V supply current 78.75 MHz, BC = 5 206 209 mA

1.9-V supply current 78.75 MHz, BC = 5 16 16 mA

1.9-V supply current 78.75 MHz, BC = 5 30 46 mA Total power dissipation, normal mode 78.75 MHz, BC = 5 743 893 mW

3.3-V supply current 162 MHz, BC = 8 110 110 mA

3.3-V supply current 162 MHz, BC = 8 35 102 mA

1.9-V supply current 162 MHz, BC = 8 275 279 mA

1.9-V supply current 162 MHz, BC = 8 22 23 mA

1.9-V supply current 162 MHz, BC = 8 56 89 mA Total power dissipation, normal mode 162 MHz, BC = 8 1112 1403 mW Total power dissipation, power-down mode 15 15 mW

(1) BC = ADC bias control setting in I2C register, 2Ch. (2) SMPTE color bar RGB input pattern used. (3) Worst-case vertical line RGB input pattern used.

(1)

(2)

TYP

(3)

TYP

UNIT

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ELECTRICAL CHARACTERISTICS

IOVDD = 3.3 V, DVDD = 1.9 V, PLL_AVDD = 1.9 V, AVDD = 1.9 V, A33VDD = 3.3 V, TA= 0 ° C to 70 ° C (unless otherwise noted)

PARAMETER TEST CONDITIONS

ANALOG INTERFACE

Input voltage range By design 0.5 1 2 V

Input impedance, analog video inputs By design 500 k Ω

DIGITAL LOGIC INTERFACE

OH_SCLK

OL_SCLK

Input capacitance By design 10 pF Input impedance By design 500 k Ω Output voltage high IOH= 2 mA 0.8 IOVDD V Output voltage low IOL= –2 mA 0.2 IOVDD V DATACLK output voltage high IOH= 4 mA 0.8 IOVDD V DATACLK output voltage low IOH= –4 mA 0.2 IOVDD V High-level input voltage By design 0.7 IOVDD V Low-level input voltage By design 0.3 IOVDD V

ADCs

ADC full scale input range Clamp disabled 0.95 1 1.05 V ADC resolution 10-bit range 10 bits

DNL DC differential nonlinearity LSB

INL DC integral nonlinearity LSB

Missing code

SNR Signal-to-noise ratio 10 MHz, 1 V

10 bit, 110 MHz, BC = 5 –1 ± 0.5 +1 8 bit, 162 MHz, BC = 8 –1 ± 0.5 +1 10 bit, 110 MHz, BC = 5 –4 ± 1 +4 8 bit, 162 MHz, BC = 8 –4 ± 1 +4 10 bit, 110 MHz, BC = 5 none 8 bit, 162 MHz, BC = 8 none

at 110 MSPS 55 dB

P-P

Analog 3-dB bandwidth By design 350 500 MHz

HORIZONTAL PLL

Clock jitter 500 ps Phase adjustment 11.6 degree VCO frequency range By design 12 162 MHz

ANALOG ADC CHANNEL

Coarse gain full-scale control range Gain control value NG= 15 ± 6 dB Coarse offset full-scale control range Referred to 10-bit ADC output ± 124 counts Coarse offset step size Referred to 10-bit ADC output 4 counts

SYNC PROCESSING

Internal clock reference frequency By design 6.3 MHz

(1) BC = ADC bias control setting in I2C register, 2Ch.

(1)

MIN TYP MAX UNIT

TVP7002

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DATACLK

Valid Data

ROUT, GOUT,

BOUT, HSOUT

Valid Data

TVP7002

SLES206 – MAY 2007

TIMING REQUIREMENTS

PARAMETER TEST CONDITIONS

CLOCKS, VIDEO DATA, SYNC TIMING

Duty cycle DATACLK (CLK POL=0) 51 %

Duty cycle DATACLK (CLK POL=1) 44 % t1 DATACLK rise time 10% to 90% 1 ns t2 DATACLK fall time 90% to 10% 1 ns t3 Output delay time 0 2.5 ns

(1) Measured at 162 MHz with 22- Ω series termination resistor and 10-pF load. Specified by characterization only.

(1)

MIN TYP MAX UNIT

Figure 1. Clock, Video Data, and Sync Timing

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SDA

SCL

Data

Stop Start Stop

TVP7002

SLES206 – MAY 2007

TIMING REQUIREMENTS

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

I2C HOST PORT TIMING

t1 Bus free time between STOP and START Specified by design 1.3 µ s t2 Setup time for a (repeated) START condition Specified by design 0.6 µ s t3 Hold time (repeated) START condition Specified by design 0.6 µ s t4 Setup time for a STOP condition Specified by design 0.6 ns t5 Data setup time Specified by design 100 ns t6 Data hold time Specified by design 0 0.9 µ s t7 Rise time SDA and SCL signal Specified by design 250 ns t8 Fall time SDA and SCL signal Specified by design 250 ns C

I2C

Capacitive load for each bus line Specified by design 400 pF

I2C clock frequency Specified by design 400 kHz

Figure 2. I2C Host Port Timing

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TVP7002

SLES206 – MAY 2007

FUNCTIONAL DESCRIPTION

Analog Channel

The TVP7002 contains three identical analog channels that are independently programmable. Each channel consists of a clamping circuit, programmable gain control, programmable offset control, and an ADC.

Analog Input Switch Control

TVP7002 has three analog channels that accept up to ten video inputs. The user can configure the internal analog video switches via the I2C interface. The ten analog video inputs can be used for different input configurations, some of which are:

• Up to three SDTV, EDTV, or HDTV component video inputs (limited by number of SOG inputs)

• Up to two 5-wire PC graphics inputs (limited by number of HSYNC and VSYNC inputs)

The input selection is performed by the input select register at I2C subaddress 19h a 1Ah (see Input Mux Select 1 and Input Mux Select 2).

Video Formats Supported

The TVP7002 supports A/D conversion of SDTV (480i, 576i), EDTV (480p, 765p), and HDTV (720p, 1080i, 1080p) YPbPr component video inputs. The TVP7002 also supports A/D conversion and color space conversion of all standard PC graphics formats (RGB) from VGA up to UXGA.

A summary of the analog video standards supported by the TVP7002 module is show in Table 1 .

Table 1. Analog Video Standards

VIDEO FORMAT VIDEO STANDARDS

SDTV (YPbPr Component) 480i, 576i EDTV (YPbPr Component) 480p, 576p HDTV (YPbPr Component) 720p, 1080i, 1080p

PC Graphics (RGB Component) VGA to UXGA

SCART (RGB Component) 576i

Analog Input Clamping

The TVP7002 provides dc restoration for all analog video inputs including the SOG slicer inputs. The dc restoration circuit (a.k.a. clamp circuit) restores the ac-coupled video signal to a fixed dc level. One dc restoration circuit is implemented prior to each of the three ADC, and a fourth one is located prior to the SOG slicer. The dc restoration circuit can be programmed to operate as either a sync-tip clamp (a.k.a. coarse clamp) or a back-porch clamp (a.k.a. fine clamp). The sync-tip clamp always clamps the video sync-tip level near the bottom of the ADC range. The back-porch type clamp supports two clamping levels (bottom-level and mid-level) that are selectable using bits 0, 1, and 2 of register 10h. When using the fine bottom-level clamp, an optional 300-mV common-mode offset may be selected using bit 7 of register 2Ah.

In general, the analog video input being used for horizontal synchronization purposes should always use the sync-tip clamp; all other analog video inputs should use the back-porch clamp. The advantage of the back-porch clamp is that it has negligible video droop or tilt across a video line.

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TVP7002

SLES206 – MAY 2007

The selection between bottom- and mid-level clamping is performed by I2C subaddress 10h (see Sync-On-Green Threshold). The fine clamps must also be enabled via I2C register 2Ah for proper operation. The internal clamping time can be adjusted using the I2C clamp start and width registers at subaddress 05h and 06h, respectively (see Clamp Start and Clamp Width).

Table 2. Recommended Clamp Setting by Video Mode

Video Mode

YPbPr Component Coarse Fine Bottom-Level Fine Mid-Level Fine Mid-Level

PC Graphics Coarse Fine Bottom-Level Fine Bottom-Level Fine Bottom-Level

SCART-RGB Coarse Fine Bottom-Level Fine Bottom-Level Fine Bottom-Level

A single-pole low-pass filter with three selectable cutoff frequencies (0.5, 1.7, and 4.8 MHz) is implemented in the feedback loop of the sync-tip clamp circuit.

Programmable Gain Control

The TVP7002 provides a 4-bit coarse analog gain control (before A/D conversion) and an 8-bit fine digital gain control (after A/D conversion). The coarse analog gain and the fine digital gain are both independently programmable for each ADC channel.

Coarse Gain Control

The 4-bit coarse analog gain control has a 4:1 linear gain control range defined by the following equation.

Coarse Gain = 0.5 + N

0.5 ≤ Coarse_Gain ≤ 2.0 Default: N

= 7 (Coarse_Gain = 1.2)

The 4-bit coarse gain control can scale a signal with a voltage-input compliance of 0.5-Vpp to 2-Vpp to a full-scale 10-bit A/D output code range. The minimum gain corresponds to a code 0h (2-Vpp full-scale input, –6-dB gain) while the maximum gain corresponds to code Fh (0.5-Vpp full-scale, +6 dB gain). The 4-bit coarse gain control is independently controllable for each ADC channel (Red Coarse Gain, Green Coarse Gain, and Blue Coarse Gain).

SOG Input Green ADC Ch Red ADC Ch Blue ADC Ch

(Y/G) (Y/G) (Pr/R) (Pb/B)

/10, where 0 ≤ N

≤ 15

Fine Gain Control

The 8-bit fine digital gain control has a 2:1 linear gain control range defined by the following equation.

Fine Gain = 1.0 + N

/256 where 0 ≤ N

≤ 255

1.0 ≤ Fine Gain < 2.0 Default: N

= 0 (Fine Gain = 1.0)

The 8-bit fine gain control is independently controllable for each ADC channel (Red Fine Gain, Green Fine Gain, and Blue Fine Gain). For a normal PC graphics input, the fine gain is used mostly.

Programmable Offset Control

The TVP7002 provides a 6-bit coarse analog offset control (before A/D conversion) and a 10-bit fine digital offset control (after A/D conversion). The coarse analog offset and the fine digital offset are both independently programmable for each ADC channel.

Coarse Offset Control

A 6-bit code sets the coarse offset (Red Coarse Offset, Green Coarse Offset, Blue Coarse Offset) with individual adjustment per channel. The coarse offset ranges from –32 counts to +31 counts. The coarse offset registers apply before the ADC.

Fine Offset Control

A 10-bit fine offset registers (Red Fine Offset, Green Fine Offset, Blue Fine Offset) apply after the ADC. The fine offset ranges from –512 counts to +511 counts.

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COAST

HSYNC

Phase

Detector

PLL Control

Bit [5:3]

PLL Control

Bit [7:6]

Phase Select

Bit [7:3]

Charge

Pump

VCO

Phase Select

Divider

ADC

Sampling

CLK

External

Clock

PLL Divide

1:0]Bit [1

Loop Filter

N = 1 or 2

Post

Divider

÷N

Post Divider

Bit [0]

TVP7002

SLES206 – MAY 2007

Automatic Level Control (ALC)

The ALC circuit maintains the level of the signal to be set at a value which is programmed at fine offset I2C register. It consists of pixel averaging filter and feedback loop. This ALC function can be enabled or disabled by the I2C register at subaddress 26h.

The ALC circuit needs a timing pulse generated internally but the user should program the position properly. The ALC pulse must be positioning after the clamp pulse. The position of ALC pulse is controlled by ALC placement I2C register at address 31h. This is available only for internal ALC pulse timing. When using an external clamp pulse, the fine clamp and the ALC both start on the leading edge of the external clamp pulse. Therefore, it is recommended to keep the external clamp pulse as long as possible.

Analog-to-Digital Converters (ADCs)

All ADCs have a resolution of 10 bits and can operate up to 165 MSPS. All A/D channels receive an identical clock from the on-chip phase-locked loop (PLL) at a frequency between 12 MHz and 165 MHz. All ADC reference voltages are generated internally. Also the external sampling clock can be used.

Horizontal PLL

The horizontal PLL generates a high-frequency internal clock used by the ADC sampling and data clocking out to derive the pixel output frequency with programmable phase. The reference signal for this PLL is the horizontal sync signal supplied on the HSYNC input or from extracted horizontal sync of the sync slicer block for embedded sync signals. The horizontal PLL consisted of phase detector, charge pump, loop filter, voltage controlled oscillator (VCO), phase select, feedback divider, and post divider. The horizontal PLL block diagram is shown in Figure 3 .

Figure 3. Horizontal PLL Block Diagram

The COAST signal is used to allow the PLL to keep running at the same frequency, in the absence of the incoming HSYNC signal or disordered HSYNC period. This is useful during the vertical sync period, or any other time that the HSYNC is not available.

There are several PLL controls to produce the correct sampling clock. The 12-bit feedback divider register is programmable to select exact multiplication number to generate the pixel clock in the range of 12 MHz to 165 MHz. The 3-bit loop filter current control register is to control the charge pump current that drives the low-pass loop filter. The applicable current values are listed in the Table 3 .

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0.1 µF

4.7 nF

1.5 kW

TVP7002

PLL_F

FILT2

FILT1

TVP7002

SLES206 – MAY 2007

The purpose of the 2-bit VCO range control is to improve the noise performance of the TVP7002. The frequency ranges for the VCO are shown in Table 3 . The phase of the ADC sample clock generated by the horizontal PLL can be accurately controlled in 32 uniform steps over a single clock period (360/32 = 11.25 degrees phase resolution) using the phase select register located at subaddress 04h.

The horizontal PLL characteristics are determined by the loop filter design, the PLL charge pump current, and the VCO range setting. The loop filter design is shown in Figure 4 . Supported settings of VCO range and charge pump current for VESA standard display modes are listed in Table 3 .

Figure 4. Horizontal PLL Loop Filter

In addition to sourcing the ADC sample clock from the horizontal PLL, an external pixel clock can be used (from pin 80).

Table 3. Recommended VCO Range and Charge Pump Current Settings for Supporting Standard Display

Formats

STANDARD RESOLUTION RATE RATE [11:4] REG [3:0] REG REG 03h

640 × 480 59.94 31.469 25.175 800 32h 00h 20h 0 ULow (00b) 100b

VGA

SVGA 800 × 600 72.188 48.077 50 1040 41h 00h 58h 0 Low (01b) 011b

XGA

WXGA (I)

SXGA 1280 × 1024 75.025 79.976 135 1688 69h 80h E8h 0 High (11b) 101b

SXGA+ 1400 × 1050 59.978 65.317 121.75 1864 74h 80h 98h 0 Med (10b) 011b

WXGA (II)

UXGA 1600 × 1200 60 75 162 2160 87h 00h E0h 0 High (11b) 100b

640 × 480 72.809 37.861 31.5 832 34h 00h 20h 0 ULow (00b) 100b 640 × 480 75 37.5 31.5 840 34h 80h 20h 0 ULow (00b) 100b 640 × 480 85.008 43.269 36 832 34h 00h 60h 0 Low (01b) 100b 800 × 600 56.25 35.156 36 1024 40h 00h 58h 0 Low (01b) 011b 800 × 600 60.317 37.879 40 1056 42h 00h 58h 0 Low (01b) 011b

800 × 600 75 46.875 49.5 1056 42h 00h 58h 0 Low (01b) 011b 800 × 600 85.061 53.674 56.25 1048 41h 80h 58h 0 Low (01b) 011b

1024 × 768 60.004 48.363 65 1344 54h 00h 58h 0 Low (01b) 011b

1024 × 768 70.069 56.476 75 1328 53h 00h A8h 0 Med (10b) 101b 1024 × 768 75.029 60.023 78.75 1312 52h 00h A8h 0 Med (10b) 101b 1024 × 768 84.997 68.677 94.5 1376 56h 00h A0h 0 Med (10b) 100b 1280 × 768 59.995 47.396 68.25 1440 5Ah 00h 50h 0 Low (01b) 010b 1280 × 768 59.87 47.776 79.5 1664 68h 00h A0h 0 Med (10b) 100b 1280 × 768 74.893 60.289 102.25 1696 6Ah 00h A0h 0 Med (10b) 100b 1280 × 768 84.837 68.633 117.5 1712 6Bh 00h A0h 0 Med (10b) 100b

1280 × 1024 60.02 63.981 108 1688 69h 80h A0h 0 Med (10b) 100b

1280 × 1024 85.024 91.146 157.5 1728 6Ch 00h E8h 0 High (11b) 101b 1400 × 1050 59.948 64.744 101 1560 61h 80h A0h 0 Med (10b) 100b

1400 × 1050 74.867 82.278 156 1896 76h 80h E0h 0 High (11b) 100b

1440 × 900 59.901 55.469 88.75 1600 64h 00h A0h 0 Med (10b) 100b 1440 × 900 59.887 55.935 106.5 1904 77h 00h 98h 0 Med (10b) 011b 1440 × 900 74.984 70.635 136.75 1936 79h 00h E0h 0 High (11b) 100b 1440 × 900 84.842 80.43 157 1952 7Ah 00h E0h 0 High (11b) 100b

FRAME PIXEL PLLDIV PLLDIV

LINE RATE DIVIDER DIVIDER RANGE CURRENT

(Hz) (MHz) 01h [7:0] 02h [7:4]

(kHz) TOTAL REG 04h REG 03h REG 03h

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PLL OUTPUT VCO CP

PIX/LINE [0] [7:6] [5:3]

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TVP7002

SLES206 – MAY 2007

Table 3. Recommended VCO Range and Charge Pump Current Settings for Supporting Standard Display

Formats (continued)

STANDARD RESOLUTION RATE RATE [11:4] REG [3:0] REG REG 03h

720 × 480i 29.97 15.374 13.5 858 35h A0h 18h 0 ULow (00b) 011b

720 × 576i 25 15.625 13.5 864 36h 00h 18h 0 ULow (00b) 011b 720 × 480p 59.94 31.469 27 858 35h A0h 18h 0 ULow (00b) 011b 720 × 576p 50 31.25 27 864 36h 00h 18h 0 ULow (00b) 011b

Video

1280 × 720p 60 45 74.25 1650 67h 20h A0h 0 Med (10b) 100b 1280 × 720p 50 37.5 74.25 1980 7Bh C0h 98h 0 Med (10b) 011b 1920 × 1080i 60 33.75 74.25 2200 89h 80h 98h 0 Med (10b) 011b

1920 × 1080i 50 28.125 74.25 2640 A5h 00h 90h 0 Med (10b) 010b 1920 × 1080p 60 67.5 148.5 2200 89h 80h E0h 0 High (11b) 100b 1920 × 1080p 50 56.25 148.5 2640 A5h 00h D8h 0 High (11b) 011b

FRAME PIXEL PLLDIV PLLDIV

LINE RATE DIVIDER DIVIDER RANGE CURRENT

(Hz) (MHz) 01h [7:0] 02h [7:4]

(kHz) TOTAL REG 04h REG 03h REG 03h

RGB-to-YCbCr Color Space Conversion

The TVP7002 supports RGB-to-YCbCr color space conversion (CSC) with I2C programmable coefficients. The TVP7002 should default to the CSC coefficients required for HDTV component video inputs. The TVP7002 supports the ability to bypass the CSC block and defaults to the bypass mode (bit 4 of subaddress 18h).

RGB-to-YCbCr CSC coefficients for HDTV component video (see CEA-770.3-C, ITU-R BT.709) (default coefficients):

PLL OUTPUT VCO CP

PIX/LINE [0] [7:6] [5:3]

G' B' R'

Y 00000016E3 000000024F 00000006CE

Pb FFFFFFF3AB 0000001000 FFFFFFFC55

Pr FFFFFFF178 FFFFFFFE88 0000001000

RGB-to-YCbCr CSC coefficients for SDTV component video (see CEA-770.2-C, ITU-R BT.601) (informative only):

G' B' R'

Y 00000012C9 00000003A6 0000000991

Pb FFFFFFF566 0000001000 FFFFFFFA9A

Pr FFFFFFF29A FFFFFFFD66 0000001000

4:4:4 to 4:2:2 Conversion

For 4:4:4 YPbPr component video inputs, the TVP7002 can downsample the chroma samples (CbCr) from 1x to

0.5x using a 27-tap half-band filter.

NOTE:

• Selection between the 30-bit 4:4:4 output format and the 20-bit 4:2:2 output format is made using bit 1 of register 15h.

• Multiplexed CbCr data is output on BOUT [9:0] in the 20-bit 4:2:2 output format.

• 4:4:4 to 4:2:2 conversion is implemented after RGB to YCbCr color space conversion.

Sync Processing

Horizontal Sync Selection

The TVP7002 provides two HSYNC inputs and three analog SOG inputs for HDTV and PC graphics inputs. The sync input used by the horizontal PLL is automatically selected based on activity detection.

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