TEXAS INSTRUMENTS TRF1223 Technical data
查询TRF1223供应商
.ti.com
www
TRF1223
SLWS166A–APRIL2005–REVISEDJULY2005
3.3-GHzTO3.8-GHZ1-WPowerAmplifier
FEATURES
VPOS
VNEG
•1WP-1dBLinear,30-dBGainTransmitter
•OperatesOverthe3300-MHzto3800-MHz
Range
•TwoTTLControlled,1-bit,16-dBGainSteps
for32dBofTotalGainControl
•SuperiorLinearity(+45dBmIP3)Overthe
EntireFrequencyRange
VDD
RFO
Power
Supply
Power
Amp /
Attenuator
Driver
Amplifier
Pre-Amp
ACNT
P
LP
RFI
•Auto-BiasDesignWithPAEnable
•TemperatureCompensatedDirectional
CouplerDetector
•LowPowerBiasMode
DETN
DETP
•InternallyMatched50-ΩInputandOutput
AGAIN1
P
AGAIN0
P
DESCRIPTION
TheTRF1223isahighlyintegratedlineartransmitter/poweramplifier(PA)MMIC.Thechiphastwo16-dBgain
stepsthatprovideatotalof32-dBgaincontrolvia1-bitTTLcontrolsignals.ThechipalsointegratesaTTLmute
functionthatturnsofftheamplifiersforpowercriticalorTDDapplications.Atemperaturecompensateddetector
isincludedforoutputpowermonitororALCapplications.ThechiphasaP
interceptof+45dBm.
TheTRF1223isdesignedtofunctionasapartofTexasInstrumentscomplete3.5-GHzchipset.TheTRF1223is
theoutputpoweramplifieroradriveramplifierforhigherpowerapplications.Thelinearnatureofthetransmitter
makesitidealforcomplexmodulationsschemessuchashighorderQAMorOFDM.
of+30dBmandathirdorder
1dB
KEYSPECIFICATIONS
•OP
•OutputIP3=+45dBm,Typical
•Gain=30dB,Typical
•GainFlatnessoverTransmitBand±2dB
•FrequencyRange=3300MHzto3800MHz
•±0.5-dBDetectedOutputVoltagevsTemperature
=+30dBm
1dB
BLOCKDIAGRAM
Thedetailedblockdiagramandthepin-outoftheASICareshowninFigure1.
Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexas
Instrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet.
PRODUCTIONDATAinformationiscurrentasofpublicationdate.
ProductsconformtospecificationsperthetermsoftheTexas
Instrumentsstandardwarranty.Productionprocessingdoesnot
necessarilyincludetestingofallparameters.
Copyright©2005,TexasInstrumentsIncorporated
TRF1223
SLWS166A–APRIL2005–REVISEDJULY2005
www
.ti.com
VDD1
VDD2
VDD3A
VDD3B
RFO
DETN
DETP
VPOS
VNEG
Power
Attenuator
Power
Supply
Amp /
ADJ1
V
VADJ2
VADJ3
Switched
PACNT
LP
Attn
PAGAIN1
Figure1.DetailedBlockDiagramofTRF1223
Driver Amp
Switched
PAGAIN0
Attn
Pre-Amp
RFI
ELECTROSTATICDISCHARGENOTE
TheTRF1223containClass1devices.Thefollowingelectrostaticdischarge(ESD)precautionsarerecommended:
•Protectiveoutergarments
•HandlinginESDsafeguardedworkarea
•TransportinginESDshieldedcontainers
•FrequentmonitoringandtestingallESDprotectionequipment
•TreatingtheTRF1223asextremelysensitivetoESD
PINOUTTABLE
Table1.PinOutofTRF1223
PIN#PINNAMEI/OTYPEDESCRIPTION
1VDD1IPowerStage1dcdrainsupplypower.Thedccurrentthroughthispinistypically5%of
IDD.
2VADJ1IAnalogNoconnectionrequiredfornormaloperation.MaybeusedtoadjustFET1bias.
DONOTGROUNDTHISPINORCONNECTTOANYOTHERPIN.
3GND--Ground
4RFIIAnalogRFinputtopoweramplifier,dcblockedinternally
5RFIIAnalogRFinputtopoweramplifier,dcblockedinternally
6VNEGIPowerNegativepowersupply–5V.Usedtosetgatevoltage.Thisvoltagemustbe
sequencedwithVDD.See
7VPOSIPowerPositivepowersupplyforbiascircuits.Biasis+5V.Usedtosetgatebiasand
logicinputlevel.
(1)
(1)
.
(1)Propersequencing:Inordertoavoidpermanentdamagetothepoweramplifier,thesupplyvoltagesmustbesequenced.Theproper
powerupsequenceisV
2
,thenV
NEG
,andthenVDD.TheproperpowerdownsequenceisremoveVDD,thenV
POS
POS
,andthenV
.
NEG
www.ti.com
SLWS166A – APRIL 2005 – REVISED JULY 2005
Table 1. Pin Out of TRF1223 (continued)
PIN # PIN NAME I/O TYPE DESCRIPTION
8 PAGAIN0 I Digital First 16-dB attenuator gain control. Logic high is high gain and logic low is low
gain.
9 PAGAIN1 I Digital Second 16-dB gain control. Logic high is high gain and logic low is low gain.
10 VADJ2 I Analog No connection required for normal operation. May be used to adjust FET2 bias.
DO NOT GROUND THIS PIN OR CONNECT TO ANY OTHER PIN.
11-14 GND - - Ground
15 VADJ3 I Analog No connection required for normal operation. May be used to adjust FET3 bias
DO NOT GROUND THIS PIN OR CONNECT TO ANY OTHER PIN.
16 LP I Digital Low power mode: Active high. Low power mode is lower dc and P
17 PACNT I Digital Power amplifier enable, High is PA on, logic low is PA off (low current)
18 VDD3B I Power Stage 3 dc-drain supply power. This pin is internally dc connected to pin 23
(VDD3A). Bias must be provided to both pins for optimal performance. The total
dc-current through these two pins is typically 70% of IDD.
19 GND - - Ground
20 RFO O Analog RF output, internal dc block
21 RFO O Analog RF output, internal dc block
22 VDD3A - - Ground
23 DETP I Power Stage 3 dc-rain supply power. This pin is internally dc connected to pin 18
(VDD3B). Bias must be provided to both pins for optimal performance. The total
dc-current through these two pins is typically 70% of IDD.
24 DETN O Analog Detector output, positive. Voltage will be 0.5 V with/without RF output
25 GND O Analog Detector output, negative. Voltage is 0.5 V with no RF and decreases with
increasing RF output power.
26-31 GND - - Ground
32 VDD2 I Power Stage 2 dc-drain supply power. The dc current through this pin is typically 25%
of IDD.
Back - - Back of package has a metal base which must be grounded for thermal and RF
performance.
TRF1223
mode.
OUT
SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETER TEST CONDITION MIN MAX UNIT
VDD 0 8 V
VPOS DC supply voltage 0 5.5 V
VNEG -5.5 0 V
I
DD
Pin RF input power 20 dBm
T
j
Pd Power dissipation 6.5 W
Θ
jc
T
stg
T
op
(1) Thermal resistance is junction to case assuming thermal pad with 25 thermal vias under package metal base. See the recommended
layout Figure 7 and application note RA1005 for more detail.
Current consumption 1300 Ma
Junction temperature 175 °C
Digital input pins -0.3 5.5
Thermal resistance junction to 20 °C/W
(1)
case
Storage temperature -40 105 °C
Operating temperature Maximum case temperature derate for -40 85 °C
PCB thermal resistance
Lead temperature 40 sec maximum 220 °C
3
Loading...