TEXAS INSTRUMENTS TPS786xx Technical data

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1

2 3 4 5

6 GND

DCQ PACKAGE

SOT223-6

(TOP VIEW)

NR/FB

OUT

GND

IN

EN

1

KTT PACKAGE

DDPAK-5

(TOP VIEW)

2 3

4 5

EN

IN

GND

OUT

0

10

20

30

40

50

60

70

80

Frequency (Hz)

1 10k 10M1k

Ripple Rejection − (dB)

I

OUT

= 1 mA

TPS78630

RIPPLE REJECTION

vs

FREQUENCY

I

OUT

= 1.5 A

VIN = 4 V C

OUT

= 10 µF

CNR = 0.01 µF

10 100 100k 1M

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

Frequency (Hz)

100 10k 100k1k

Output Spectral Noise Density − (µV/ Hz)

I

OUT

= 1 mA

TPS78630

OUTPUT SPECTRAL NOISE DENSITY

vs

FREQUENCY

I

OUT

= 1.5 A

VIN = 5.5 V C

OUT

= 2.2 µF

CNR = 0.1 µF

NR/FB

TAB GND

查询TPS78618供应商

ULTRALOW-NOISE, HIGH-PSRR, FAST, RF, 1.5-A

LOW-DROPOUT LINEAR REGULATORS

FEATURES DESCRIPTION

• 1.5-A Low-Dropout Regulator With Enable

• Available in Fixed and Adjustable (1.2-V to

5.5-V) Output Versions

• High PSRR (49 dB at 10 kHz)

• Ultralow Noise (48 µ V

• Fast Start-Up Time (50 µs)

• Stable With a 1- µ F Ceramic Capacitor

• Excellent Load/Line Transient Response

• Very Low Dropout Voltage (390 mV at Full

Load, TPS78630)

• 6-Pin SOT223 and 5-Pin DDPAK Package

APPLICATIONS

• RF: VCOs, Receivers, ADCs

• Audio

• Bluetooth

• Cellular and Cordless Telephones

• Handheld Organizers, PDAs

®

, Wireless LAN

, TPS78630)

RMS

TPS786xx

SLVS389F – SEPTEMBER 2002 – REVISED DECEMBER 2005

The TPS786xx family of low-dropout (LDO) low-power linear voltage regulators features high power-supply rejection ratio (PSRR), ultralow noise, fast start-up, and excellent line and load transient responses in small outline, SOT223-6 and DDPAK-5 packages. Each device in the family is stable, with a small 1- µ F ceramic capacitor on the output. The family uses an advanced, proprietary BiCMOS fabrication process to yield extremely low dropout voltages (for example, 390 mV at 1.5 A). Each device achieves fast start-up times (approximately 50 µ s with a 0.001 µF bypass capacitor) while consuming very low quiescent current (265 µ A, typical). Moreover, when the device is placed in standby mode, the supply current is reduced to less than 1 µ A. The TPS78630 exhibits approximately 48 µ V voltage at 3.0 V output noise with a 0.1 µ F bypass capacitor. Applications with analog components that are noise sensitive, such as portable RF electronics, benefit from the high PSRR, low noise features, and the fast response time.

of output

RMS

Bluetooth is a registered trademark of Bluetooth SIG, Inc. All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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TPS786xx

SLVS389F – SEPTEMBER 2002 – REVISED DECEMBER 2005

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ORDERING INFORMATION

PRODUCT V

TPS786 xxyyyz XX is nominal output voltage (for example, 28 = 2.8 V, 285 = 2.85 V, 01 = Adjustable).

YYY is package designator. Z is package quantity.

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com .

(2) Output voltages from 1.3 V to 5.0 V in 100 mV increments are available; minimum order quantities may apply. Contact factory for details

and availability.

(1)

(2)

OUT

ABSOLUTE MAXIMUM RATINGS

over operating temperature (unless otherwise noted)

VINrange –0.3 V to 6 V V

range –0.3 V to VIN+ 0.3 V

EN

V

range 6 V

OUT

Peak output current Internally limited ESD rating, HBM 2 kV ESD rating, CDM 500 V Continuous total power dissipation See Dissipation Ratings table Junction temperature range, T Storage temperature range, T

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

J

stg

(1)

VALUE

–40 ° C to +150 ° C –65 ° C to +150 ° C

PACKAGE DISSIPATION RATINGS

PACKAGE BOARD R θ

DDPAK High-K

SOT223 Low-K

(1) The JEDEC high-K (2s2p) board design used to derive this data was a 3-in x 3-in (7,5-cm x 7,5-cm), multilayer board with 1 ounce

internal power and ground planes and 2 ounce copper traces on top and bottom of the board.

(2) The JEDEC low-K (1s) board design used to derive this data was a 3-in x 3-in (7,5-cm x 7,5cm), two-layered board with 2 ounce copper

traces on top of the board.

2

(1)

(2)

JC

2 ° C/W 23 ° C/W

15 ° C/W 53 ° C/W

R θ

JA

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TPS786xx

SLVS389F – SEPTEMBER 2002 – REVISED DECEMBER 2005

ELECTRICAL CHARACTERISTICS

V

+ 1 V

(1)

, I

= 1 mA,

OUT

DO

(1.02)V

OUT

IN

Over recommended operating temperature range (T C

OUT

= 10 µ F, C

= 0.01 µ F, unless otherwise noted. Typical values are at +25 ° C.

NR

= –40 ° C to +125 ° C), V

J

= VIN, V

EN

= V

IN

OUT(nom)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Input voltage, V Continuous output current I

(1)

IN

OUT

2.7 5.5 V 0 1.5 A

Output voltage range TPS78601 1.225 5.5 – V Output voltage

Accuracy

Output voltage line regulation ( ∆ V Load regulation ( ∆ V

Dropout voltage VIN= V

OUT(nom)

(3)

– 0.1 V

%/V

OUT

) 0 µ A ≤ I

%/V

OUT

TPS78601 Fixed V

IN

TPS78628 I TPS78630 I

TPS78633 I Output current limit V Ground pin current 0 µ A ≤ I Shutdown current

(4)

(2)

0 µ A ≤ I 0 µ A ≤ I

OUT

(1)

)

V

OUT

OUT OUT OUT

OUT

OUT OUT

≤ 1.5 A, V ≤ 1.5 A, V

+ 1 V ≤ VIN≤ 5.5 V

OUT

+ 1 V ≤ VIN≤ 5.5 V –2.0 +2.0 %

OUT

+ 1 V ≤ VIN≤ 5.5 V 5 12 %/V

≤ 1.5 A 7 mV

OUT

= 1.5 A 410 580 = 1.5 A 390 550 mV = 1.5 A 340 510

= 0 V 2.4 4.2 A

≤ 1.5 A 260 385 µ A

OUT

(1)

(0.98)V

OUT

VEN= 0 V, 2.7 V ≤ VIN≤ 5.5 V 0.07 1 µ A

FB pin current VFB= 1.225 V 1 µ A

f = 100 Hz, I

Power-supply ripple rejection TPS78630 dB

f = 100 Hz, I f = 10 kHz, I f = 100 kHz, I

= 10 mA 59

OUT

= 1.5 A 52

OUT

= 1.5 A 49

OUT

= 1.5 A 32

OUT

CNR= 0.001 µ F 66

Output noise voltage (TPS78630) µ V

BW = 100 Hz to 100 kHz, I

= 1.5 A

OUT

CNR= 0.0047 µ F 51 CNR= 0.01 µ F 49 CNR= 0.1 µ F 48 CNR= 0.001 µ F 50

Time, start-up (TPS78630) RL= 2 Ω , C

= 1 µ F CNR= 0.0047 µ F 75

OUT

CNR= 0.01 µ F 110 High-level enable input voltage 2.7 V ≤ VIN≤ 5.5 V 1.7 V Low-level enable input voltage 2.7 V ≤ VIN≤ 5.5 V 0 0.7 V EN pin current VEN= 0 –1 1 µ A UVLO threshold VCCrising 2.25 2.65 V UVLO hysteresis 100 mV

V V

RMS

µ s

V

(1) Minimum VIN= V (2) Tolerance of external resistors not included in this specification.

+ V

OUT

or 2.7 V, whichever is greater.

DO

(3) Dropout is not measured for TPS78618 or TPS78625 since minimum VIN= 2.7 V. (4) For adjustable version, this applies only after VINis applied; then V

transitions high to low.

EN

3

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Current

Sense

Thermal

Shutdown

UVLO

R

1

FB

R

2

External to the Device

Overshoot

Detect

250 k

Ω

Quickstart

Bandgap

Reference

1.225 V

IN

V

IN

EN

GND

OUT

300

Ω

V

REF

ILIM SHUTDOWN

Current

Sense

Thermal

Shutdown

UVLO

R

1

R

2

R2= 40 k

Ω

Overshoot

Detect

250 k

Ω

Quickstart

Bandgap

Reference

1.225 V

IN

V

IN

EN

GND

NR

OUT

300

Ω

V

REF

ILIM SHUTDOWN

TPS786xx

SLVS389F – SEPTEMBER 2002 – REVISED DECEMBER 2005

FUNCTIONAL BLOCK DIAGRAM—ADJUSTABLE VERSION

FUNCTIONAL BLOCK DIAGRAM—FIXED VERSION

TERMINAL

NAME (SOT223) (DDPAK) DESCRIPTION

DCQ KTT

NR 5 5

EN 1 1

Noise-reduction pin for fixed versions only. An external bypass capacitor, connected to this terminal, in conjunction with an internal resistor, creates a low-pass filter to further reduce regulator noise.

The EN terminal is an input that enables or shuts down the device. When EN goes to a logic high, the device will be enabled. When the device goes to a logic low, the device is in shutdown mode.

Terminal Functions

FB 5 5 Feedback input voltage for the adjustable device.

GND 3, 6 3, TAB Regulator ground

IN 2 2 Input supply

OUT 4 4 Regulator output

4

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2.95

2.96

2.97

2.98

2.99

3.00

3.01

3.02

3.03

3.04

3.05

0.0 0.3 0.6 0.9 1.2 1.5

V

OUT

(V)

I

OUT

(A)

VIN = 4 V C

OUT

= 10 µF

TJ = 25°C

0

1

2

3

4

5

−40−25−10 5 20 35 50 65 80 95 110 125

V

OUT

(V)

TJ (°C)

I

OUT

= 1 mA

2.798

2.794

2.790

2.782

2.778

I

OUT

= 1.5 A

VIN = 3.8 V C

OUT

= 10 µF

2.786

290

300

310

320

330

340

350

−40−25−10 5 20 35 50 65 80 95 110 125

I

GND

(µA)

TJ (°C)

VIN = 3.8 V C

OUT

= 10 µF

I

OUT

= 1 mA

I

OUT

= 1.5 A

0.00

0.10

0.20

0.30

0.40

0.50

0.60

0.70

0.80

Frequency (Hz)

100 10k 100k1k

Output Spectral Noise Density (µV/Hz)

I

OUT

= 1 mA

I

OUT

= 1.5 A

VIN = 5.5 V C

OUT

= 2.2 µF

CNR = 0.1 µF

0.0

0.1

0.2

0.3

0.4

0.5

0.6

Frequency (Hz)

100 10k 100k1k

Output Spectral Noise Density (µV/Hz)

I

OUT

= 1 mA

I

OUT

= 1.5 A

VIN = 5.5 V C

OUT

= 10 µF

CNR = 0.1 µF

0.0

0.5

1.0

1.5

2.0

2.5

3.0

Frequency (Hz)

100 10k 100k1k

Output Spectral Noise Density − (µV/Hz)

VIN = 5.5 V C

OUT

= 10 µF

I

OUT

= 1.5 A

CNR = 0.1 µF

CNR = 0.01 µF

CNR = 0.0047 µF

CNR = 0.001 µF

0

10

20

30

40

50

60

70

80

RMS Output Noise (µV

RMS

)

C

NR

(µF)

I

OUT

= 1.5 A

C

OUT

= 10 µF

BW = 100 Hz to 100 kHz

0.001 µF 0.01 µF 0.1 µF0.0047 µF

0

10

20

30

40

50

60

70

80

f (Hz)

1 10k 10M1k

Ripple Rejection − (dB)

I

OUT

= 1 mA

I

OUT

= 1.5 A

VIN = 4 V C

OUT

= 10 µF

CNR = 0.01 µF

10 100 100k 1M

0

100

200

300

400

500

600

−40−25−10 5 20 35 50 65 80 95 110125

V

DO

(mV)

TJ (°C)

VIN = 2.7 V C

OUT

= 10 µF

I

OUT

= 1.5 A

SLVS389F – SEPTEMBER 2002 – REVISED DECEMBER 2005

TYPICAL CHARACTERISTICS

TPS78630 TPS78628 TPS78628

OUTPUT VOLTAGE OUTPUT VOLTAGE GROUND CURRENT

vs OUTPUT CURRENT vs JUNCTION TEMPERATURE vs JUNCTION TEMPERATURE

Figure 1. Figure 2. Figure 3.

TPS786xx

TPS78630 TPS78630 TPS78630

OUTPUT SPECTRAL OUTPUT SPECTRAL OUTPUT SPECTRAL

NOISE DENSITY NOISE DENSITY NOISE DENSITY vs FREQUENCY vs FREQUENCY vs FREQUENCY

Figure 4. Figure 5. Figure 6.

TPS78630 TPS78628 TPS78630

ROOT MEAN SQUARED DROPOUT VOLTAGE RIPPLE REJECTION

OUTPUT NOISE vs JUNCTION TEMPERATURE vs FREQUENCY

vs BYPASS CAPACITANCE

Figure 7. Figure 8. Figure 9.

5

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0

10

20

30

40

50

60

70

80

f (Hz)

1 10k 10M1k

Ripple Rejection (dB)

I

OUT

= 1 mA

I

OUT

= 1.5 A

VIN = 4 V C

OUT

= 10 µF

CNR = 0.1 µF

10 100 100k 1M

0

10

20

30

40

50

60

70

80

f (Hz)

1 10k 10M1k

Ripple Rejection (dB)

I

OUT

= 1 mA

I

OUT

= 1.5 A

VIN = 4 V C

OUT

= 2.2 µF

CNR = 0.01 µF

10 100 100k 1M

0

10

20

30

40

50

60

70

80

f (Hz)

1 10k 10M1k

Ripple Rejection (dB)

I

OUT

= 1 mA

I

OUT

= 1.5 A

VIN = 4 V C

OUT

= 2.2 µF

CNR = 0.1 µF

10 100 100k 1M

5

4

2

−30

−60

3

0

30

60

V

IN

(V)

t (µs)

6040200 80 100 120 140 160 180 200

I

OUT

= 1.5 A

C

OUT

= 10 µF

CNR = 0.01 µF

dv

dt



1 V

s

∆V

OUT

(mV)

t (µs)

6

5

3

−40

−80

4

0

40

80

6040200 80 100 120 140 160 180 200

I

OUT

= 1.5 A

C

OUT

= 10 µF

CNR = 0.01 µF

dv

dt



1 V

s

V

IN

(V)

∆V

OUT

(mV)

∆V

OUT

(mV)

t (µs)

2

1

−1

−75

−150

0

75

150

I

OUT

(A)

3002001000 400 500 600 700 800 900 1000

VIN = 3.8 V C

OUT

= 10 µF

CNR = 0.01 µF

di dt



1.5 A s

Time (µs)

4.0

3.5

2.5

0.5 0

3.0

1.0

1.5

2.0

V

OUT

(V)

4000 800 1200 1600 2000

V

OUT

= 2.5 V RL = 1.6 Ω CNR = 0.01 µF

V

IN

V

OUT

0

100

200

300

400

500

600

0 200 400 600 800 1000 1200 1400

V

DO

(mV)

I

OUT

(mA)

TJ = 125°C

TJ = −40°C

TJ = 25°C

0

50

100

150

200

250

300

350

400

450

500

2.5 3.0 3.5 4.0 4.5 5.0

V

DO

(mV)

VIN (V)

TJ = 125°C

TJ = −40°C

TJ = 25°C

I

OUT

= 1.5 A C

OUT

= 10 µF

CNR = 0.01 µF

TPS786xx

SLVS389F – SEPTEMBER 2002 – REVISED DECEMBER 2005

TYPICAL CHARACTERISTICS (continued)

TPS78630 TPS78630 TPS78630

RIPPLE REJECTION RIPPLE REJECTION RIPPLE REJECTION

vs FREQUENCY vs FREQUENCY vs FREQUENCY

Figure 10. Figure 11. Figure 12.

LINE TRANSIENT RESPONSE LINE TRANSIENT RESPONSE LOAD TRANSIENT RESPONSE

TPS78618 TPS78630 TPS78628

Figure 13. Figure 14. Figure 15.

TPS78625 TPS78630 TPS78601

POWER UP/ DROPOUT VOLTAGE DROPOUT VOLTAGE

POWER DOWN vs OUTPUT CURRENT vs INPUT VOLTAGE

6

Figure 16. Figure 17. Figure 18.

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ESR − Equivalent Series Resistance (Ω

I

OUT

(mA)

Region of Instability

100

10

1

0.1

0.01

C

OUT

= 1 µF

Region of Stability

1 500 1000 150030 125

ESR − Equivalent Series Resistance (Ω)

I

OUT

(mA)

Region of Instability

100

10

1

0.1

0.01

C

OUT

= 2.2 µF

Region of Stability

1 500 1000 150030 125

2.0

2.5

3.0

3.5

4.0

4.5

5.0

1.5 2.0 2.5 3.0 3.5 4.0

Minimum V

IN

(V)

V

OUT

(V)

TJ = 125°C

TJ = −40°C

I

OUT

= 1.5 A

TJ = 25°C

0

0.25

0.50

0.75

1

1.25

1.50

1.75

2

2.25

2.50

2.75

3

0 100 200 300 400 500 600

t (µs)

VIN = 4 V, C

OUT

= 10 µF,

IIN = 1.5 A

Enable

CNR =

0.01 µF

CNR =

0.001 µF

CNR =

0.0047 µF

V

OUT

(V)

ESR − Equivalent Series Resistance (Ω)

I

OUT

(mA)

Region of Instability

100

10

1

0.1

0.01

C

OUT

= 10 µF

Region of Stability

1 500 1000 150030 125

SLVS389F – SEPTEMBER 2002 – REVISED DECEMBER 2005

TYPICAL CHARACTERISTICS (continued)

MINIMUM REQUIRED TPS78630 TPS78630

INPUT VOLTAGE TYPICAL REGIONS OF STABILITY TYPICAL REGIONS OF STABILITY

vs EQUIVALENT SERIES RESISTANCE EQUIVALENT SERIES RESISTANCE

OUTPUT VOLTAGE (ESR) (ESR)

vs OUTPUT CURRENT vs OUTPUT CURRENT

Figure 19. Figure 20. Figure 21.

TPS786xx

TYPICAL REGIONS OF STABILITY START-UP

TPS78630

EQUIVALENT SERIES RESISTANCE

(ESR)

vs OUTPUT CURRENT

Figure 22. Figure 23.

7

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TPS786xx

GNDEN NR

IN OUT

V

IN

V

OUT

0.1µF

0.01µF

2.2µF

TPS786xx

SLVS389F – SEPTEMBER 2002 – REVISED DECEMBER 2005

APPLICATION INFORMATION

The TPS786xx family of low-dropout (LDO) regulators has been optimized for use in noise-sensitive equipment. The device features extremely low dropout voltages, high PSRR, ultralow output noise, low quiescent current (265 µ A, typically), and enable input to reduce supply currents to less than 1 µ A when the regulator is turned off.

A typical application circuit is shown in Figure 24 .

Figure 24. Typical Application Circuit

EXTERNAL CAPACITOR REQUIREMENTS

A 2.2- µ F or larger ceramic input bypass capacitor, connected between IN and GND and located close to the TPS786xx, is required for stability and improves transient response, noise rejection, and ripple rejection. A higher-value input capacitor may be necessary if large, fast-rise-time load transients are anticipated and the device is located several inches from the power source.

Like most low-dropout regulators, the TPS786xx requires an output capacitor connected between OUT and GND to stabilize the internal control loop. The minimum recommended capacitance is 1 µ F. Any 1 µ F or larger ceramic capacitor is suitable.

The internal voltage reference is a key source of noise in an LDO regulator. The TPS786xx has an NR pin which is connected to the voltage reference through a 250-k Ω internal resistor. The 250-k Ω internal resistor, in conjunction with an external bypass capacitor connected to the NR pin, creates a low pass filter to reduce the voltage reference noise

and, therefore, the noise at the regulator output. In order for the regulator to operate properly, the current flow out of the NR pin must be at a minimum, because any leakage current creates an IR drop across the internal resistor, thus creating an output error. Therefore, the bypass capacitor must have minimal leakage current. The bypass capacitor should be no more than 0.1- µ F to ensure that it is fully charged during the quickstart time provided by the internal switch shown in the functional block diagram.

For example, the TPS78630 exhibits only 48 µ V

RMS

of output voltage noise using a 0.1- µ F ceramic bypass capacitor and a 10- µ F ceramic output capacitor. Note that the output starts up slower as the bypass capacitance increases due to the RC time constant at the bypass pin that is created by the internal 250-k Ω resistor and external capacitor.

BOARD LAYOUT RECOMMENDATIONS TO IMPROVE PSRR AND NOISE PERFORMANCE

To improve ac measurements like PSRR, output noise, and transient response, it is recommended that the board be designed with separate ground planes for V

and V

IN

, with each ground plane connected

OUT

only at the ground pin of the device. In addition, the ground connection for the bypass capacitor should connect directly to the ground pin of the device.

REGULATOR MOUNTING

The tab of the SOT223-6 package is electrically connected to ground. For best thermal performance, the tab of the surface-mount version should be soldered directly to a circuit-board copper area. Increasing the copper area improves heat dissipation.

Solder pad footprint recommendations for the devices are presented in Application Report SBFA015 , Solder Pad Recommendations for Surface-Mount Devices, available from the TI web site at www.ti.com .

8

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C

1



(3 x 10−7) x (R1 R2)

(R1x R2)

V

OUT

 V

REF





1 

R

1

R

2



R

1





V

OUT

V

REF

 1 R

2

TPS78601

GND

FB

IN OUT EN

V

IN

V

OUT

R

1

C

1

R

2

1µF

2.2µF

OUTPUT VOLTAGE

PROGRAMMING GUIDE

OUTPUT

VOLTAGE

R

1

R

2

C

1

1.8 V

3.6 V

14.0 kΩ

57.9 kΩ

30.1 kΩ

33 pF 15 pF

TPS786xx

SLVS389F – SEPTEMBER 2002 – REVISED DECEMBER 2005

PROGRAMMING THE TPS78601

The approximate value of this capacitor can be

ADJUSTABLE LDO REGULATOR calculated using Equation 3 :

The output voltage of the TPS78601 adjustable regulator is programmed using an external resistor divider as shown in Figure 25 . The output voltage is calculated using Equation 1 :

where:

• V

= 1.2246 V typ (the internal reference

REF

voltage)

Resistors R

and R

1

should be chosen for

2

approximately 40- µ A divider current. Lower value resistors can be used for improved noise performance, but the device wastes more power. Higher values should be avoided, as leakage current at FB increases the output voltage error.

The recommended design procedure is to choose R

= 30.1 k Ω to set the divider current at 40 µ A,

2

C

= 15 pF for stability, and then calculate R

1

using

1

Equation 2 :

In order to improve the stability of the adjustable version, it is suggested that a small compensation capacitor be placed between OUT and FB.

(1)

(2)

The suggested value of this capacitor for several resistor ratios is shown in the table below. If this capacitor is not used (such as in a unity-gain configuration), then the minimum recommended output capacitor is 2.2 µ F instead of 1 µ F.

REGULATOR PROTECTION

The TPS786xx PMOS-pass transistor has a built-in back diode that conducts reverse current when the input voltage drops below the output voltage (for example, during power down). Current is conducted from the output to the input and is not internally limited. If extended reverse voltage operation is anticipated, external limiting might be appropriate.

The TPS786xx features internal current limiting and thermal protection. During normal operation, the TPS786xx limits output current to approximately

2.8 A. When current limiting engages, the output voltage scales back linearly until the overcurrent condition ends. While current limiting is designed to prevent gross device failure, care should be taken not to exceed the power dissipation ratings of the package. If the temperature of the device exceeds approximately 165 ° C, thermal-protection circuitry shuts it down. Once the device has cooled down to below approximately 140 ° C, regulator operation resumes.

(3)

Figure 25. TPS78601 Adjustable LDO Regulator Programming

9

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TJ TA PDmax R

JC

 R

CS

 R

SA



PDmax V

IN(avg)

 V

OUT(avg)



 I

OUT(avg)

 V

IN(avg)

 I

Q

A

B

C

T

J

A

R

θ

JC

T

C

B

R

θ

CS

T

A

C

R

θ

SA

(a)

(b)

DDPAK Package

SOT223 Package

CIRCUIT BOARD COPPER AREA

B

A

C

TPS786xx

SLVS389F – SEPTEMBER 2002 – REVISED DECEMBER 2005

THERMAL INFORMATION

The amount of heat that an LDO linear regulator generates is directly proportional to the amount of power it dissipates during operation. All integrated circuits have a maximum allowable junction temperature (T

max) above which normal operation is

J

not assured. A system designer must design the operating environment so that the operating junction temperature (T junction temperature (T

) does not exceed the maximum

J

max). The two main

J

environmental variables that a designer can use to improve thermal performance are air flow and

the ambient temperature (T temperature due to the regulator power dissipation. The temperature rise is computed by multiplying the maximum expected power dissipation by the sum of the thermal resistances between the junction and the case (R heatsink to ambient (R

), the case to heatsink (R

θJC

θSA

measures of how effectively an object dissipates heat. Typically, the larger the device, the more surface area available for power dissipation and the lower the object's thermal resistance.

external heatsinks. The purpose of this information is Figure 26 illustrates these thermal resistances for (a) to aid the designer in determining the proper a SOT223 package mounted in a JEDEC low-K operating environment for a linear regulator that is board, and (b) a DDPAK package mounted on a operating at a specific power level. JEDEC high-K board.

In general, the maximum expected power (P

max) Equation 5 summarizes the computation:

D

consumed by a linear regulator is computed as shown in Equation 4 :

where:

• V

• I

IN(avg) OUT(avg)

OUT(avg)

is the average input voltage.

is the average output voltage.

is the average output current.

• IQis the quiescent current. For most TI LDO regulators, the quiescent current is

The R

(4)

by its package, lead frame, and die size provided in the regulator data sheet. The R type and size of heatsink. For example, black body radiator type heatsinks can have R from 5 ° C/W for very large heatsinks to 50 ° C/W for very small heatsinks. The R the package is attached to the heatsink. For example, if a thermal compound is used to attach a heatsink to a SOT223 package, R

is specific to each regulator as determined

θJC

θCS

insignificant compared to the average output current; therefore, the term V

× IQcan be neglected. The

IN(avg)

operating junction temperature is computed by adding

) and the increase in

A

), and the

θ CS

). Thermal resistances are

is a function of the

θ SA

values ranging

θCS

is a function of how

θCS

of 1 ° C/W is reasonable.

(5)

10

Figure 26. Thermal Resistances

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R

JA

max  (125  55)°C2.5 W  28°CW

TJ TA PDmax  R

JA

R

JA



TJ T

A

PDmax

15

20

25

30

35

40

0.1 1 10 100

PCB Copper Area (cm2)

No Air Flow

150 LFM

250 LFM

R

θ

JA

− Thermal Resistance (°C/W)

1 oz. Copper Power Plane

1 oz. Copper

Ground Plane

2 oz. Copper Solder Pad

with 25 Thermal Vias

Thermal Vias,

0.3 mm Diameter,

1.5 mm Pitch

PDmax (5  2.5)V  1 A  2.5 W

TPS786xx

SLVS389F – SEPTEMBER 2002 – REVISED DECEMBER 2005

Even if no external black body radiator type heatsink is attached to the package, the board on which the regulator is mounted provides some heatsinking through the pin solder connections. Some packages, like the DDPAK and SOT223 packages, use a copper plane underneath the package or the circuit board ground plane for additional heatsinking to improve their thermal performance. Computer-aided thermal modeling can be used to compute very accurate approximations of an integrated circuit's thermal performance in different operating environments (for example, different types of circuit boards, different types and sizes of heatsinks, different air flows, etc.). Using these models, the three thermal resistances can be combined into one thermal resistance between junction and ambient (R

θJA

). This R

θJA

valid only for the specific operating environment used in the computer model.

Equation 5 simplifies into Equation 6 :

Rearranging Equation 6 gives Equation 7 :

Using Equation 6 and the computer model generated curves shown in Figure 27 and Figure 30 , a designer can quickly compute the required heatsink thermal resistance/board area for a given ambient temperature, power dissipation, and operating environment.

DDPAK POWER DISSIPATION

The DDPAK package provides an effective means of managing power dissipation in surface mount applications. The DDPAK package dimensions are provided in the mechanical drawing section at the end of the data sheet. The addition of a copper plane directly underneath the DDPAK package enhances the thermal performance of the package.

To illustrate, the TPS78625 in a DDPAK package was chosen. For this example, the average input voltage is 5 V, the output voltage is 2.5 V, the average output current is 1 A, the ambient temperature 55 ° C, the air flow is 150 LFM, and the operating environment is the same as documented below. Neglecting the quiescent current, the maximum average power is shown in Equation 8 :

Substituting TJmax for T

Equation 9 :

into Equation 6 gives

J

(9)

From Figure 27 , DDPAK Thermal Resistance vs Copper Heatsink Area, the ground plane needs to be

2

1 cm

for the part to dissipate 2.5 W. The operating environment used in the computer model to construct

Figure 27 consisted of a standard JEDEC High-K

board (2S2P) with a 1 oz. internal copper plane and ground plane. The package is soldered to a 2 oz. copper pad. The pad is tied through thermal vias to the 1 oz. ground plane. Figure 28 shows the side view of the operating environment used in the computer model.

is

(6)

(7)

Figure 27. DDPAK Thermal Resistance

vs PCB Copper Area

(8)

Figure 28. DDPAK Thermal Resistance

Computer Model

11

www.ti.com

1

2

3

4

5

0.1 1 10 100 PCB Copper Area (cm2)

TA = 55°C

No Air Flow

150 LFM

250 LFM

P

D

− Maximum Power Dissipation (W)

0

100

120

140

160

180

PCB Copper Area (in2)

No Air Flow

80 60 40 20

0.1 1 10

R

θ

JA

− Thermal Resistance (°C/W)

PDmax (3.3  2.5)V  1 A  800 mW

R

JA

max  (125  55)°C800 mW  87.5°CW

0

1

2

3

6

0 25 50 75 100 150125

TA = 25°C

TA − Ambient Temperature (°C)

4

5

4 in2 PCB Area

0.5 in2 PCB Area

P

D

− Maximum Power Dissipation (W)

TPS786xx

SLVS389F – SEPTEMBER 2002 – REVISED DECEMBER 2005

From the data in Figure 29 and rearranging dissipate 800 mW. The operating environment used

Equation 6 , the maximum power dissipation for a to construct Figure 30 consisted of a board with 1 oz.

different ground plane area and a specific ambient copper planes. The package is soldered to a 1 oz. temperature can be computed. copper pad on the top of the board. The pad is tied

through thermal vias to the 1 oz. ground plane.

Figure 29. DDPAK Maximum Power Dissipation

vs PCB Copper Area Figure 30. SOT223 Thermal Resistance

SOT223 POWER DISSIPATION

The SOT223 package provides an effective means of managing power dissipation in surface-mount applications. The SOT223 package dimensions are provided in the mechanical drawing section at the end of the data sheet. The addition of a copper plane directly underneath the SOT223 package enhances the thermal performance of the package.

To illustrate, the TPS78625 in a SOT223 package was chosen. For this example, the average input voltage is 3.3 V, the output voltage is 2.5 V, the average output current is 1 A, the ambient temperature 55 ° C, no air flow is present, and the operating environment is the same as documented below. Neglecting the quiescent current, the maximum average power is calculated as shown in

Equation 10 :

Substituting TJmax for T

Equation 11 :

From Figure 30 , R ground plane needs to be 0.55 in

12

θ JA

into Equation 6 gives

J

vs PCB Copper Area, the

2

for the part to

vs PCB Copper Area

From the data in Figure 30 and rearranging

Equation 6 , the maximum power dissipation for a

different ground plane area and a specific ambient temperature can be computed, as shown in

Figure 31 .

(10)

(11)

Figure 31. SOT223 Maximum Power Dissipation

vs Ambient Temperature

PACKAGE OPTION ADDENDUM

www.ti.com

PACKAGING INFORMATION

Orderable Device Status

TPS78601DCQ ACTIVE SOT-223 DCQ 6 78 Green (RoHS &

TPS78601DCQG4 ACTIVE SOT-223 DCQ 6 78 Green (RoHS &

TPS78601DCQR ACTIVE SOT-223 DCQ 6 2500 Green (RoHS &

TPS78601DCQRG4 ACTIVE SOT-223 DCQ 6 2500 Green (RoHS &

TPS78601KTT OBSOLETE DDPAK/

TPS78601KTTR ACTIVE DDPAK/

TPS78601KTTRG3 ACTIVE DDPAK/

TPS78601KTTT ACTIVE DDPAK/

TPS78601KTTTG3 ACTIVE DDPAK/

TPS78618DCQ ACTIVE SOT-223 DCQ 6 78 Green (RoHS &

TPS78618DCQG4 ACTIVE SOT-223 DCQ 6 78 Green (RoHS &

TPS78618DCQR ACTIVE SOT-223 DCQ 6 2500 Green (RoHS &

TPS78618DCQRG4 ACTIVE SOT-223 DCQ 6 2500 Green (RoHS &

TPS78618KTT OBSOLETE DDPAK/

TPS78618KTTR ACTIVE DDPAK/

TPS78618KTTRE3 ACTIVE DDPAK/

TPS78618KTTRG3 ACTIVE DDPAK/

TPS78618KTTT ACTIVE DDPAK/

TPS78625DCQ ACTIVE SOT-223 DCQ 6 78 Green (RoHS &

TPS78625DCQR ACTIVE SOT-223 DCQ 6 2500 Green (RoHS &

TPS78625DCQRG4 ACTIVE SOT-223 DCQ 6 2500 Green (RoHS &

TPS78625KTT OBSOLETE DDPAK/

TPS78625KTTR ACTIVE DDPAK/

TPS78625KTTRG3 ACTIVE DDPAK/

TPS78625KTTT ACTIVE DDPAK/

(1)

Package

Type

TO-263

Package

Drawing

KTT 5 TBD Call TI Call TI

KTT 5 500 Green (RoHS &

KTT 5 50 Green (RoHS &

KTT 5 TBD Call TI Call TI

KTT 5 500 Green (RoHS &

KTT 5 50 Green (RoHS &

KTT 5 TBD Call TI Call TI

KTT 5 500 Green (RoHS &

KTT 5 50 Green (RoHS &

Pins Package

Qty

Eco Plan

no Sb/Br)

(2)

Lead/Ball Finish MSL Peak Temp

Call TI Level-2-260C-1 YEAR

CU NIPDAU Level-2-260C-1 YEAR

CU SN Level-2-260C-1 YEAR

CU NIPDAU Level-2-260C-1 YEAR

CU SN Level-2-260C-1 YEAR

CU NIPDAU Level-2-260C-1 YEAR

CU SN Level-2-260C-1 YEAR

27-Feb-2006

(3)

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

Orderable Device Status

(1)

Package

Type

TPS78625KTTTG3 ACTIVE DDPAK/

TO-263

Package

Drawing

Pins Package

Qty

Eco Plan

KTT 5 50 Green (RoHS &

no Sb/Br)

(2)

TPS78628DCQ ACTIVE SOT-223 DCQ 6 78 Green (RoHS &

no Sb/Br)

TPS78628DCQG4 ACTIVE SOT-223 DCQ 6 78 Green (RoHS &

no Sb/Br)

TPS78628DCQR ACTIVE SOT-223 DCQ 6 2500 Green (RoHS &

no Sb/Br)

TPS78628DCQRG4 ACTIVE SOT-223 DCQ 6 2500 Green (RoHS &

no Sb/Br)

TPS78628KTT OBSOLETE DDPAK/

KTT 5 TBD Call TI Call TI

TO-263

TPS78628KTTR ACTIVE DDPAK/

TO-263

TPS78628KTTRG3 ACTIVE DDPAK/

TO-263

TPS78628KTTT ACTIVE DDPAK/

TO-263

KTT 5 500 Green (RoHS &

no Sb/Br)

KTT 5 500 Green (RoHS &

no Sb/Br)

KTT 5 50 Green (RoHS &

no Sb/Br)

TPS78630DCQ ACTIVE SOT-223 DCQ 6 78 Green (RoHS &

no Sb/Br)

TPS78630DCQG4 ACTIVE SOT-223 DCQ 6 78 Green (RoHS &

no Sb/Br)

TPS78630DCQR ACTIVE SOT-223 DCQ 6 2500 Green (RoHS &

no Sb/Br)

TPS78630DCQRG4 ACTIVE SOT-223 DCQ 6 2500 Green (RoHS &

no Sb/Br)

TPS78630KTT OBSOLETE DDPAK/

KTT 5 TBD Call TI Call TI

TO-263

TPS78630KTTR ACTIVE DDPAK/

TO-263

TPS78630KTTRG3 ACTIVE DDPAK/

TO-263

TPS78630KTTT ACTIVE DDPAK/

TO-263

TPS78630KTTTG3 ACTIVE DDPAK/

TO-263

KTT 5 500 Green (RoHS &

no Sb/Br)

KTT 5 500 Green (RoHS &

no Sb/Br)

KTT 5 50 Green (RoHS &

no Sb/Br)

KTT 5 50 Green (RoHS &

no Sb/Br)

TPS78633DCQ ACTIVE SOT-223 DCQ 6 78 Green (RoHS &

no Sb/Br)

TPS78633DCQG4 ACTIVE SOT-223 DCQ 6 78 Green (RoHS &

no Sb/Br)

TPS78633DCQR ACTIVE SOT-223 DCQ 6 2500 Green (RoHS &

no Sb/Br)

TPS78633DCQRG4 ACTIVE SOT-223 DCQ 6 2500 Green (RoHS &

no Sb/Br)

TPS78633KTT OBSOLETE DDPAK/

KTT 5 TBD Call TI Call TI

TO-263

TPS78633KTTR ACTIVE DDPAK/

TO-263

TPS78633KTTRE3 ACTIVE DDPAK/

TO-263

TPS78633KTTRG3 ACTIVE DDPAK/

TO-263

KTT 5 500 Green (RoHS &

no Sb/Br)

KTT 5 500 Green (RoHS &

no Sb/Br)

KTT 5 500 Green (RoHS &

no Sb/Br)

27-Feb-2006

Lead/Ball Finish MSL Peak Temp

CU SN Level-2-260C-1 YEAR

CU NIPDAU Level-2-260C-1 YEAR

CU SN Level-2-260C-1 YEAR

CU NIPDAU Level-2-260C-1 YEAR

CU SN Level-2-260C-1 YEAR

CU NIPDAU Level-2-260C-1 YEAR

CU SN Level-2-260C-1 YEAR

(3)

Addendum-Page 2

PACKAGE OPTION ADDENDUM

www.ti.com

Orderable Device Status

(1)

Package

TPS78633KTTT ACTIVE DDPAK/

TO-263

TPS78633KTTTG3 ACTIVE DDPAK/

TO-263

(1)

The marketing status values are defined as follows:

Type

Package

Drawing

Pins Package

Qty

Eco Plan

KTT 5 50 Green (RoHS &

no Sb/Br)

KTT 5 50 Green (RoHS &

no Sb/Br)

(2)

Lead/Ball Finish MSL Peak Temp

CU SN Level-2-260C-1 YEAR

27-Feb-2006

(3)

ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 3

IMPORTANT NOTICE

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TEXAS INSTRUMENTS TPS786xx Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual