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TPS 74301
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Texas Instruments TPS 74301 INSTALLATION INSTRUCTIONS

TPS74301
TPS74301
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500mV/div
Time(20ms/div)
V
PG
V
TRACK
I =500mA
OUT
V
OUT
1.5A Ultra-LDO with Programmable Sequencing
TPS74301
SBVS065E – DECEMBER 2005 – REVISED MAY 2007

FEATURES

• Track Pin Allows for Flexible Power-Up
Sequencing
• 1% Accuracy Over Line, Load, and
Temperature
• Supports Input Voltages as Low as 0.9V with
External Bias Supply
• Adjustable Output (0.8V to 3.6V)
• Ultra-Low Dropout: 55mV at 1.5A (typ)
• Stable with Any or No Output Capacitor
• Excellent Transient Response
• Available in 5mm × 5mm × 1mm QFN and
DDPAK-7 Packages
• Open-Drain Power-Good (5 × 5 QFN)
• Active High Enable

APPLICATIONS

• FPGA Applications
• DSP Core and I/O Voltages
• Post-Regulation Applications
• Applications with Special Start-Up Time or
Sequencing Requirements

DESCRIPTION

The TPS74301 low-dropout (LDO) linear regulator provides an easy-to-use robust power management solution for a wide variety of applications. The TRACK pin allows the output to track an external supply. This feature is useful in minimizing the stress on ESD structures that are present between the CORE and I/O power pins of many processors. The enable input and power-good output allow easy sequencing with external regulators. This complete flexibility allows the user to configure a solution that meets the sequencing requirements of FPGAs, DSPs, and other applications with special start-up requirements.
A precision reference and error amplifier deliver 1% accuracy over load, line, temperature, and process. Each LDO is stable with low-cost ceramic output capacitors and the device is fully specified from –40 ° C to +125 ° C. The TPS74301 is offered in a small (5mm × 5mm) QFN package, yielding a highly compact total solution size. For applications that require additional power dissipation, the DDPAK (KTW) package is also available.
Figure 1. Typical Application Circuit
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Figure 2. Tracking Response
Copyright © 2005–2007, Texas Instruments Incorporated
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TPS74301
SBVS065E – DECEMBER 2005 – REVISED MAY 2007
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
PRODUCT V
TPS743 xxyyyz XX is nominal output voltage (for example, 12 = 1.2V, 15 = 1.5V, 01 = Adjustable).
(1)
(2)
OUT
(3)
YYY is package designator. Z is package quantity.
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com .
(2) Output voltages from 0.9V to 1.5V in 50mV increments and 1.5V to 3.3V in 100mV increments are available through the use of
innovative factory EEPROM programming; minimum order quantities may apply. Contact factory for details and availability.
(3) For fixed 0.8V operation, tie FB to OUT.

ABSOLUTE MAXIMUM RATINGS

(1)
At TJ= –40 ° C to +125 ° C, unless otherwise noted. All voltages are with respect to GND.
TPS74301 UNIT
VIN, V
V
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Input voltage range –0.3 to +6 V
BIAS
V
Enable voltage range –0.3 to +6 V
EN
V
Power-good voltage range –0.3 to +6 V
PG
IPGPG sink current 0 to +1.5 mA
Track pin voltage range –0.3 to +6 V
TRACK
V
Feedback pin voltage range –0.3 to +6 V
FB
V
Output voltage range –0.3 to VIN+ 0.3 V
OUT
I
Maximum output current Internally limited
OUT
Output short circuit duration Indefinite
P
Continuous total power dissipation See Dissipation Ratings Table
DISS
TJOperating junction temperature range –40 to +125 ° C
T
Storage junction temperature range –55 to +150 ° C
STG

DISSIPATION RATINGS

PACKAGE θ
RGW (QFN)
KTW (DDPAK)
(1) See Figure 31 for PCB layout description. (2) See Figure 34 for PCB layout description.
2
(1)
(2)
JA
36.5 ° C/W 4.05 ° C/W 2.74W 27.4mW/ ° C
18.8 ° C/W 2.32 ° C/W 5.32W 53.2mW/ ° C
θ
JC
POWER RATING ABOVE TA= +25 ° C
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TA< +25 ° C DERATING FACTOR
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ELECTRICAL CHARACTERISTICS

At V
= 1.1V, V
EN
unless otherwise noted. Typical values are at TJ= +25 ° C.
V
IN
V
BIAS
V
REF
V
OUT
V
/V
OUT
IN
V
/I
OUT
OUT
V
DO
ICLCurrent limit V
I
BIAS
I
SHDN
IFBFeedback pin current
PSRR
Noise Output noise voltage 100Hz to 100kHz, I
V
TRAN
t
STR
T
ACC
ITRTrack pin current V
V
EN, HI
V
EN, LO
V
EN, HYS
V
EN, DG
IENEnable pin current V V
IT
V
HYS
V
PG, LO
I
PG, LKG
T
J
T
SD
= V
OUT
+ 0.3V, C
IN
= C
IN
BIAS
= 0.1 µ F, C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Input voltage range V Bias pin voltage range 2.375 5.25 V Internal reference (Adj.) TJ= +25 ° C 0.796 0.8 0.804 V Output voltage range VIN= 5V, I
BIAS
IN
IN
BIAS
dropout voltage
)
to V
OUT
(1)
)
OUT
to V
OUT
droop during load
2.375V ≤ V V
OUT (NOM)
V
OUT (NOM)
0mA ≤ I 50mA ≤ I I
= 1.5A, V
(2)
OUT
I
= 1.5A, V
OUT
(2)
I
= 1.5A, VIN= V
OUT
= 80% × V
OUT
= 0mA to 1.5A 2 4 mA
OUT
V
≤ 0.4V 1 100 µ A
EN
(3)
I
= 50mA to 1.5A –250 68 250 nA
OUT
1kHz, I 800kHz, I 1kHz, I
)
800kHz, I
I
= 50mA to 1.5A at 1A/ µ s, C
OUT
TRACK
Accuracy
Line regulation %/V
Load regulation
VINdropout voltage
V
Bias pin current I Shutdown supply current
(V
Power-supply rejection (V
Power-supply rejection (V
%V transient
Minimum startup time V Track pin accuracy 0.2V ≤ V
TRACK
= 1.5A, V
OUT
≤ 5.25V, 50mA ≤ I
BIAS
+ 0.3 ≤ VIN≤ 5.5V, QFN 0.0005 0.05 + 0.3 ≤ VIN≤ 5.5V, DDPAK 0.0005 0.06
≤ 50mA 0.013 %/mA
OUT
≤ 1.5A 0.04 %/A
OUT
BIAS BIAS
OUT (NOM)
= 1.5A, VIN= 1.8V, V
OUT
= 1.5A, VIN= 1.8V, V
OUT
= 1.5A, VIN= 1.8V, V
OUT
= 1.5A, VIN= 1.8V, V
OUT
> 0.8V 40 µ s
≤ 0.7V, V
TRACK
= 0.4V 0.1 1 µ A Enable input high level 1.1 5.5 V Enable input low level 0 0.4 V Enable pin hysteresis 50 mV Enable pin deglitch time 20 µ s
= 5V 0.1 1 µ A
EN
PG trip threshold V
decreasing 86.5 90 93.5 %V
OUT
PG trip hysteresis 3 %V PG output low voltage IPG= 1mA (sinking), V PG leakage current V
PG
= 5.25V, V
OUT
Operating junction temperature
Thermal shutdown temperature
Shutdown, temperature increasing +155 Reset, temperature decreasing +140
SBVS065E – DECEMBER 2005 – REVISED MAY 2007
= 10 µ F, I
OUT
= 5V V
BIAS
– V
OUT (NOM)
– V
OUT (NOM)
BIAS
≥ 1.62V, QFN 55 100 ≥ 1.62V, DDPAK 60 120
= 50mA, V
OUT
≤ 1.5A –1 ± 0.2 1 %
OUT
= 5.0V, and TJ= –40 ° C to +125 ° C,
BIAS
+ V
OUT
REF
1.8 4 A
= 1.5V 73
OUT
= 1.5V 42
OUT
= 1.5V 67
OUT
= 1.5V 50
OUT
= 1.5A 25 × V
OUT
= none 3.5 %V
OUT
= 0.8V –60 60 mV
OUT
< V
OUT
IT
> V
IT
–40 +125 ° C
TPS74301
TPS74301
DO
OUT
0.3 1 µ A
5.5 V
3.6 V
1.4 V
0.3 V
mV
dB
dB
µ V
RMS
OUT
OUT OUT
° C
(1) Adjustable devices tested at 0.8V; external resistor tolerance is not taken into account. (2) Dropout is defined as the voltage from the input to V (3) IFBcurrent flow is out of the device.
when V
OUT
OUT
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is 2% below nominal.
3
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Thermal
Limit
FB
PG
IN
BIAS
TRACK
EN
Hysteresis
andDe-Glitch
Current
Limit
UVLO
0.8V Reference
0.9 V´
REF
GND
V <V =1,V >V =0
TRACK REF TRACK REF
V
OUT
R
1
R
2
V =0.8x( )
OUT
1+
R
1
R
2
1
0
TPS74301
SBVS065E – DECEMBER 2005 – REVISED MAY 2007

BLOCK DIAGRAM

(1) V
OUT
= 0.8 × (1 + R1/R2)
Table 1. Standard 1% Resistor Values for Programming the Output Voltage
R1(k Ω ) R2(k Ω ) V
Short Open 0.8
0.619 4.99 0.9
1.13 4.53 1.0
1.37 4.42 1.05
1.87 4.99 1.1
2.49 4.99 1.2
4.12 4.75 1.5
3.57 2.87 1.8
3.57 1.69 2.5
3.57 1.15 3.3
(1)
(V)
OUT
4
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IN
IN
IN
PG
BIAS
OUT
OUT
OUT
NC
FB
TPS74301
IN
EN
11
GND
12
NC
13
NC
14
TRACK
15
6
7
8
9
10
20
19
18
17
16
5
NC4
NC3
NC2
OUT1
5 5QFN(RGW)´
Package TopView¾
7-Lead
DDPAK(KTW)
Surface-Mount
OUT
GND
BIAS
IN
FB
TRACK
1 2 3 4
5
6
EN
7
TPS74301
SBVS065E – DECEMBER 2005 – REVISED MAY 2007

PIN DESCRIPTIONS

NAME KTW (DDPAK) RGW (QFN) DESCRIPTION
IN 5 5–8 Unregulated input to the device.
EN 7 11
TRACK 1 15
Enable pin. Driving this pin high enables the regulator. Driving this pin low puts the regulator into shutdown mode. This pin must not be left floating.
Tracking pin. Connect this pin to the center tap of a resistor divider off of an external supply to program the device to track an external supply.
BIAS 6 10 Bias input voltage for error amplifier, reference, and internal control circuits.
Power-Good (PG) is an open-drain, active-high output that indicates the status of V
. When V
OUT
high-impedance state. When V
PG N/A 9 low-impedance state. A pull-up resistor from 10k Ω to 1M Ω should be
exceeds the PG trip threshold, the PG pin goes into a
OUT
OUT
connected from this pin to a supply up to 5.5V. The supply can be higher than the input voltage. Alternatively, the PG pin can be left floating if output monitoring is not necessary.
FB 2 16
This pin is the feedback connection to the center tap of an external resistor divider network that sets the output voltage. This pin must not be left floating.
OUT 3 1, 18–20 Regulated output voltage. No capacitor is required on this pin for stability.
NC N/A 2–4, 13, 14, 17
No connection. This pin can be left floating or connected to GND to allow better thermal contact to the top-side plane.
GND 4 12 Ground
PAD/TAB Should be soldered to the ground plane for increased thermal performance.
is below this threshold the pin is driven to a
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1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
-0.1 0
10 20 30 40
ChangeinV (%)
OUT
I (mA)
OUT
50
+125 C°
+25 C°
-40 C°
ReferredtoI =50mA
OUT
0.050
0.025
0
-0.025
-0.050
-0.075
-0.100
-0.125
-0.150
50
500 1000
ChangeinV (%)
OUT
I (mA)
OUT
1500
+125 C°
+25 C°
- °40 C
ReferredtoI =50mA
OUT
0.05
0.04
0.03
0.02
0.01
0
-0.01
-0.02
-0.03
-0.04
-0.05
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
ChangeinV (%)
OUT
V V-
IN OUT
(V)
4.5
T = 40- °JC
TJ=+25°C
TJ=+125°C
100
75
50
25
0
0
0.5 1.0
DropoutVoltage(mV)
I (A)
OUT
1.5
+125 C°
+25 C°
- °40 C
200
180
160
140
120
100
80
60
40
20
0
0.9
1.4 1.9 2.4 2.9 3.4
DropoutVoltage(mV)
V V-
BIAS OUT
(V)
3.9
+125 C°
+25 C°
-40°C
I =1.5A
OUT
60
50
40
30
20
10
0
0.9
1.4 1.9 2.4 2.9 3.4
DropoutV
oltage(mV)
V -
BIASVOUT
(V)
3.9
+125 C°
+25 C°
-40°C
I =500mA
OUT
TPS74301
SBVS065E – DECEMBER 2005 – REVISED MAY 2007
At TJ= +25 ° C, V unless otherwise noted.
= 1.5V, VIN= V
OUT
LOAD REGULATION LOAD REGULATION
Figure 3. Figure 4.

TYPICAL CHARACTERISTICS

OUT(TYP)
+ 0.3V, V
BIAS
= 3.3V, I
= 50mA, EN = VIN, CIN= 1 µ F, C
OUT
= 4.7 µ F, and C
BIAS
= 10 µ F,
OUT
LINE REGULATION I
AND TEMPERATURE (TJ)
OUT
Figure 5. Figure 6.
VINDROPOUT VOLTAGE vs VINDROPOUT VOLTAGE vs
V
– V
VINDROPOUT VOLTAGE vs
BIAS
AND TEMPERATURE (TJ) V
OUT
– V
BIAS
AND TEMPERATURE (TJ)
OUT
6
Figure 7. Figure 8.
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1400
1300
1200
1100
1000
900
800
700
600
500
50
500 1000
DropoutVoltage(mV)
I (mA)
OUT
1500
+125 C°
+25 C°
- °40 C
90
80
70
60
50
40
30
20
10
0
P
ower
-SupplyRejection(dB)
10 100
1k
10k 100k
1M
10M
Frequency(Hz)
I =1.5A
OUT
100
90
80
70
60
50
40
30
20
10
0
10
100 1k 10k 100k 1M
Power
-SupplyRejectionRatio(dB)
Frequency(Hz)
10M
V =1.8,V =1.5V
IN OUT OUT
,I =1.5A
C =0 F
OUT
m
C =10 F
OUT
m
C =100 F
OUT
m
100
90
80
70
60
50
40
30
20
10
0
10
100 1k 10k 100k 1M
Power
-SupplyRejectionRatio(dB)
Frequency(Hz)
10M
V =1.8,V =1.5V
IN OUT OUT
,I =100mA
C =10 F
OUT
m
C =100 F
OUT
m
C =0 F
OUT
m
90
80
70
60
50
40
30
20
10
0
0
0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25
Power-SupplyRejectionRatio(dB)
V V-
IN OUT
(V)
2.50
1kHz
100kHz
300kHz
700kHz
I =1.5A
OUT
1
0.1
0.01
100
1k 10k
OutputSpectralNoiseDensity(mV/Ö
)
Hz
Frequency(Hz)
100k
I =1.5A
OUT
V =1.1V
OUT
At TJ= +25 ° C, V unless otherwise noted.
= 1.5V, VIN= V
OUT
V
TYPICAL CHARACTERISTICS (continued)
OUT(TYP)
DROPOUT VOLTAGE vs
BIAS
I
AND TEMPERATURE V
OUT
+ 0.3V, V
BIAS
= 3.3V, I
= 50mA, EN = VIN, CIN= 1 µ F, C
OUT
TPS74301
SBVS065E – DECEMBER 2005 – REVISED MAY 2007
= 4.7 µ F, and C
BIAS
PSRR vs FREQUENCY
BIAS
= 10 µ F,
OUT
Figure 9. Figure 10.
VINPSRR vs FREQUENCY VINPSRR vs FREQUENCY
Figure 11. Figure 12.
VINPSRR vs VIN– V
OUT
NOISE SPECTRAL DENSITY
Figure 13. Figure 14.
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20mV/div
20mV/div
20mV/div
20mV/div
1V/div
Time(50 s/div)m
4.3V
C =2x470 F(OSCON)
OUT
m
C =100 F(Cer.)
OUT
m
C =10 F(Cer.)
OUT
m
1V/ sm
3.3V
C =0 F
OUT
m
4.3V
10mV/div
10mV/div
10mV/div
10mV/div
500mV/div
Time(50 s/div)m
C =2x470 F(OSCON)
OUT
m
C =100 F(Cer.)
OUT
m
C =10 F(Cer.)
OUT
m
C =0 F
OUT
m
2.5V
1.5V
V =1.2V
OUT
1V/ sm
50mV/div
50mV/div
50mV/div
50mV/div
1A/div
Time(50 s/div)m
50mA
C =2x470 F(OSCON)
OUT
m
C =100 F(Cer.)
OUT
m
C =10 F(Cer.)
OUT
m
1A/ sm
C =0 F
OUT
m
1.5A
500mV/div
Time(20ms/div)
V
PG
V
TRACK
I =500mA
OUT
V
OUT
1V/div
Time(20ms/div)
V (500mV/div)
PG
V
OUT
V =V
IN BIAS EN
=V
2.85
2.65
2.45
2.25
2.05
1.85
1.65
1.45
1.25 0
0.5 1.0
BiasCurrent(mA)
I (A)
OUT
1.5
+125 C°
+25 C°
- °40 C
TPS74301
SBVS065E – DECEMBER 2005 – REVISED MAY 2007
At TJ= +25 ° C, V unless otherwise noted.
= 1.5V, VIN= V
OUT
V
LINE TRANSIENT VINLINE TRANSIENT (1.5A)
BIAS
Figure 15. Figure 16.
OUTPUT LOAD TRANSIENT RESPONSE TRACKING RESPONSE
TYPICAL CHARACTERISTICS (continued)
OUT(TYP)
+ 0.3V, V
BIAS
= 3.3V, I
= 50mA, EN = VIN, CIN= 1 µ F, C
OUT
= 4.7 µ F, and C
BIAS
= 10 µ F,
OUT
8
Figure 17. Figure 18.
POWER-UP/POWER-DOWN I
Figure 19. Figure 20.
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vs I
BIAS
AND TEMPERATURE
OUT
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3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
2.0
2.5 3.0 3.5 4.0 4.5
BiasCurrent(mA)
V (V)
BIAS
5.0
+125 C°
+25 C°
- °40 C
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
-40
-20 0 20 40 60 80 100
BiasCurrent( A)m
JunctionTemperature( C)°
120
V =2.375V
BIAS
V =5.5V
BIAS
1V/div
1V/div
Time(50 s/div)m
V
OUT
0V
1.1V
V
EN
V =V
I =1.5A
TRACK IN
OUT
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
V Low-LevelPGVoltage(V)
OL
0
2 4
6 8 10
12
PGCurrent(mA)
Time(20 s/div)m
V
OUT
50mV/div
I
OUT
500mA/div
OutputOpen
OutputShorted
At TJ= +25 ° C, V unless otherwise noted.
= 1.5V, VIN= V
OUT
TYPICAL CHARACTERISTICS (continued)
AND V
+ 0.3V, V
OUT
OUT(TYP)
I
vs V
BIAS
BIAS
Figure 21. Figure 22.
BIAS
= 3.3V, I
= 50mA, EN = VIN, CIN= 1 µ F, C
OUT
I
BIAS
TPS74301
SBVS065E – DECEMBER 2005 – REVISED MAY 2007
= 4.7 µ F, and C
BIAS
SHUTDOWN vs TEMPERATURE
= 10 µ F,
OUT
TURN-ON RESPONSE–QFN PACKAGE LOW-LEVEL PG VOLTAGE vs PG CURRENT
Figure 23. Figure 24.
OUTPUT SHORT-CIRCUIT RECOVERY
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Figure 25.
9
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