Texas Instruments TPS3808-EP Datasheet

Delay (s) = CT (nF) + 0.5 x 10−3 (s)

20ms Delay

300ms Delay

(c)

(b)

(a)

175

3.3V

TPS3808G33

V

DD

SENSE

CTRESET

3.3V

TPS3808G33

V

DD

SENSE

C

T

C

T

RESET

3.3V

TPS3808G33

V

DD

SENSE

C

T

50k

Ω

RESET

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SBVS103D –APRIL 2008–REVISED DECEMBER 2014

TPS3808-EP Low Quiescent Current, Programmable Delay Supervisory Circuit

1 Features 2 Applications

1

• Controlled Baseline
– One Assembly Site
– One Test Site
– One Fabrication Site

• Extended Temperature Performance of
–55°C to 125°C

• Enhanced Diminishing Manufacturing Sources
(DMS) Support

• Enhanced Product-Change Notification

• Qualification Pedigree

(1)

• Power-On Reset Generator With Adjustable Delay
Time: 1.25 ms to 10 s

• Very Low Quiescent Current: 2.4 μA Typical

• High Threshold Accuracy: 0.5% Typical

• Fixed Threshold Voltages for Standard Voltage
Rails From 0.9 V to 5 V and Adjustable Voltage
Down to 0.4 V Are Available

• Manual Reset (MR) Input

• Open-Drain RESET Output

• Temperature Range: –55°C to 125°C

• Small SOT-23 Package

(1) Component qualification in accordance with JEDEC and

industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited Device Information
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.

• DSP or Microcontroller Applications

• Notebook/Desktop Computers

• PDAs and Hand-Held Products

• Portable and Battery Powered Products

• FPGA and ASIC Applications

3 Description

The TPS3808xxx family of microprocessor
supervisory circuits monitors system voltages from

0.4 V to 5.0 V, asserting an open-drain RESET signal
when the SENSE voltage drops below a preset
threshold or when the manual reset (MR) pin drops to
a logic low. The RESET output remains low for the
user-adjustable delay time after the SENSE voltage
and manual reset (MR) return above the respective
thresholds.

The TPS3808 uses a precision reference to achieve

0.5% threshold accuracy for VIT≤ 3.3 V. The reset
delay time can be set to 20 ms by disconnecting the
CTpin, 300 ms by connecting the CTpin to VDDusing
a resistor, or can be user-adjusted between 1.25 ms
and 10 s by connecting the CTpin to an external
capacitor. The TPS3808 has a very low typical
quiescent current of 2.4 μA, so it is well-suited to
battery-powered applications. It is available in a small
SOT-23 package, and is fully specified over a
temperature range of –55°C to +125°C (TJ).

PART NUMBER PACKAGE BODY SIZE (NOM)

TPS3808-EP SOT (6) 2.90 mm x 1.60 mm
(1) For all available packages, see the orderable addendum at

the end of the datasheet.

TPS3808-EP

(1)

Typical Application Circuit

1

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

TPS3808-EP

SBVS103D –APRIL 2008–REVISED DECEMBER 2014

www.ti.com

Table of Contents

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description ............................................................. 1

4 Revision History..................................................... 2

5 Pin Configuration and Functions......................... 3

6 Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 4

6.5 Electrical Characteristics........................................... 5

6.6 Switching Characteristics.......................................... 5

6.7 Typical Characteristics.............................................. 7

7 Detailed Description .............................................. 9

7.1 Overview ................................................................... 9

7.2 Functional Block Diagrams ....................................... 9

7.3 Feature Description................................................... 9

7.4 Device Functional Modes.......................................... 9

8 Application and Implementation ........................ 10

8.1 Application Information............................................ 10

8.2 Typical Application .................................................. 13

9 Power Supply Recommendations...................... 15

10 Layout................................................................... 15

10.1 Layout Guidelines ................................................. 15

10.2 Layout Example .................................................... 15

11 Device and Documentation Support ................. 16

11.1 Trademarks ........................................................... 16

11.2 Electrostatic Discharge Caution............................ 16

11.3 Glossary ................................................................ 16

12 Mechanical, Packaging, and Orderable

Information........................................................... 16

4 Revision History

Changes from Revision C (September 2008) to Revision D Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and

Mechanical, Packaging, and Orderable Information section ................................................................................................. 4

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V

DD

SENSE

C

T

RESET

GND

MR

1

2

3

6

5

4

TPS3808-EP

www.ti.com

SBVS103D –APRIL 2008–REVISED DECEMBER 2014

5 Pin Configuration and Functions

DBV PACKAGE

SOT-23

(TOP VIEW)

Pin Functions

PIN

NAME NO.

RESET 1 O RESET is an open-drain output that is driven to a low impedance state when RESET is asserted

GND 2 — Ground
MR 3 I Driving the manual reset pin (MR) low asserts RESET. MR is internally tied to VDDby a 90kΩ pullup

C

T

4 I Reset period programming pin. Connecting this pin to VDDthrough a 40-kΩ to 200-kΩ resistor or

SENSE 5 I This pin is connected to the voltage to be monitored. If the voltage at this terminal drops below the

V

DD

6 I Supply voltage. It is good analog design practice to place a 0.1-μF ceramic capacitor close to this pin.

I/O DESCRIPTION

(either the SENSE input is lower than the threshold voltage (VIT) or the MR pin is set to a logic low).
RESET remains low (asserted) for the reset period after both SENSE is above VITand MR is set to a
logic high. A pullup resistor from 10 kΩ to 1 MΩ should be used on this pin, and allows the reset pin to
attain voltages higher than VDD.

resistor.

leaving it open results in fixed delay times (see Switching Characteristics). Connecting this pin to a
ground referenced capacitor ≥ 100 pF gives a user-programmable delay time. See the Selecting the

Reset Delay Time section for more information.

threshold voltage VIT, then RESET is asserted.

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TPS3808-EP

SBVS103D –APRIL 2008–REVISED DECEMBER 2014

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6 Specifications

6.1 Absolute Maximum Ratings

Over operating junction temperature range, unless otherwise noted.

Input voltage, V
CTvoltage, V
Other voltage: V
RESET pin current 5 mA
Operating junction temperature, T
Storage temperature, T

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) As a result of the low dissipated power in this device, it is assumed that TJ= TA.

CT

DD

RESET

, VMR, V

stg

SENSE

(2)

J

6.2 ESD Ratings

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins

V

(ESD)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

Electrostatic discharge V

Charged device model (CDM), per JEDEC specification JESD22-C101, all ±1000

(2)

pins

(1)

MIN MAX UNIT

–0.3 7.0
–0.3 VDD+ 0.3 V
–0.3 7

–55 150
–65 150

°C

VALUE UNIT

(1)

±3000

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN NOM MAX UNIT

V

DD

Power-up reset voltage VOL(max) = 0.2 V, I

Input supply range 1.7 6.5 V

= 15 μA 0.8 V

RESET

6.4 Thermal Information

TPS3808-EP

THERMAL METRIC

R

θJA

R

θJC(top)

R

θJB

ψ

JT

ψ

JB

Junction-to-ambient thermal resistance 180.9
Junction-to-case (top) thermal resistance 117.8
Junction-to-board thermal resistance 27.8 °C/W
Junction-to-top characterization parameter 1.12
Junction-to-board characterization parameter 27.3

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(1)

DBV UNIT

6 PINS

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6.5 Electrical Characteristics

1.7 V ≤ VDD≤ 6.5 V, R

otherwise noted. Typical values are at TJ= +25°C.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

DD

I

DD

V

OL

V

IT

V

HYS

R

I

SENSE

I

OH

C

IN

V

IL

V

IH

θ

JA

(1) The lowest supply voltage (VDD) at which RESET becomes active. T

Input supply range 1.7 6.5 V

Supply current (current into VDDpin) μA

Low-level output voltage

Power-up reset voltage

Negative-going input
threshold accuracy

Hysteresis on VITpin V

MR Internal pullup resistance 70 90 kΩ

MR

Input current at
SENSE pin

RESET leakage current V
Input capacitance,

any pin
MR logic low input 0 0.3 V

MR logic high input 0.7 V
Thermal resistance, junction-to-ambient 290 °C/W

LRESET

= 100 kΩ, C

= 50 pF, over operating temperature range (TJ= –55°C to +125°C), unless

LRESET

VDD= 3.3 V, RESET not asserted
MR, RESET, CTopen

VDD= 6.5 V, RESET not asserted
MR, RESET, CTopen

1.3 V ≤ VDD< 1.8 V, IOL= 0.4 mA 0.3

1.8 V ≤ VDD≤ 6.5 V, IOL= 1.0 mA 0.4 V

(1)

VOL(max) = 0.2 V, I
TPS3808G01 –2.0% ±1.0% +2.0%
VIT≤ 3.3 V –1.7% ±0.5% +1.7%

3.3 V < VIT≤ 5.0 V –2.0% ±1.0% +2.0%
TPS3808G01 1.5% 3.0%
Fixed versions 1.0% 2.5%

TPS3808G01 V
Fixed versions V

= V

SENSE
SENSE

RESET

IT

= 6.5 V 1.7 μA

= 6.5 V, RESET not asserted 300 nA
CTpin VIN= 0 V to V
Other pins VIN= 0 V to 6.5 V 5

DD

rise(VDD)

SBVS103D –APRIL 2008–REVISED DECEMBER 2014

= 15 μA 0.8

RESET

–25 25 nA

DD

≥ 15 μs/V.

TPS3808-EP

2.4 5.0

2.7 6.0

5

DD

V

DD

IT

pF

V

6.6 Switching Characteristics

1.7 V ≤ VDD≤ 6.5 V, R
otherwise noted. Typical values are at TJ= +25°C.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Input pulse width to

t

w

RESET

t

RESET delay time See Timing Diagram

d

Propagation delay MR to RESET VIH= 0.7 VDD, VIL= 0.3 V

t

pHL

High-to-low level RESET
delay

LRESET

= 100 kΩ, C

= 50 pF, over operating temperature range (TJ= –55°C to +125°C), unless

LRESET

SENSE VIH= 1.05 VIT, VIL= 0.95 V
MR VIH= 0.7 VDD, VIL= 0.3 V
CT= Open 12 20 29

CT= V

DD

CT= 100 pF 0.75 1.25 1.8
CT= 180 nF 0.7 1.2 1.8 s

SENSE to RESET VIH= 1.05 VIT, VIL= 0.95 V

DD

DD

IT

20

0.00

μs

1

180 300 440 ms

150 ns

IT

20 μs

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Time

0.8V

0.0V

VIT+ V

HYS

V

IT

0.7V

DD

0.3V

DD

MR

SENSE

RESET

V

DD

t

D

t

D

t

D

tD= Reset Delay

= Undefined State

TPS3808-EP

SBVS103D –APRIL 2008–REVISED DECEMBER 2014

www.ti.com

Figure 1. TPS3808 Timing Diagram Showing MR and SENSE Reset Timing

Table 1. Truth Table

MR SENSE > V

IT

L 0 L
L 1 L
H 0 L
H 1 H

RESET

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1.0

0.8

0.6

0.4

0.2
0

10 30 50 70 90 110 130

Temperature (°C)

−50 −30 −10

−1.0

−0.8

−0.6

−0.4

−0.2

Normalized V

IT

(%)

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5
0

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

V

OL

Low−Level RESET Voltage (V)

VDD= 1.8V

RESET

Current (mA)

10

8
6
4
2
0

10 30 50 70 90 110 130

Temperature (°C)

−50 −30 −10

−10

−8

−6

−4

−2

Normalized RESET Timeout Period (%)

100

10

1

0 5 10 15 20 30 35 4525

Overdrive (%VIT)

5040

Transient Duration below V

IT

(µs)

RESET OCCURS

ABOVE THE CURVE

100

10

1

0.1

0.01

0.001

0.0001 0.001 0.01 0.1
CT(µF)

101

−40°C, +25°C, +125°C

RESET Timeout (sec)

0 1 2 3 4 5 6 7

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5
0

−40

_

C

+25_C

+85_C

+125_C

I

DD

(µA)

VDD (V)

www.ti.com

6.7 Typical Characteristics

At TJ= +25°C, VDD= 3.3 V, R

LRESET

= 100kΩ, and C

= 50pF, unless otherwise noted.

LRESET

TPS3808-EP

SBVS103D –APRIL 2008–REVISED DECEMBER 2014

Figure 2. Supply Current vs Supply Voltage

Figure 3. RESET Timeout Period vs C

T

CT= Open, CT= VDD, CT= Any

Figure 4. Normalized RESET Timeout Period vs Figure 5. Maximum Transient Duration at Sense vs Sense

Temperature Threshold Overdrive Voltage

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Figure 6. Normalized Sense Threshold Voltage (VIT) vs

Temperature

Figure 7. Low-Level RESET Voltage vs RESET Current

Product Folder Links: TPS3808-EP

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1
0

V

OL

Low−Level RESET Voltage (V)

RESET Current (mA)

VDD= 3.3V

VDD= 6.5V

TPS3808-EP

SBVS103D –APRIL 2008–REVISED DECEMBER 2014

Typical Characteristics (continued)

www.ti.com

At TJ= +25°C, VDD= 3.3 V, R

= 100kΩ, and C

LRESET

= 50pF, unless otherwise noted.

LRESET

Figure 8. Low-Level RESET Voltage vs RESET Current

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