Texas Instruments TPS2546RTER Schematic [ru]
OUT
GND
FAULT
ILIM_LO
EN
R
ILIM_LO
R
STATUS
(10 kW)
Power Switch EN
4.5V – 5.5V
TPS2546
0.1 uF
C
USB
Fault Signal
DM_IN
DP_IN
VBUS
DD+
GND
USB
Connector
To Portable Device à
Power Bus
CTL1
CTL2
CTL3
ILIM_SEL
ILIM Select
DM_OUT
DP_OUT
To Host Controller à
Mode Select I/O
IN
STATUS
STATUS Signal
R
ILIM_HI
ILIM_HI
R
FAULT
(10 kW)
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Folder
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TPS2546
SLVSBJ2B –FEBRUARY 2013–REVISED JANUARY 2016
TPS2546 USB Charging Port Controller and Power Switch With Load Detection
1 Features 2 Applications
1
• D+/D– CDP/DCP Modes per USB Battery
Charging Specification 1.2
• D+/D– Shorted Mode per Chinese
Telecommunication Industry Standard YD/T
1591-2009
• Supports Non-BC1.2 Charging Modes by The TPS2546 is a USB charging port controller and
Automatic Selection:
– D+/D– Divider Modes 2 V/2.7 V and 2.7 V/2 V
– D+/D– 1.2-V Mode
• Supports Sleep-Mode Charging and charging of popular mobile phones, tablets, and
Mouse/Keyboard Wakeup
• Automatic SDP/CDP Switching for Devices That
Do Not Connect to CDP Ports
• Load Detection for Power Supply Control in S4/S5
Charging and Port Power Management in All
Charge Modes
• Compatible With USB 2.0 and 3.0 Power Switch
Requirements
• Integrated 73-mΩ (Typical) High-Side MOSFET
• Adjustable Current-Limit up to 3 A (Typical)
• Operating Range: 4.5 V to 5.5 V
• Max Device Current:
– 2 µA When Device Disabled
– 270 µA When Device Enabled
• Drop-In and BOM Compatible With TPS2543
• Available in 16-Pin WQFN (3.00 mm × 3.00 mm)
Package
• 8-kV ESD Rating on DM/DP Pins
• UL Listed File No. E169910 and CB certified
• USB Ports (Host and Hubs)
• Notebook and Desktop PCs
• Universal Wall-Charging Adapters
3 Description
power switch with an integrated USB 2.0 high-speed
data line (D+/D–) switch. TPS2546 provides the
electrical signatures on D+/D– to support charging
schemes listed under Feature Description. TI tests
media devices with the TPS2546 to ensure
compatibility with both BC1.2 compliant, and nonBC1.2 compliant devices.
In addition to charging popular devices, the TPS2546
also supports two distinct power management
features, namely, power wake and port power
management (PPM) through the STATUS pin. Power
wake allows for power supply control in S4/S5
charging and PPM the ability to manage port power in
a multi-port application. Additionally, system wake up
(from S3) with a mouse/keyboard (both low speed
and full speed) is fully supported in the TPS2546.
The TPS2546 73-mΩ power-distribution switch is
intended for applications where heavy capacitive
loads and short-circuits are likely to be encountered.
Two programmable current thresholds provide
flexibility for setting current limits and load detect
thresholds.
Device Information
PART NUMBER PACKAGE BODY SIZE (NOM)
TPS2546 WQFN (16) 3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
(1)
1
Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS2546
SLVSBJ2B –FEBRUARY 2013–REVISED JANUARY 2016
www.ti.com
Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions......................... 3
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 5
6.6 Electrical Characteristics: High-Bandwidth Switch.... 6
6.7 Electrical Characteristics: Charging Controller ......... 7
6.8 Typical Characteristics.............................................. 9
7 Parameter Measurement Information ................ 12
8 Detailed Description............................................ 14
8.1 Overview ................................................................. 14
8.2 Functional Block Diagram ....................................... 15
8.3 Feature Description................................................. 15
8.4 Device Functional Modes........................................ 25
9 Application and Implementation ........................ 28
9.1 Application Information............................................ 28
9.2 Typical Application .................................................. 29
10 Power Supply Recommendations..................... 32
11 Layout................................................................... 32
11.1 Layout Guidelines ................................................. 32
11.2 Layout Example .................................................... 33
12 Device and Documentation Support ................. 34
12.1 Documentation Support ....................................... 34
12.2 Community Resources.......................................... 34
12.3 Trademarks........................................................... 34
12.4 Electrostatic Discharge Caution............................ 34
12.5 Glossary................................................................ 34
13 Mechanical, Packaging, and Orderable
Information........................................................... 34
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (Febuary 2013) to Revision B Page
• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
Changes from Original (February 2013) to Revision A Page
• Changed the device From: Preview To: Production............................................................................................................... 1
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1
2
3
4
5 6 7 8
9
10
11
12
13141516
Thermal Pad
IN
DM_OUT
DP_OUT
EN
OUT
DM_IN
DP_IN
STATUS
ILIM_HI
ILIM_LO
GND
FAULT
www.ti.com
5 Pin Configuration and Functions
TPS2546
SLVSBJ2B –FEBRUARY 2013–REVISED JANUARY 2016
RTE Package
16-Pin WQFN
Top View
Pin Functions
PIN
NO. NAME
1 IN P
2 DM_OUT I/O D– data line to USB host controller.
3 DP_OUT I/O D+ data line to USB host controller.
4 ILIM_SEL I
5 EN I and power switches and holds OUT in discharge. Can be tied directly to IN or GND without pullup or
6 CTL1 I
7 CTL2 I
8 CTL3 I
9 STATUS O Active-low open-drain output, asserted in load detection conditions.
10 DP_IN I/O D+ data line to downstream connector.
11 DM_IN I/O D– data line to downstream connector.
12 OUT P Power-switch output.
13 FAULT O Active-low open-drain output, asserted during overtemperature or current limit conditions.
14 GND P Ground connection.
15 ILIM_LO I
16 ILIM_HI I External resistor connection used to set the high-current-limit threshold.
— —
(1) G = ground, I = input, O = output, P = power.
Thermal Internally connected to GND; used to heatsink the part to the circuit board traces. Connect to GND
Pad plane.
TYPE
(1)
Input voltage and supply voltage; connect 0.1 μF or greater ceramic capacitor from IN to GND as close
to the device as possible.
Logic-level input signal used to control the charging mode, current limit threshold, and load detection;
see Table 3. Can be tied directly to IN or GND without pullup or pulldown resistor.
Logic-level input for turning the power switch and the signal switches on/off; logic low turns off the signal
pulldown resistor.
Logic-level inputs used to control the charging mode and the signal switches; see Table 3. Can be tied
directly to IN or GND without pullup or pulldown resistor.
External resistor connection used to set the low current-limit threshold and the load detection current
threshold. A resistor to ILIM_LO is optional; see Current-Limit Settings in Detailed Description.
DESCRIPTION
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TPS2546
SLVSBJ2B –FEBRUARY 2013–REVISED JANUARY 2016
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)
IN, EN, ILIM_LO, ILIM_HI, FAULT, STATUS,
Voltage V
Input clamp current DP_IN, DM_IN, DP_OUT, DM_OUT ±20 mA
Continuous current in SDP or CDP
mode
Continuous current in BC1.2 DCP mode DP_IN to DM_IN ±50 mA
Continuous output current OUT Internally limited
Continuous output sink current FAULT, STATUS 25 mA
Continuous output source current ILIM_LO, ILIM_HI Internally limited mA
Operating junction temperature, T
J
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
ILIM_SEL, CTL1, CTL2, CTL3, OUT
IN to OUT –7 7
DP_IN, DM_IN, DP_OUT, DM_OUT –0.3 (IN + 0.3) or 5.7
DP_IN to DP_OUT or DM_IN to DM_OUT ±100 mA
(1)
MIN MAX UNIT
–0.3 7
–40 Internally limited °C
6.2 ESD Ratings
HBM ±2000
V
(ESD)
Electrostatic
discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-
(1)
001
Charged-device model (CDM), per JEDEC specification JESD22-C101
HBM wrt GND and each
other, DP_IN, DM_IN, ±8000 V
OUT
(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
voltages are referenced to GND (unless otherwise noted)
MIN MAX UNIT
V
IN
V
IH
V
IL
I
OUT
R
ILIM_XX
T
J
Input voltage, IN 4.5 5.5 V
Input voltage, logic-level inputs, EN, CTL1, CTL2, CTL3, ILIM_SEL 0 5.5 V
Input voltage, data line inputs, DP_IN, DM_IN, DP_OUT, DM_OUT 0 V
High-level input voltage, EN, CTL1, CTL2, CTL3, ILIM_SEL 1.8 V
Low-level input voltage, EN, CTL1, CTL2, CTL3, ILIM_SEL 0.8 V
Continuous current, data line inputs, SDP or CDP mode, DP_IN to DP_OUT, DM_IN to
DM_OUT
Continuous current, data line inputs, BC1.2 DCP mode, DP_IN to DM_IN ±15 mA
Continuous output current, OUT 0 2.5 A
Continuous output sink current, FAULT, STATUS 0 10 mA
Current-limit set resistors 16.9 750 kΩ
Operating virtual junction temperature –40 125 °C
VALUE UNIT
±500
V
IN
±30 mA
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TPS2546
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SLVSBJ2B –FEBRUARY 2013–REVISED JANUARY 2016
6.4 Thermal Information
TPS2546
THERMAL METRIC
(1)
RTE (WQFN) UNIT
16 PINS
R
θJA
R
θJC(top)
R
θJB
ψ
JT
ψ
JB
R
θJC(bot)
Junction-to-ambient thermal resistance 53.4 °C/W
Junction-to-case (top) thermal resistance 51.4 °C/W
Junction-to-board thermal resistance 17.2 °C/W
Junction-to-top characterization parameter 3.7 °C/W
Junction-to-board characterization parameter 20.7 °C/W
Junction-to-case (bottom) thermal resistance 3.9 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics
Unless otherwise noted: –40 ≤ TJ≤ 125°C, 4.5 V ≤ VIN≤ 5.5 V, VEN= VIN, V
R
STATUS
= 10 kΩ, R
ILIM_HI
= 20 kΩ, R
= 80.6 kΩ. Positive currents are into pins. Typical values are at 25°C. All voltages
ILIM_LO
are with respect to GND.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SWITCH
TJ= 25°C, I
R
DS(on)
ON resistance
(1)
–40°C ≤ TJ≤ 85°C, I
–40°C ≤ TJ≤ 125°C, I
t
t
t
t
I
r
f
on
off
REV
OUT voltage rise time 0.7 1 1.6
OUT voltage fall time 0.2 0.35 0.5
OUT voltage turnon time 2.7 4
OUT voltage turnoff time 1.7 3
Reverse leakage current 2 µA
VIN= 5 V, CL= 1 µF, RL= 100 Ω (see Figure 23 and
Figure 24)
VIN= 5 V, CL= 1 µF, RL= 100 Ω (see Figure 23 and
Figure 25)
V
= 5.5 V, VIN= VEN= 0 V, –40 ≤ TJ≤ 85°C,
OUT
Measure I
DISCHARGE
R
DCHG
t
DCHG_L
t
DCHG_S
OUT discharge resistance 400 500 630 Ω
Long OUT discharge hold time Time V
Short OUT discharge hold time Time V
OUT
OUT
EN, ILIMSEL, CTL1, CTL2, CTL3 INPUTS
Input pin rising logic threshold
voltage
Input pin falling logic threshold
voltage
Hysteresis
(2)
Input current Pin voltage = 0 V or 5.5 V –0.5 0.5 µA
ILIMSEL CURRENT LIMIT
V
ILIM_SEL
V
ILIM_SEL
V
ILIM_SEL
V
ILIM_SEL
V
ILIM_SEL
VIN= 5 V, R = 0.1Ω, lead length = 2 inches
(see Figure 27)
I
t
OS
IOS
OUT short-circuit current limit
Response time to OUT short-
(2)
circuit
(1)
(1) Pulse-testing techniques maintain junction temperature close to ambient temperature; Thermal effects must be taken into account
separately.
(2) These parameters are provided for reference only and do not constitute part of TI's published device specifications for purposes of TI's
product warranty.
= 2 A 73 84
OUT
= 2 A 73 105 mΩ
OUT
= 2 A 73 120
OUT
OUT
< 0.7 V (see Figure 26) 1.3 2 2.9 s
< 0.7 V (see Figure 26) 205 310 450 ms
= 0 V, R
= 0 V, R
= 0 V, R
= VIN, R
= VIN, R
= 210 kΩ 205 240 275
ILIM_LO
= 80.6 kΩ 575 625 680
ILIM_LO
= 22.1 kΩ 2120 2275 2430 mA
ILIM_LO
= 20 kΩ 2340 2510 2685
ILIM_HI
= 16.9 kΩ 2770 2970 3170
ILIM_HI
ILIM_SEL
= VIN, V
CTL1
= V
CTL2
= V
CTL3
1 1.35 1.7 V
0.85 1.15 1.45
= VIN. R
FAULT
ms
ms
200 mV
1.5 µs
=
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SLVSBJ2B –FEBRUARY 2013–REVISED JANUARY 2016
Electrical Characteristics (continued)
www.ti.com
Unless otherwise noted: –40 ≤ TJ≤ 125°C, 4.5 V ≤ VIN≤ 5.5 V, VEN= VIN, V
R
STATUS
= 10 kΩ, R
ILIM_HI
= 20 kΩ, R
= 80.6 kΩ. Positive currents are into pins. Typical values are at 25°C. All voltages
ILIM_LO
are with respect to GND.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
I
IN_OFF
I
IN_ON
UNDERVOLTAGE LOCKOUT
V
UVLO
FAULT
STATUS
THERMAL SHUTDOWN
Disabled IN supply current VEN= 0 V, V
V
= V
CTL1
V
= V
CTL1
Enabled IN supply current V
V
V
CTL1
CTL1
CTL1
= V
= V
= 0 V, V
= 0 V, –40 ≤ TJ≤ 85°C 0.1 2 µA
OUT
CTL2
CTL2
CTL2
CTL2
= VIN, V
= V
CTL3
= VIN, V
= VIN, V
CTL2
= V
= 0 V, V
CTL3
= VIN, V
= 0 V, V
CTL3
= VIN, V
CTL3
= V
CTL3
ILIM_SEL
IN
IN rising UVLO threshold voltage 3.9 4.1 4.3 V
Hysteresis
Output low voltage I
OFF-state leakage V
(2)
= 1 mA 100 mV
FAULT
= 5.5 V 1 µA
FAULT
Overcurrent FAULT rising and
falling deglitch
Output low voltage I
OFF-state leakage V
= 1 mA 100 mV
STATUS
= 5.5 V 1 µA
STATUS
Thermal shutdown threshold 155
Thermal shutdown threshold in
current-limit
Hysteresis
(2)
ILIM_SEL
ILIM_SEL
= VIN, V
= 0 V 165 220
CTL1
= V
CTL2
= V
CTL3
= 0 V 175 230
ILIM_SEL
ILIM_SEL
= V
= V
IN
IN
185 240 µA
195 250
215 270
100 mV
5 8.2 12 ms
135 °C
= VIN. R
20
FAULT
=
6.6 Electrical Characteristics: High-Bandwidth Switch
Unless otherwise noted: –40 ≤ TJ≤ 125°C, 4.5 V ≤ VIN≤ 5.5 V, VEN= VIN, V
R
STATUS
= 10 kΩ, R
ILIM_HI
= 20 kΩ, R
= 80.6 kΩ. Positive currents are into pins. Typical values are at 25°C. All voltages
ILIM_LO
are with respect to GND.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
HIGH-BANDWIDTH ANALOG SWITCH
V
DP/DM switch ON resistance Ω
Switch resistance mismatch between
DP / DM channels
DP/DM switch OFF-state capacitance
DP/DM switch ON-state capacitance
O
X
IRR
TALK
OFF-state isolation
ON-state cross channel isolation
OFF-state leakage current 0.1 1.5 µA
BW Bandwidth (–3 dB)
t
pd
Propagation delay
(1)
(2)
(3)
(3)
(3)
(3)
DP/DM_OUT
V
DP/DM_OUT
V
DP/DM_OUT
V
DP/DM_OUT
VEN= 0 V, V
f = 1 MHz
V
DP/DM_IN
VEN= 0 V, f = 250 MHz 33 dB
f = 250 MHz 52 dB
VEN= 0 V, V
measure I
RL= 50 Ω 2.6 GHz
(1) The resistance in series with the parasitic capacitance to GND is typically 250 Ω.
(2) The resistance in series with the parasitic capacitance to GND is typically 150 Ω
(3) These parameters are provided for reference only and do not constitute part of TI's published device specifications for purposes of TI's
product warranty.
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= 0 V, I
DP/DM_IN
= 2.4 V, I
= 0 V, I
= 2.4 V, I
DP/DM_IN
DP/DM_IN
DP/DM_IN
DP/DM_IN
= 0.3 V, Vac= 0.6 V
= 0.3 V, Vac= 0.6 V
DP/DM_IN
DP/DM_OUT
= 3.6 V, V
ILIM_SEL
= VIN, V
CTL1
= V
CTL2
= V
CTL3
= 30 mA 2 4
= –15 mA 3 6
= 30 mA 0.05 0.15
= –15 mA 0.05 0.15
,
pk–pk
, f = 1 MHz 5.4 6.2 pF
pk-pk
DP/DM_OUT
= 0 V,
0.25 ns
= VIN. R
FAULT
3 3.6 pF
=
Ω
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Electrical Characteristics: High-Bandwidth Switch (continued)
TPS2546
SLVSBJ2B –FEBRUARY 2013–REVISED JANUARY 2016
Unless otherwise noted: –40 ≤ TJ≤ 125°C, 4.5 V ≤ VIN≤ 5.5 V, VEN= VIN, V
R
STATUS
= 10 kΩ, R
ILIM_HI
= 20 kΩ, R
= 80.6 kΩ. Positive currents are into pins. Typical values are at 25°C. All voltages
ILIM_LO
ILIM_SEL
= VIN, V
CTL1
= V
CTL2
= V
CTL3
= VIN. R
FAULT
are with respect to GND.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
SK
Skew between opposite transitions of the
same port (t
PHL
– t
PLH
)
0.1 0.2 ns
6.7 Electrical Characteristics: Charging Controller
Unless otherwise noted: –40 ≤ TJ≤ 125°C, 4.5 V ≤ VIN≤ 5.5 V, VEN= VIN, V
R
FAULT
= R
STATUS
= 10 kΩ, R
ILIM_HI
= 20 kΩ, R
= 80.6 kΩ. Positive currents are into pins. Typical values are at 25°C. All
ILIM_LO
voltages are with respect to GND.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SHORTED MODE (BC1.2 DCP)
DP_IN / DM_IN shorting resistance VCTL1 = VIN, VCTL2 = VCTL3 = 0 V 125 200 Ω
1.2 V MODE
DP_IN /DM_IN output voltage 1.19 1.25 1.31 V
DP_IN /DM_IN output impedance 60 75 94 kΩ
DIVIDER1 MODE
DP_IN divider1 output voltage 1.9 2 2.1 V
DM_IN divider1 output voltage 2.57 2.7 2.84 V
DP_IN output impedance 8 10.5 12.5 kΩ
DM_IN output impedance 8 10.5 12.5 kΩ
DIVIDER2 MODE
DP_IN divider2 output voltage 2.57 2.7 2.84 V
DM_IN divider2 output voltage 1.9 2 2.1 V
DP_IN output impedance 8 10.5 12.5 kΩ
DM_IN output impedance 8 10.5 12.5 kΩ
CHARGING DOWNSTREAM PORT
V
DM_SRC
V
DAT_REF
V
LGC_SRC
I
DP_SINK
DM_IN CDP output voltage –250 µA < I
DP_IN rising lower window threshold
for V
Hysteresis
DM_SRC
activation
(1)
DP_IN rising upper window threshold
for V
Hysteresis
DM_SRC
de-activation
(1)
DP_IN sink current V
LOAD DETECT – NON-POWER WAKE
I
LD
t
LD_SET
IOUT rising load detect current
threshold
Hysteresis
(1)
Load detect set time 140 200 275 ms
Load detect reset time 1.9 3 4.2 s
(1) These parameters are provided for reference only and do not constitute part of Texas Instrument's published device specifications for
purposes of Texas Instrument's product warranty.
VCTL1 = VIN, VCTL2 = VCTL3 = 0 V
VCTL1 = VIN, VCTL2 = VCTL3 = 0 V
IOUT = 1 A
VCTL1 = VCTL2 = VCTL3 =
VIN
VCTL1 = VCTL2 = VCTL3 = VIN
VCTL1 = VCTL2 = VCTL3 =
VIN
VCTL1 = VCTL2 = VCTL3 = VIN
ILIM_SEL
V
DP_IN
µA
DP_IN
= VIN, V
CTL1
= 0 V, V
CTL2
= V
CTL3
= VIN.
= 0.6 V,
< 0 0.5 0.6 0.7 V
DM_IN
0.25 0.4 V
50 mV
0.8 1 V
100 mV
= 0.6 V 40 70 100 µA
635 700 765 mA
50 mA
=
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Electrical Characteristics: Charging Controller (continued)
www.ti.com
Unless otherwise noted: –40 ≤ TJ≤ 125°C, 4.5 V ≤ VIN≤ 5.5 V, VEN= VIN, V
R
FAULT
= R
STATUS
= 10 kΩ, R
ILIM_HI
= 20 kΩ, R
= 80.6 kΩ. Positive currents are into pins. Typical values are at 25°C. All
ILIM_LO
voltages are with respect to GND.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
LOAD DETECT – POWER WAKE
I
OS_PW
Power wake short-circuit current limit 32 55 78 mA
I
falling power wake reset current
OUT
detection threshold
Reset current hysteresis
(1)
VCTL1 = VCTL2 = 0 V, VCTL3 = VIN
Power wake reset time 10.7 15 20.6 s
ILIM_SEL
= VIN, V
CTL1
= 0 V, V
CTL2
= V
CTL3
= VIN.
23 45 67 mA
5 mA
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0
0.2
0.4
0.6
0.8
1
1.2
−40 −20 0 20 40 60 80 100
Junction Temperature (°C)
Disabled IN Supply Current (µA)
VIN = 5.5 V
G005
130
140
150
160
170
180
190
−40 −25 −10 5 20 35 50 65 80 95 110 125
Junction Temperature (°C)
Enabled IN Supply Current (µA)
VIN = 4.5 V
VIN = 5 V
VIN = 5.5 V
Device configured for SDP
V
ILIMSEL
= 0 V
G006
460
480
500
520
540
560
580
−40 −25 −10 5 20 35 50 65 80 95 110 125
Junction Temperature (°C)
OUT Discharge Resistance (Ω)
VIN = 4.5 V
VIN = 5 V
VIN = 5.5 V
G003
0
500
1000
1500
2000
2500
3000
3500
−40 −25 −10 5 20 35 50 65 80 95 110 125
Junction Temperature (°C)
OUT Short Circuit Current Limit (mA)
R
ILIM_LO
= 210 kΩ
R
ILIM_LO
= 80.6 kΩ
R
ILIM_HI
= 20 kΩ
R
ILIM_HI
= 16.9 kΩ
G004
50
60
70
80
90
100
−40 −25 −10 5 20 35 50 65 80 95 110 125
Junction Temperature (°C)
On Resistance (mΩ)
G001
0
0.05
0.1
0.15
0.2
0.25
0.3
−40 −25 −10 5 20 35 50 65 80 95 110 125
Junction Temperature (°C)
Reverse Leakage Current (µA)
G002
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6.8 Typical Characteristics
Figure 1. Power Switch ON Resistance vs Temperature Figure 2. Reverse Leakage Current vs Temperature
TPS2546
SLVSBJ2B –FEBRUARY 2013–REVISED JANUARY 2016
Figure 3. OUT Discharge Resistance vs Temperature Figure 4. OUT Short-Circuit Current Limit vs Temperature
Figure 5. Disabled in Supply Current vs Temperature Figure 6. Enabled in Supply Current - SDP vs Temperature
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0
60
O
IRR
- Off State Isolation - dB
10
40
20
50
0.01 1
Frequency - GHz
0.1 10
30
0
60
X
TALK
- ON State Cross-Channel Isolation - dB
10
40
20
50
0.01 1
Frequency - GHz
0.1 10
30
80
70
-20
0
Transmission Gain - dB
-20
-10
-15
-5
0.01 1
Frequency - GHz
0.1 10
0
100
200
300
400
500
600
700
0 1 2 3 4 5 6 7 8 9 10
Sinking Current (mA)
Output Low Voltage (mV)
TJ = −40°C
TJ = 25°C
TJ = 125°C
VIN = 4.5 V
G009
160
170
180
190
200
210
220
−40 −25 −10 5 20 35 50 65 80 95 110 125
Junction Temperature (°C)
Enabled IN Supply Current (µA)
VIN = 4.5 V
VIN = 5 V
VIN = 5.5 V
Device configured for CDP
G007
180
190
200
210
220
230
240
−40 −25 −10 5 20 35 50 65 80 95 110 125
Junction Temperature (°C)
Enabled IN Supply Current (µA)
VIN = 4.5 V
VIN = 5 V
VIN = 5.5 V
Device configured for DCP AUTO
G008
TPS2546
SLVSBJ2B –FEBRUARY 2013–REVISED JANUARY 2016
Typical Characteristics (continued)
Figure 7. Enabled in Supply Current - CDP vs Temperature Figure 8. Enabled in Supply Current - DCP Auto
vs Temperature
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Figure 9. Status and Fault Output Low Voltage
Figure 11. OFF-State Data Switch Isolation vs Frequency
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vs Sinking Current
Figure 10. Data Transmission Characteristics vs Frequency
Figure 12. ON-State Cross-Channel Isolation vs Frequency
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I
IN
V
5 V/div
EN
V
2 V/div
OUT
t - Time - 1 ms/div
R
LOAD
= 5
C = 150 FΩµ
LOAD
G021
52
53
54
55
56
57
58
59
−40 −25 −10 5 20 35 50 65 80 95 110 125
Junction Temperature (°C)
Power Wake Current Limit (mA)
G017
600
620
640
660
680
700
720
740
−40 −25 −10 5 20 35 50 65 80 95 110 125
Junction Temperature (°C)
Current (mA)
IOS - OUT Short Circuit Current Limit
ILD - I
OUT
Rising Load Detect Threshold
R
ILIM_LO
= 80.6 kΩ
G015
200
205
210
215
220
225
230
−40 −25 −10 5 20 35 50 65 80 95 110 125
Junction Temperature (°C)
Load Detect Set Time (ms)
G016
G013
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
Time (ns)
Differential Signal (V)
G014
0.5
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
Time (ns)
Differential Signal (V)
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SLVSBJ2B –FEBRUARY 2013–REVISED JANUARY 2016
Typical Characteristics (continued)
Figure 13. Eye Diagram Using USB Compliance Test Pattern Figure 14. Eye Diagram Using USB Compliance Test Pattern
(With No Switch) (With Data Switch)
TPS2546
Figure 15. IOUT Rising Load Detect Threshold and Out Figure 16. Load Detect Set Time vs Temperature
Short-Circuit Current Limit vs Temperature
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Figure 17. Power Wake Current Limit vs Temperature
Figure 18. Turnon Response
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10%
90%
V
OUT
t
r
t
f
R
L
C
L
I
1 A/div
IN
V
5 V/div
EN
V
5 V/div
/FAULT
t - Time - 5 ms/div
R
ILM_HI
= 20 kΩ
G024
I
2 A/div
IN
V
2 V/div
OUT
V
5 V/div
/FAULT
t - Time - 2 ms/div
R
ILIM_HI
LOAD
LOAD
= 20 k
R = 5
C = 150 F
Ω
Ω
µ
G025
I
IN
V
5 V/div
EN
V
2 V/div
OUT
t - Time - 1 ms/div
R
LOAD
= 5
C = 150 FΩµ
LOAD
G022
I
IN
V
5 V/div
EN
V
5 V/div
/FAULT
t - Time - 2 ms/div
R
ILM_LO
= 80.6 kΩ
G023
TPS2546
SLVSBJ2B –FEBRUARY 2013–REVISED JANUARY 2016
Typical Characteristics (continued)
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Figure 19. Turnoff Response
Figure 21. Device Enabled Into Short-Circuit - Thermal Figure 22. Short-Circuit to Full Load Recovery
Cycling
7 Parameter Measurement Information
Figure 20. Device Enabled Into Short-Circuit
Figure 23. Out Rise/Fall Test Load
Figure 24. Power-ON and OFF Timing
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Product Folder Links: TPS2546
t
IOS
I
OUT
I
OS
5 V
V
OUT
0 V
t
DCHG
V
EN
V
OUT
t
on
50 %
50 %
t
off
90 %
10 %
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TPS2546
SLVSBJ2B –FEBRUARY 2013–REVISED JANUARY 2016
Parameter Measurement Information (continued)
Figure 25. Enable Timing, Active High Enable
Figure 26. Out Discharge During Mode Change
Figure 27. Output Short-Circuit Parameters
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