TEXAS INSTRUMENTS TPS2456 Technical data

SENSEA

PGA

ENA

FLTA

SENMA

GAT1A

OUTA

SETA

GAT2A

SENPA

GND

PGB

ENB

FLTB

TPS2456

36 PIN QFN

CTB

SETA

INB

INA

GND GND

COMMON

CIRCUITRY

ORENB

INT

0.1mF

VINT

ORENA

CTA

GND

GAT1B

OUTB

GAT2B

33nF

G1B

G2B

INB

GND

MONA

GND

MONB

INA

0.1mF R

G1ARG2A

SENSEB

SETB

SENPB

SETB

SENMB

INB

0.1mF

M1A

M2A

M1B

M2B

TPS2456

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Dual 12 V Protection / Blocking Controller

Check for Samples: TPS2456

FEATURES

• Dual 12 V Protection and Blocking Control

• Independent Current Limit and Fast Trip

• Blocking Permits ORing of Multiple Inputs

• Power Good and Fault Outputs

• Analog Current Monitor Outputs

• -40°C to 125°C Operating Junction Temperature

• QFN36 Package

APPLICATIONS

• ATCA Carrier Boards

• AdvancedMC™ Slots

• Blade Servers

• Base Stations

• Configurable for – 1 Source, 2 Loads – 2 Sources, 1 Load – 2 Sources, 2 Loads

SLVSA78A –MARCH 2010–REVISED MARCH 2010

DESCRIPTION

The TPS2456 is a dual, 12 V, channel protection (hotswap) and blocking (ORing) controller that provides inrush control, current limiting, overload protection, and reverse current blocking. The current sense topology provides both accurate current limits and independent setting of current limit and fast trip thresholds.

The ORing control uses an external MOSFET to block reverse current when an input is shorted. Systems with closely matched supply voltages and feed networks can supply current from both supplies simultaneously.

The MONx output provides an accurate analog indication of load current.

The protection circuits may be used without blocking, and the blocking may be used without protection. Internal connections prevent implementation of these as four fully-independent functions.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Figure 1. Two Sources, One Load Application Diagram

TPS2456

SLVSA78A –MARCH 2010–REVISED MARCH 2010

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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

PRODUCT INFORMATION

(1)

DEVICE TEMPERATURE PACKAGE MARKING

TPS2456RHH –40°C to 85°C QFN36 (6mm × 6mm) TPS2456

(1) For package and ordering information see the Package Option Addendum at the end of this document or see the TI Web site at

www.ti.com.

THERMAL INFORMATION

TPS2456

THERMAL METRIC

JC(top)

JC(bottom)

Junction-to-ambient thermal resistance Junction-to-case(top) thermal resistance Junction-to-board thermal resistance Junction-to-top characterization parameter Junction-to-board characterization parameter Junction-to-case(bottom) thermal resistance

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. (2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(3) The junction-to-case(top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard

test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(5) The junction-to-top characterization parameter, yJT, estimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining qJA, using a procedure described in JESD51-2a (sections 6 and 7).

(6) The junction-to-board characterization parameter, yJBestimates the junction temperature of a device in a real system and is extracted

from the simulation data for obtaining qJA, using a procedure described in JESD51-2a (sections 6 and 7).

(7) The junction-to-case(bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific

JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(1)

RHH UNITS

36 PINS

(2)

(3)

(4)

(5)

(6)

(7)

32 23 11

0.5 10

2.1

°C/W

ABSOLUTE MAXIMUM RATINGS

(1)

Over recommended junction temperature range and all voltages referenced to GND, unless otherwise noted.

PINS OR PIN GROUPS VALUE UNITS

GAT1x, GAT2x –0.3 to 30 V INx, OUTx, SENPx, SENMx, SETx, ENx, FLTx, PGx, ORENx –0.3 to 17 V CTx, MONx –0.3 to 5 V FLTx, PGx current sinking 5 mA MONx current sourcing 5 mA VINT current –1 to 1 mA

ESD

Junction Temperature Internally Limited °C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only. Functional operation of the device under any conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute maximum rated conditions for extended periods of time may affect device reliability.

Human Body Model 2 kV Charged Device Model 0.5 kV

Product Folder Link(s): TPS2456

TPS2456

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SLVSA78A –MARCH 2010–REVISED MARCH 2010

RECOMMENDED OPERATING CONDITIONS

Over recommended junction temperature range and all voltages referenced to GND, unless otherwise noted.

MIN TYP MAX UNIT

INx

MONx

GAT1x, GAT2x board leakage current

(1)

VINT bypass capacitance 1 100 250 nF Operating junction temperature range, T

(1) This condition applies to the PCB and is not a limit on the TPS2456.

8.5 12 15 V 100 1000 µA

–1 1 µA

–40 125 °C

ELECTRICAL CHARACTERISTICS

Common conditions (unless otherwise noted) are: INA = INB = SENPA = SENPB = SENMA = SENMB = SETPA = SETPB = 12 V, ENA = ENB = ORENA = ORENB = 3 V, CTA = CTB = GND, R –40°C ≤ TJ≤ 125°C

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Enable Input – ENx, ORENx

Threshold voltage V Hysteresis 20 50 80 mV Pullup current ENx = ORENx = 0 V, current sourcing 5 8 15 µA Input bias current ENx = ORENx = 17 V, current sinking 6 15 µA Turn off time

(1) (2)

Power Good Output – PGx

Output low voltage I Leakage current PGx = 17 V (sinking) 1 µA Threshold voltage PGx, V Hysteresis PGx, V Deglitch time PGx falling 50 100 150 µs

Fault Output – FLTx

Output low voltage I Leakage current V

Bias Supply – VINT

Output voltage 0 < I

Fault Timer – CTx

Sourcing current V Upper threshold voltage 1.30 1.35 1.40 V Discharge pulldown

(2)

Timer start threshold 5 6 7 V

Channel Current Monitor – MONx

Input referred offset –1.5 1.5 mV MONx threshold V

Leakage current V

(1) Tested with HAT2156 MOSFET. (2) These parameters are provided for reference only, and do not constitute part of TI's published device specifications for purposes of TI's

product warranty.

↑ 1.25 1.35 1.45 V

INx

ENx deasserts to V

= 2 mA sinking 0.14 0.25 V

PGx

↓ 10.2 10.5 10.8 V

OUTx

↑ 130

OUTx

= 2 mA sinking 0.14 0.25 V

FLTx

= 17 V (sinking) 1 µA

FLTx

< 50 µA 2 2.3 2.8 V

VINT

= 0 V, during fault 7 10 13 µA

CTx

– V

GAT1x

current

10.8 V ≤ V measure V

GAT1x SETx

) when timer starts, with V

INx

SENMx

– V

SETx

= 15 V 0.66 0.675 0.69 V

= (V

SENMx

< 1 V, C

OUTx

≤ 13.2 V, V

SENMx

SENPx

OUT

= V

= 0 µF, Q

GAT1x

+ 50 mV,

SENMx

– 10 mV) 1 µA

= R

MONA

= 33 nF 20 µs

GAT1x

= 6.81kΩ, all other pins open,

MONB

(2)

200 Ω

falling due to over

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90%

ENx

GAT1x

GAT2x

P50-90

time

50%

SENPx

SENMx

GAT1x

GAT2x

P50-50

time

50%

TPS2456

SLVSA78A –MARCH 2010–REVISED MARCH 2010

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ELECTRICAL CHARACTERISTICS (continued)

Common conditions (unless otherwise noted) are: INA = INB = SENPA = SENPB = SENMA = SENMB = SETPA = SETPB = 12 V, ENA = ENB = ORENA = ORENB = 3 V, CTA = CTB = GND, R –40°C ≤ TJ≤ 125°C

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Current limit

= 500 Ω, R

Current limit threshold 47.5 50 52.5 mV Sink current in current

limit Fast trip threshold Measure V Fast turn-off delay (V

SETx

GAT1x

MONx

SENP

= 15 V

= 1 V, V

SENPx

– V

SENM

Channel UVLO

UVLO V UVLO hysteresis V

↑ 8.1 8.5 8.9 V

INx

↓ 0.44 0.5 0.59 V

INx

Blocking Comparator

Turn-on threshold Measure (V Turn-off threshold Measure (V

SENPx SENPx

Turn-off delay 20 mV overdrive, t

Gate Drivers – GAT1x, GAT2x

Output voltage V Sourcing current V

Sinking current

= V

INx

= V

INx

Fast turnoff, V

= 10 V 21.5 23 24.5 V

OUTx

= 10 V, V

OUTx

GAT1x

Sustained, 4 V ≤ (V Pulldown resistance In thermal shutdown 14 20 26 kΩ Fast turn-off duration 5 10 15 µs Disable delay ENx pin to V

GATx1

Startup Time INx rising to GAT1x or GAT2x sourcing current (ENx and ORENx 0.25 ms

high)

Supply Current (I

INx

+ I

SENPx

+ I

SENMx

+ I

SETx

Both channels enabled 3.1 4 mA Both channels disabled 2 2.8 mA

Thermal Shutdown

Shutdown temperature TJrising 140 150 °C Hysteresis 10

(3) See Figure 3 for timing definition. (4) See Figure 2 for timing definition. (5) These parameters are provided for reference only, and do not constitute part of TI's published device specifications for purposes of TI's

product warranty.

= 6800 Ω, measure V

MONx

= 12 V, measure I

GAT1x

– V

SENMx

): 0 V → 120 mV, t

– V

) 5 10 20 mV

OUTx

– V

) –6 –3 0 mV

OUTx

p50-50

= V

GAT1x

+ I

= V

GAT1x

and V

OUTx

= 14 V, pulsed measurement 0.5 1 A

GAT2x

= V

GAT2x

, t

GAT2x

)

SENPx

GAT1x

(3)

P50-50

= 17 V 20 30 40 µA

GAT2x

) ≤ 25 V 10 14 20 mA

(4)

P50-90

MONA

– V

= R

SENMx

= 6.81kΩ, all other pins open,

MONB

when

20 40 µA 80 100 120 mV

200 300 ns

1 µs

(5)

°C

Figure 2. t

Definition Figure 3. t

P50-90

Product Folder Link(s): TPS2456

P50-50

Definition

100mV

675mV

Control & Fault

Vcp

30mA

enx

MONx

FLTx

PGx

prgx

blx

OUTx

GAT2x

GAT1x

SETx

SENMx

SENPx

100ms

INx

OUTx

10.50V /

10.63V

30mA

ENx

MONx

CTx

por

Charge

Pump

Vcp

~25V

60mA

ORENx

G1x

SETx

G2x

SENSEx

10 mV

3 mV

SQQ

OUTx

prgx

blx

200kW

VINT

enx

12V Channel

Input Supply

8.5V / 8V

INx

Fast

Trip

Current

Limit

FLT Tmr.

Gate Mon.

10ms

UVLO

Blocking

Control

Output

10ms

PREREG

VINT

2.2V Pwr On

Reset

en por

Control

Logic

GND

INA

INB

OUTA

OUTB

VINT

TPS2456

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FUNCTIONAL BLOCK DIAGRAM

SLVSA78A –MARCH 2010–REVISED MARCH 2010

Figure 4. TPS2456 Channel (2 channels per device)

Figure 5. Common Control Circuits

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TPS2456

SLVSA78A –MARCH 2010–REVISED MARCH 2010

PIN FUNCTIONS

NAME NO.

TYPE A/B

SENPA 1 I A Input voltage sense – connect to input supply. Connect to the source side of R SETA 2 I A SENMA 3 I A Connect this pin to the load side of the R

VINT 4 I/O – Connect a bypass capacitor (e.g., 0.01µF) to GND for this internal supply. MONA 5 I/O A ORENA 6 I A Blocking transistor enable, active high.

GND 7 GND – Connect pin to ground. GND 8 GND – Connect pin to ground

MONB 9 I/O B CTB 10 I/O B Connect CTBfrom CTB to GND to set the fault timer period (see text).

GAT2B 11 O B Blocking transistor gate drive. OUTB 12 I/O B Output voltage monitor and bias input. GND 13 GND B Connect pin to ground. ORENB 14 I B Blocking transistor enable, active high. GAT1B 15 O B Protection transistor gate drive. SENMB 16 I B Connect this pin to the load side of the R

SETB 17 I B SENPB 18 I B Input voltage sense – connect to input supply. Connect to the source side of R

INB 19 PWR B Control power input – connect to input supply. – 20 – – No connection. FLTB 21 O B Fault output, active low, asserted when B fault timer runs out. PGB 22 O B Power good output, active low, asserts when V GND 23 GND – Connect pin to ground. GND 24 GND – Connect pin to ground. GND 25 GND – Connect pin to ground. PGA 26 O A Power good output, active low, asserts when V FLTA 27 O A Fault output, active low, asserted when A fault timer runs out. GND 28 GND – Connect pin to ground. ENB 29 I B Enable, (active high). GAT1A 30 O A Protection transistor gate drive. ENA 31 I A Enable, (active high). GND 32 GND A Connect pin to ground. OUTA 33 I/O A Output voltage monitor and bias input. GAT2A 34 O A Blocking transistor gate drive. CTA 35 I/O A Connect CTAfrom CTA to GND to set the fault timer period (see text). INA 36 PWR A Control power input – connect to input supply. PAD – – – Solder pad to GND.

(1) Specifies whether this pin is part of A channel, B channel, or is common to both (-).

(1)

Connect R and R

MONA

Connect R text).

Connect R conjunction with R

DESCRIPTION

from the input supply to SETA to program the current limit in conjunction with R

SETA

(see text).

. The fast-trip threshold equals 100 mV / R

SENSEA

from MONA to GND to set the current limit in conjunction with R

MONA

from MONB to GND to set the current limit in conjunction with R

MONB

. The fast-trip threshold equals 100 mV / R

SENSEB

from input supply to SETB to program the current limit program the current limit in

SETB

SENSEB

and R

MONB

(see text).

OUTB

OUTA

> 10.63 V.

SENSEA

SENSEB

SENSEA

and R

SENSEB

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SENSEA

(see

SETA

(see

SETB

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TPS2456

36 3435 33 3132 30 2829

10 1211 13 1514 16 1817

SENPA

SETA

SENMA

VINT

MONA

ORENA

GND

MONB

FLTA

PGA

GND

PGB

FLTB

INB

INA

CTA

GAT2A

OUTA

GND

ENA

GAT1A

ENB

GNDSENPB

SETB

SENMB

GAT1B

ORENB

GND

OUTB

GAT2B

CTB

PAD - Backside

TPS2456

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SLVSA78A –MARCH 2010–REVISED MARCH 2010

DEVICE PINOUT

(TOP VIEW)

DETAILED PIN DESCRIPTIONS

The TPS2456 supports two 12-V protection (hotswap) and blocking (ORing) channels designated A and B. Where there are separate pins for both A and B channels, the pin name is shown with an x in place of A or B to describe the function. For example, references to CTx would be the same as CTA or CTB. Programming components are referred to in the text by reference designators used in Figure 1.

CTx – A capacitor from CTx to GND sets the period V channel down and declares a fault. V

will be low during startup and current limit. Low V

GAT1x

to source 10 µA into the external capacitor (CTx). When V by pulling the GAT1x and GAT2x pins low, declares a fault by pulling the FLTx pin low, and latching off. A 200 Ω internal pull down keeps this pin low during normal operation when not in current limit. It is normal to see a sawtooth on this pin when the channel is latched off by a fault.

ENx – Active high enable input. A low on ENx turns off the channel by pulling GAT1x and GAT2x low. An internal 200 kΩ resistor pulls this pin up to VINT. ENx may be left floating when the channel is to be permanently enabled.

FLTx – Active low open-drain output indicating that V the fault timer and shut the channel down. FLTx may be left open if not used.

GAT1x – Gate drive output for the protection MOSFET. This pin sources 30 µA to turn the MOSFET on. An internal clamp prevents this pin from rising more than 14.5 V above INx.

Up to 30µA may be sunk while current limit is active. A fast trip (overcurrent), disable (from ENx), or fault timeout enables a 10 µs, 1 A, discharge current and 14 mA pulldown. The pulldown will be released after 10 µs if only a fast trip had occurred.

Setting ENx low holds GAT1x low. GAT1x may be left open if not used.

Product Folder Link(s): TPS2456

can be low ( V

GAT1x

reaches 1.35 V, the TPS2456 shuts the channel off

CTx

has been low ( V

GAT1x

< V

+ 6 V) before it shuts the

INx

GAT1x

< V

+ 6 V) long enough trip

INx

causes this pin

TPS2456

SLVSA78A –MARCH 2010–REVISED MARCH 2010

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GAT2x – Gate drive output for the blocking MOSFET. The blocking MOSFET prevents reverse channel current

when OUTx is higher than INx. This is often used when two input sources are ORed together. GAT2x sources 30 µA to turn the MOSFET on. GAT2x is low when ENx is low, ORENx is low, FLTx is low, a fast trip is active, or a voltage reversal has occurred. A 10 µs, 1 A, discharge and 14 mA pulldown are applied when this occurs.

An internal clamp prevents this pin from rising more than 14.5 V above OUTx. Setting the ORENx or ENx pins low holds the GAT2x pin low.

GAT2x may be left open if not used.

INx - Supply pin for the internal circuitry. A small bypass capacitor (e.g. 0.1 µF) is recommended for this pin. MONx – A resistor connected from this pin to ground forms part of the current limit programming. As the current

delivered to the load increases, so does the voltage on this pin. The current-limit circuit controls GAT1x to limit channel current at a V

Equation 1 through Equation 4 define current limit and fast trip values using R

of 675 mV. The current limit circuit is inactive for lower values of V

MONx

, R

SENSEx

MONx

, and R

SETx

. V

MONx

can by sampled with an external A/D converter to measure the channel current. ORENx – Active high input. Pulling this pin low disables the blocking function by pulling the GAT2x pin low.

Pulling this pin high (or allowing it to float high) allows the blocking function to operate normally. The M2x internal diode may carry the load current when GAT2x is low and V

INX

> V

OUTX

An internal 200 kΩ resistor pulls this pin to VINT. ORENx may be left open when blocking is not used, or does not require active control.

OUTx – Senses the output voltage of the channel. This voltage is used by the biasing, blocking, and power good circuits.

PGx – Active low open-drain output. A low on PGx indicates that V

has exceeded 10.63 V, and has not

OUTx

fallen below 10.50 V. These thresholds are internally set, and modifying the OUTx connection may effect blocking operation.

SENMx – Senses the voltage on the load side of R

SENSEx

SENPx – Senses the voltage on the source side of R trip overcurrent shutdown is activated at a V

SENP-SENM

SETx – A resistor connected from this pin to SENPx sets the current limit level in conjunction with R R

as described in Equation 1 through Equation 4.

MONx

for use by the fast trip and current limiting circuits.

SENSEx

for use by the fast trip and blocking circuits. The fast

of 0.1 V.

SENSEx

and

VINT – This pin connects to the internal 2.35 V rail. A 0.1 µF capacitor must be connected from this pin to ground. VINT is not designed to be a general-purpose bias rail.

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2.1

2.2

2.3

2.4

-40 -20 0 20 40 60 80 100 120 T -JunctionTemperature-°C

SupplyCurrent-mA

2.1

2.15

2.2

2.25

2.3

2.35

2.4

2.45

10 10.5 11 11.5 12 12.5 13 13.5 14

V -InputVoltage-V

INx

T =25°C

SupplyCurrent-mA

-40 -20 0 20 40 60 80 100 120 T - Junction Temperature - °C

(V - V ) - mV

INx OUTx

-3.15

-3.05

-3.00

-2.95

-2.90

-2.85

-2.80

-3.10

50.2

50.4

50.6

50.8

-40 -20 0 20 40 60 80 100 120 T - Junction Temperature - °C

( ) - mVV - V

SENPx SENMx

R = 500

SETx

R = 6800

MONx

TPS2456

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SLVSA78A –MARCH 2010–REVISED MARCH 2010

TYPICAL CHARACTERISTICS

SUPPLY CURRENT vs TEMPERATURE SUPPLY CURRENT vs INPUT VOLTAGE

Figure 6. Figure 7.

CURRENT LIMIT THRESHOLD vs TEMPERATURE BLOCKING TURNOFF THRESHOLD vs TEMPERATURE

Figure 8. Figure 9.

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9.5

10.5

11.5

-40 -20 0 20 40 60 80 100 120 T -JunctionTemperature-°C

(V -V )-mV

INx OUTx

GAT1x,

10V/div

OUTxstartingupinto500 (24mA) Outputcapacitanceis830 FWm

675mV

MONx,

0.5V/div

OUTx,

10V/div

40mV

Time-1ms/div

OUTxstartingupinto1.8 (6.7 A,80W) Outputcapacitanceis830 FWm

675mV

580mV

Time-1ms/div

GAT1x, 10V/div

MONx,

0.5V/div

OUTx,

10V/div

TPS2456

SLVSA78A –MARCH 2010–REVISED MARCH 2010

TYPICAL CHARACTERISTICS (continued)

BLOCKING TURN ON THRESHOLD vs TEMPERATURE

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Figure 10.

Figure 11. Startup into 500 Ω, 830 µF Load Figure 12. Startup into 80 Watt, 830 µF Load

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+ 23 hidden pages

TEXAS INSTRUMENTS TPS2456 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

DESCRIPTION

THERMAL INFORMATION

ABSOLUTE MAXIMUM RATINGS

RECOMMENDED OPERATING CONDITIONS

ELECTRICAL CHARACTERISTICS

FUNCTIONAL BLOCK DIAGRAM

DETAILED PIN DESCRIPTIONS

TYPICAL CHARACTERISTICS