1
2
3
4
8
7
6
5
GND
IN
IN
EN
OUT
OUT
OUT
OC
TPS2051B
D PACKAGE
(TOP VIEW)
1
2
3
4
8
7
6
5
GND
IN
EN1
EN2
OC1
OUT1
OUT2
OC2
TPS2042B
D PACKAGE
(TOP VIEW)
1
2
3
5
4
IN
EN
OC
GNDGND
OUT
TPS2041B
DBV PACKAGE
(TOP VIEW)
www.ti.com
SLVS782B – NOVEMBER 2007–REVISED OCTOBER 2011
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
Check for Samples: TPS2041B-Q1, TPS2042B-Q1, TPS2051B-Q1
1
FEATURES
• Qualified for Automotive Applications • Heavy Capacitive Loads
• 70-mΩ High-Side MOSFET • Short-Circuit Protection
• 500-mA Continuous Current
• Thermal and Short-Circuit Protection
• Accurate Current Limit:
0.75 A (Min), 1.25 A (Max)
• Operating Range: 2.7 V to 5.5 V
• 0.6-ms Typical Rise Time
• Undervoltage Lockout
• Deglitched Fault Report (OC)
• No OC Glitch During Power Up
• Maximum Standby Supply Current:
1 μA (Single, Dual) or 2 μA (Triple, Quad)
• Bidirectional Switch
• Junction Temperature Range: –40°C to 125°C
• ESD Protection Level Per AEC-Q100
Classification
• UL Recognized, File Number E169910
APPLICATIONS
TPS2041B-Q1
TPS2042B-Q1
TPS2051B-Q1
DESCRIPTION
The TPS204xB/TPS205xB power-distribution switches are intended for applications where heavy capacitive
loads and short circuits are likely to be encountered. These devices incorporate 70-mΩ N-channel MOSFET
power switches for power-distribution systems that require multiple power switches in a single package. Each
switch is controlled by a logic enable input. Gate drive is provided by an internal charge pump designed to
control the power-switch rise times and fall times to minimize current surges during switching. The charge pump
requires no external components and allows operation from supplies as low as 2.7 V.
When the output load exceeds the current-limit threshold or a short is present, the device limits the output current
to a safe level by switching into a constant-current mode, pulling the overcurrent (OCx) logic output low. When
continuous heavy overloads and short circuits increase the power dissipation in the switch, causing the junction
temperature to rise, a thermal protection circuit shuts off the switch to prevent damage. Recovery from a thermal
shutdown is automatic once the device has cooled sufficiently. Internal circuitry ensures that the switch remains
off until valid input voltage is present. This power-distribution switch is designed to set current limit at 1 A (typ).
1
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007–2011, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TPS201xA
TPS202x
TPS203x
33 mΩ, single
0.2 A − 2 A
0.2 A − 2 A
0.2 A − 2 A
TPS2014
TPS2015
TPS2041B
TPS2051B
TPS2045
TPS2055
TPS2061
TPS2065
80 mΩ, single
600 mA
1 A
500 mA
500 mA
250 mA
250 mA
1 A
1 A
GENERAL SWITCH CATALOG
TPS2042B
TPS2052B
TPS2046
TPS2056
TPS2062
TPS2066
TPS2060
TPS2064
80 mΩ, dual
500 mA
500 mA
250 mA
250 mA
1 A
1 A
1.5 A
1.5 A
TPS2100/1
260 mΩ
IN1 500 mA
IN2 10 mA
OUT
IN1
IN2
TPS2102/3/4/5
IN1 500 mA
IN2 100 mA
1.3 Ω
TPS2043B
TPS2053B
TPS2047
TPS2057
80 mΩ, triple
500 mA
500 mA
250 mA
250 mA
TPS2044B
TPS2054B
TPS2048
TPS2058
80 mΩ, quad
500 mA
500 mA
250 mA
250 mA
80 mΩ, dual
TPS2080
TPS2081
TPS2082
TPS2090
500 mA
500 mA
500 mA
250 mA
TPS2091
TPS2092
250 mA
250 mA
80 mΩ, quad
TPS2085
TPS2086
TPS2087
TPS2095
500 mA
500 mA
500 mA
250 mA
TPS2096
TPS2097
250 mA
250 mA
TPS2041B-Q1
TPS2042B-Q1
TPS2051B-Q1
SLVS782B – NOVEMBER 2007–REVISED OCTOBER 2011
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
www.ti.com
ORDERING INFORMATION
T
J
ENABLE PACKAGE
NO. OF ORDERABLE TOP-SIDE
SWITCHES PART NUMBER MARKING
(1)
(2)
Active high Single SOIC – D Reel of 2500 TPS2051BQDRQ1 2051BQ
–40°C to 125°C Single SOT-23 – DBV Reel of 3000 TPS2041BQDBVRQ1 PLIQ
Active low
Dual SOIC – D Reel of 2500 TPS2042BQDRQ1 2042B
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
2 Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated
Product Folder Link(s): TPS2041B-Q1 TPS2042B-Q1 TPS2051B-Q1
TPS2041B-Q1
TPS2042B-Q1
TPS2051B-Q1
www.ti.com
ABSOLUTE MAXIMUM RATINGS
(1)
over operating free-air temperature range unless otherwise noted
V
I(IN)
V
O(OUT)
V
O(OUTx)
V
I(
ENx
Input voltage range (IN)
,
Output voltage range (OUT, OUTx)
Input voltage range (ENx, EN) –0.3 V to 6 V
,
V
I(EN)
V
I(
OC
, Voltage range (OC, OCx) –0.3 V to 6 V
V
I(
OCx
I
,
O(OUT)
I
O(OUTx)
Continuous output current Internally limited
Continuous total power dissipation See Dissipation Ratings
T
J
T
stg
Operating virtual-junction temperature range –40°C to 125°C
Storage temperature range –65°C to 150°C
Lead temperature, soldering 1,6 mm (1/16 in) from case for 10 s 260°C
Electrostatic discharge (ESD)
protection
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to GND.
(2)
(2)
)
)
)
Human-Body Model (HBM) (H2) 2500 V
TPS2041B Machine Model (MM) (M0) 50 V
Charged-Device Model (CDM) (C5) 1500 V
Human-Body Model (HBM) (H2) 2500 V
TPS2042B Machine Model (MM) (M0) 50 V
Charged-Device Model (CDM) (C5) 1500 V
Human-Body Model (HBM) (H2) 2000 V
TPS2051B Machine Model (MM) (M0) 50 V
Charged-Device Model (CDM) (C5) 1500 V
SLVS782B – NOVEMBER 2007–REVISED OCTOBER 2011
–0.3 V to 6 V
–0.3 V to 6 V
DISSIPATING RATINGS
PACKAGE
D-8 585.82 mW 5.8582 mW/°C 322.20 mW 234.32 mW
DBV-5 285 mW 2.85 mW/°C 155 mW 114 mW
TA≤ 25°C DERATING FACTOR TA= 70°C TA= 85°C
POWER RATING ABOVE TA= 25°C POWER RATING POWER RATING
RECOMMENDED OPERATING CONDITIONS
MIN MAX UNIT
V
I(IN)
V
I(
ENx
, V
I
O(OUT)
I
O(OUTx)
T
J
Copyright © 2007–2011, Texas Instruments Incorporated Submit Documentation Feedback 3
Input voltage (IN) 2.7 5.5 V
Input voltage (ENx, EN) 0 5.5 V
I(EN)
,
Continuous output current (OUT, OUTx) 0 500 mA
)
Operating virtual-junction temperature –40 125 °C
Product Folder Link(s): TPS2041B-Q1 TPS2042B-Q1 TPS2051B-Q1
TPS2041B-Q1
TPS2042B-Q1
TPS2051B-Q1
SLVS782B – NOVEMBER 2007–REVISED OCTOBER 2011
ELECTRICAL CHARACTERISTICS
over recommended operating junction temperature range, V
PARAMETER TEST CONDITIONS
Power Switch
Static drain-source on-state
resistance, 5-V or 3.3-V V
r
t
t
operation
DS(on)
Static drain-source on-state
resistance, 2.7-V operation
Rise time, output
r
Fall time, output
f
(2)
(2)
(2)
Enable Input (EN, ENx )
V
V
I
t
t
High-level input voltage 2.7 V ≤ V
IH
Low-level input voltage 2.7 V ≤ V
IL
Input current V
I
on
off
Turn-on time
Turn-off time
(2)
(2)
Current Limit
I
Short-circuit output current A
OS
Supply Current (TPS2041B/TPS2051B)
Supply current, low-level output μA
Supply current, high-level output μA
Leakage current –40°C ≤ TJ≤ 125°C 1 μA
Reverse leakage current V
Supply Current (TPS2042B)
Supply current, low-level output μA
Supply current, high-level output μA
Leakage current –40°C ≤ TJ≤ 125°C 1 μA
Reverse leakage current V
Undervoltage Lockout
Low-level input voltage, IN, INx 2 2.5 V
Hysteresis, IN, INx TJ= 25°C 75 mV
Overcurrent (OC,
OCx )
Output low voltage, V
Off-state current
OC deglitch
(2)
OL(/OCx)
(2)
= 5 V or 3.3 V, IO= 0.5 A –40°C ≤ TJ≤ 125°C 70 135
I(IN)
V
= 2.7 V, IO= 0.5 A –40°C ≤ TJ≤ 125°C 75 150
I(IN)
V
= 5.5 V 0.6 1.5
I(IN)
V
= 2.7 V 0.4 1
I(IN)
V
= 5.5 V 0.05 0.5
I(IN)
V
= 2.7 V 0.05 0.5
I(IN)
≤ 5.5 V 2 V
I(IN)
≤ 5.5 V 0.8 V
I(IN)
I( ENx )
CL= 100 μF, RL= 10 Ω 3 ms
CL= 100 μF, RL= 10 Ω 10 ms
V
= 5 V, OUT connected to GND,
I(IN)
device enabled into short-circuit
No load on OUT,
V
= 5.5 V or V
I(EN)
I(EN)
No load on OUT,
V
= 0 V or V
I(EN)
I(EN)
OUT connected to ground,
V
= 5.5 V or V
I(EN)
= 5.5 V, IN = ground
I(OUTx)
No load on OUT, V
ENx
I(EN)
I(
= 5.5 V
No load on OUT, V
ENx
I(
= 0 V
OUT connected to ground, V
ENx
= 5.5 V
= 5.5 V, IN = ground
I(OUTx)
I
O( OCx )
V
O( OCx )
OCx assertion or deassertion 4 8 15 ms
= 5.5 V, IO= 0.5 A, V
I(IN)
CL= 1 μF,
RL= 10 Ω
= 0 V
= 5.5 V
= 0 V
(2)
I(
(2)
= 0 V (unless otherwise noted)
I(ENx)
(1)
MIN TYP MAX UNIT
TJ= 25°C ms
= 0 V or 5.5 V –0.5 0.5 μA
TJ= 25°C 0.65 1 1.25
–40°C ≤ TJ≤ 125°C 0.6 1 1.3
TJ= 25°C 0.5 1
–40°C ≤ TJ≤ 125°C 0.5 5
TJ= 25°C 43 60
–40°C ≤ TJ≤ 125°C 43 70
TJ= 25°C 0 μA
TJ= 25°C 0.5 1
)
–40°C ≤ TJ≤ 125°C 0.5 5
TJ= 25°C 50 70
)
–40°C ≤ TJ≤ 125°C 50 90
)
TJ= 25°C 0.2 μA
= 5 mA 0.4 V
= 5 V or 3.3 V 1 μA
www.ti.com
mΩ
(1) Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be accounted for separately.
(2) Specified by design
4 Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated
Product Folder Link(s): TPS2041B-Q1 TPS2042B-Q1 TPS2051B-Q1
OUT
OC
IN
EN
GND
Current
Limit
Driver
UVLO
Charge
Pump
CS
Thermal
Sense
Deglitch
(See Note A)
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
over recommended operating junction temperature range, V
PARAMETER TEST CONDITIONS
Thermal Shutdown
Thermal shutdown threshold
Recovery from thermal shutdown
Hysteresis
(3) The thermal shutdown only reacts under overcurrent conditions.
(2)
(3)
(2)
(2)
= 5.5 V, IO= 0.5 A, V
I(IN)
DEVICE INFORMATION
Terminal Functions (TPS2041B)
TERMINAL
NAME NO.
EN 4 I Enable input, logic low turns on power switch
GND 2 Ground
IN 5 I Input voltage
OC 3 O Overcurrent, open-drain output, active low
OUT 1 O Power-switch output
I/O DESCRIPTION
TPS2041B-Q1
TPS2042B-Q1
TPS2051B-Q1
SLVS782B – NOVEMBER 2007–REVISED OCTOBER 2011
= 0 V (unless otherwise noted)
I(ENx)
(1)
MIN TYP MAX UNIT
135 °C
125 °C
10 °C
Functional Block Diagram (TPS2041B)
A. CS = Current sense
Copyright © 2007–2011, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): TPS2041B-Q1 TPS2042B-Q1 TPS2051B-Q1
Thermal
Sense
Driver
Current
Limit
Charge
Pump
UVLO
CS
Driver
Current
Limit
CS
Thermal
Sense
Charge
Pump
GND
EN1
IN
EN2
OC1
OUT1
OUT2
OC2
Deglitch
Deglitch
(See Note A)
(See Note A)
TPS2041B-Q1
TPS2042B-Q1
TPS2051B-Q1
SLVS782B – NOVEMBER 2007–REVISED OCTOBER 2011
Terminal Functions (TPS2042B)
TERMINAL
NAME NO.
EN1 3 I Enable input, logic low turns on power switch IN-OUT1
EN2 4 I Enable input, logic low turns on power switch IN-OUT2
GND 1 Ground
IN 2 I Input voltage
OC1 8 O Overcurrent, open-drain output, active low, IN-OUT1
OC2 5 O Overcurrent, open-drain output, active low, IN-OUT2
OUT1 7 O Power-switch output, IN-OUT1
OUT2 6 O Power-switch output, IN-OUT2
I/O DESCRIPTION
Functional Block Diagram (TPS2042B)
www.ti.com
A. CS = Current sense
6 Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated
Product Folder Link(s): TPS2041B-Q1 TPS2042B-Q1 TPS2051B-Q1
OUT
OC
IN
EN
GND
Current
Limit
Driver
UVLO
Charge
Pump
CS
Thermal
Sense
Deglitch
(See Note A)
www.ti.com
Terminal Functions (TPS2051B)
TERMINAL
NAME NO.
EN 4 I Enable input, logic high turns on power switch
GND 1 Ground
IN 2, 3 I Input voltage
OC 5 O Overcurrent open-drain output, active low
OUT 6, 7, 8 O Power-switch output
I/O DESCRIPTION
Functional Block Diagram (TPS2051B)
TPS2041B-Q1
TPS2042B-Q1
TPS2051B-Q1
SLVS782B – NOVEMBER 2007–REVISED OCTOBER 2011
A. CS = Current sense
Copyright © 2007–2011, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): TPS2041B-Q1 TPS2042B-Q1 TPS2051B-Q1
R
L
C
L
OUT
t
r
t
f
90%
90%
10%
10%
50%
50%
90%
10%
V
O(OUT)
V
I(EN)
V
O(OUT)
VOLTAGE WAVEFORMS
TEST CIRCUIT
t
on
t
off
50%
50%
90%
10%
V
I(EN)
V
O(OUT)
t
on
t
off
V
I(EN
)
V
I(EN)
5 V/div
V
O(OUT)
2 V/div
RL = 10 W,
CL = 1 mF
TA = 255C
t − Time − 500 ms/div
V
I(EN
)
V
I(EN)
5 V/div
V
O(OUT)
2 V/div
RL = 10 W,
CL = 1 mF
TA = 255C
t − Time − 500 ms/div
TPS2041B-Q1
TPS2042B-Q1
TPS2051B-Q1
SLVS782B – NOVEMBER 2007–REVISED OCTOBER 2011
PARAMETER MEASUREMENT INFORMATION
Figure 1. Test Circuit and Voltage Waveforms
www.ti.com
Figure 2. Turn-On Delay and Rise Time With 1-μF Figure 3. Turn-Off Delay and Fall Time With 1-μF
Load Load
Product Folder Link(s): TPS2041B-Q1 TPS2042B-Q1 TPS2051B-Q1
8 Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated
V
I(EN
)
V
I(EN)
5 V/div
V
O(OUT)
2 V/div
RL = 10 W,
CL = 100 mF
TA = 255C
t − Time − 500 ms/div
V
O(OUT)
2 V/div
V
I(EN
)
V
I(EN)
5 V/div
RL = 10 W,
CL = 100 mF
TA = 255C
t − Time − 500 ms/div
220 mF
470 mF
100 mF
VI = 5 V ,
RL = 10 W,
TA = 255C
V
I(EN
)
V
I(EN)
5 V/div
I
O(OUT)
500 mA/div
t − Time − 500 ms/div
V
I(EN
)
V
I(EN)
5 V/div
I
O(OUT)
500 mA/div
t − Time − 500 ms/div
TPS2041B-Q1
TPS2042B-Q1
TPS2051B-Q1
www.ti.com
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 4. Turn-On Delay and Rise Time With Figure 5. Turn-Off Delay and Fall Time With 100-μF
100-μF Load Load
SLVS782B – NOVEMBER 2007–REVISED OCTOBER 2011
Figure 6. Short-Circuit Current, Figure 7. Inrush Current With Different
Device Enabled Into Short Load Capacitance
Copyright © 2007–2011, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Link(s): TPS2041B-Q1 TPS2042B-Q1 TPS2051B-Q1
V
O(OC
)
2 V/div
I
O(OUT)
500 mA/div
t − Time − 2 ms/div
V
O(OC
)
2 V/div
I
O(OUT)
500 mA/div
t − Time − 2 ms/div
TPS2041B-Q1
TPS2042B-Q1
TPS2051B-Q1
SLVS782B – NOVEMBER 2007–REVISED OCTOBER 2011
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 8. 3-Ω Load Connected to Enabled Device Figure 9. 2-Ω Load Connected to Enabled Device
www.ti.com
10 Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated
Product Folder Link(s): TPS2041B-Q1 TPS2042B-Q1 TPS2051B-Q1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
2 3 4 5 6
Turnon Time − ms
VI − Input Voltage − V
CL = 100 mF,
RL = 10 W,
TA = 255C
2.8
2.9
3
3.1
3.2
3.3
2 3 4 5 6
Turnoff Time − ms
VI − Input Voltage − V
CL = 100 mF,
RL = 10 W,
TA = 255C
0
0.1
0.2
0.3
0.4
0.5
0.6
2 3 4 5 6
Rise Time − ms
VI − Input Voltage − V
CL = 1 mF,
RL = 10 W,
TA = 255C
0
0.05
0.1
0.15
0.2
0.25
2 3 4 5 6
CL = 1 mF,
RL = 10 W,
TA = 255C
Fall Time − ms
VI − Input Voltage − V
www.ti.com
TPS2041B-Q1
TPS2042B-Q1
TPS2051B-Q1
SLVS782B – NOVEMBER 2007–REVISED OCTOBER 2011
TYPICAL CHARACTERISTICS
TURN-ON TIME TURN-OFF TIME
vs vs
INPUT VOLTAGE INPUT VOLTAGE
Figure 10. Figure 11.
RISE TIME FALL TIME
vs vs
INPUT VOLTAGE INPUT VOLTAGE
Figure 12. Figure 13.
Copyright © 2007–2011, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Link(s): TPS2041B-Q1 TPS2042B-Q1 TPS2051B-Q1
0
10
20
30
40
50
60
−50 0 50 100 150
VI = 5.5 V
VI = 3.3 V
VI = 2.7 V
TJ − Junction Temperature − 5C
− Supply Current, Output Enabled −
I
I (IN)
Aµ
VI = 5 V
0
10
20
30
40
50
60
70
−50 0 50 100 150
VI = 5.5 V
VI = 5 V
VI = 3.3 V
VI = 2.7 V
TJ − Junction Temperature − 5C
− Supply Current, Output Enabled −
I
I (IN)
Aµ
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
−50 0 50 100 150
VI = 5.5 V
VI = 5 V
VI = 3.3 V
VI = 2.7 V
TJ − Junction Temperature − 5C
− Supply Current, Output Disabled −
I
I (IN)
Aµ
TJ − Junction Temperature − 5C
− Supply Current, Output Disabled −I
I (IN)
Aµ
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
−50 0 50 100 150
VI = 2.7 V
VI = 3.3 V
VI = 5.5 V
VI = 5 V
TPS2041B-Q1
TPS2042B-Q1
TPS2051B-Q1
SLVS782B – NOVEMBER 2007–REVISED OCTOBER 2011
TYPICAL CHARACTERISTICS (continued)
TPS2041B/TPS2051B TPS2042B
SUPPLY CURRENT, OUTPUT ENABLED SUPPLY CURRENT, OUTPUT ENABLED
vs vs
JUNCTION TEMPERATURE JUNCTION TEMPERATURE
www.ti.com
Figure 14. Figure 15.
TPS2041B/TPS2051B TPS2042B
SUPPLY CURRENT, OUTPUT DISABLED SUPPLY CURRENT, OUTPUT DISABLED
JUNCTION TEMPERATURE JUNCTION TEMPERATURE
12 Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated
Figure 16. Figure 17.
vs vs
Product Folder Link(s): TPS2041B-Q1 TPS2042B-Q1 TPS2051B-Q1
0.9
0.92
0.94
0.96
0.98
1.0
1.02
1.04
1.06
1.08
−50 0 50 100 150
VI = 5 V
VI = 3.3 V
VI = 5.5 V
TJ − Junction Temperature − 5C
VI = 2.7 V
− Short-Circuit Output Current − A
I
OS
0
20
40
60
80
100
120
−50 0 50 100 150
VI = 5 V
VI = 3.3 V
TJ − Junction Temperature − 5C
r
DS(on) − Static Drain-Source On-State Resistance − m
Ω
VI = 2.7 V
IO = 0.5 A
Threshold Trip Current − A
VI − Input Voltage − V
1
1.2
1.4
1.6
1.8
2
2.5 3 3.5 4 4.5 5 5.5 6
TA = 255C
Load Ramp = 1 A/10 ms
2.1
2.14
2.18
2.22
2.26
2.3
−50 0 50 100 150
UVLO Rising
UVLO Falling
UVLO − Undervoltage Lockout − V
TJ − Junction Temperature − 5C
www.ti.com
TPS2041B-Q1
TPS2042B-Q1
TPS2051B-Q1
SLVS782B – NOVEMBER 2007–REVISED OCTOBER 2011
TYPICAL CHARACTERISTICS (continued)
STATIC DRAIN-SOURCE ON-STATE RESISTANCE SHORT-CIRCUIT OUTPUT CURRENT
vs vs
JUNCTION TEMPERATURE JUNCTION TEMPERATURE
Figure 18. Figure 19.
THRESHOLD TRIP CURRENT UNDERVOLTAGE LOCKOUT
vs vs
INPUT VOLTAGE JUNCTION TEMPERATURE
Figure 20. Figure 21.
Copyright © 2007–2011, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): TPS2041B-Q1 TPS2042B-Q1 TPS2051B-Q1
0
20
40
60
80
100
0 2.5 5 7.5 10 12.5
Peak Current − A
VI = 5 V ,
TA = 255C
Current-Limit Response − sµ
TPS2041B-Q1
TPS2042B-Q1
TPS2051B-Q1
SLVS782B – NOVEMBER 2007–REVISED OCTOBER 2011
TYPICAL CHARACTERISTICS (continued)
www.ti.com
CURRENT-LIMIT RESPONSE
vs
PEAK CURRENT
Figure 22.
14 Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated
Product Folder Link(s): TPS2041B-Q1 TPS2042B-Q1 TPS2051B-Q1
IN
OC1
EN1
OC2
2
8
5
7
0.1 µF 22 µF
0.1 µF 22 µF
Load
Load
OUT1
OUT2
Power Supply
2.7 V to 5.5 V
6
EN2
3
4
GND
0.1 µF
TPS2042B
1
www.ti.com
Power-Supply Considerations
Figure 23. Typical Application (Example, TPS2042B)
TPS2041B-Q1
TPS2042B-Q1
TPS2051B-Q1
SLVS782B – NOVEMBER 2007–REVISED OCTOBER 2011
APPLICATION INFORMATION
A 0.01-μF to 0.1-μF ceramic bypass capacitor between IN and GND, close to the device, is recommended.
Placing a high-value electrolytic capacitor on the output pin(s) is recommended when the output load is heavy.
This precaution reduces power-supply transients that may cause ringing on the input. Additionally, bypassing the
output with a 0.01-μF to 0.1-μF ceramic capacitor improves the immunity of the device to short-circuit transients.
Overcurrent
A sense FET is employed to check for overcurrent conditions. Unlike current-sense resistors, sense FETs do not
increase the series resistance of the current path. When an overcurrent condition is detected, the device
maintains a constant output current and reduces the output voltage accordingly. Complete shutdown occurs only
if the fault is present long enough to activate thermal limiting.
Three possible overload conditions can occur. In the first condition, the output has been shorted before the
device is enabled or before V
has been applied (see Figure 14 and Figure 15). The TPS204xB/TPS205xB
I(IN)
senses the short and immediately switches into a constant-current output.
In the second condition, a short or an overload occurs while the device is enabled. At the instant the overload
occurs, high currents may flow for a short period of time before the current-limit circuit can react. After the
current-limit circuit has tripped (reached the overcurrent trip threshold), the device switches into constant-current
mode.
In the third condition, the load has been gradually increased beyond the recommended operating current. The
current is permitted to rise until the current-limit threshold is reached or until the thermal limit of the device is
exceeded (see Figure 16 and Figure 17). The TPS204xB/TPS205xB is capable of delivering current up to the
current-limit threshold without damaging the device. Once the threshold has been reached, the device switches
into its constant-current mode.
OC Response
The OCx open-drain output is asserted (active low) when an overcurrent or overtemperature shutdown condition
is encountered after a 10-ms deglitch timeout. The output remains asserted until the overcurrent or
overtemperature condition is removed. Connecting a heavy capacitive load to an enabled device can cause a
momentary overcurrent condition; however, no false reporting on OCx occurs due to the 10-ms deglitch circuit.
The TPS204xB/TPS205xB is designed to eliminate false overcurrent reporting. The internal overcurrent deglitch
eliminates the need for external components to remove unwanted pulses. OCx is not deglitched when the switch
is turned off due to an overtemperature shutdown.
Copyright © 2007–2011, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): TPS2041B-Q1 TPS2042B-Q1 TPS2051B-Q1
GND
IN
EN1
EN2
OC1
OC2
OUT1
OUT2
TPS2042B
R
pullup
V+
TPS2041B-Q1
TPS2042B-Q1
TPS2051B-Q1
SLVS782B – NOVEMBER 2007–REVISED OCTOBER 2011
Figure 24. Typical Circuit for the OC Pin (Example, TPS2042B)
Power Dissipation and Junction Temperature
The low on-resistance on the N-channel MOSFET allows the small surface-mount packages to pass large
currents. The thermal resistances of these packages are high compared to those of power packages; it is good
design practice to check power dissipation and junction temperature. Begin by determining the r
N-channel MOSFET relative to the input voltage and operating temperature. As an initial estimate, use the
highest operating ambient temperature of interest and read r
dissipation per switch can be calculated by:
PD= r
DS(on)
× I
2
Multiply this number by the number of switches being used. This step renders the total power dissipation from
the N-channel MOSFETs.
Finally, calculate the junction temperature:
TJ= PD× R
θJA
+ T
A
Where:
TA= Ambient temperature (°C)
R
= Thermal resistance
θJA
PD= Total power dissipation based on number of switches being used.
Compare the calculated junction temperature with the initial estimate. If they do not agree within a few degrees,
repeat the calculation, using the calculated value as the new estimate. Two or three iterations are generally
sufficient to get a reasonable answer.
from Figure 18. Using this value, the power
DS(on)
www.ti.com
DS(on)
of the
Thermal Protection
Thermal protection prevents damage to the IC when heavy-overload or short-circuit faults are present for
extended periods of time. The TPS204xB/TPS205xB implements a thermal sensing to monitor the operating
junction temperature of the power distribution switch. In an overcurrent or short-circuit condition, the junction
temperature rises due to excessive power dissipation. Once the die temperature rises to approximately 140°C
due to overcurrent conditions, the internal thermal sense circuitry turns the power switch off, thus preventing the
power switch from damage. Hysteresis is built into the thermal sense circuit, and after the device has cooled
approximately 10°C, the switch turns back on. The switch continues to cycle in this manner until the load fault or
input power is removed. The OCx open-drain output is asserted (active low) when an overtemperature shutdown
or overcurrent occurs.
Undervoltage Lockout (UVLO)
The UVLO ensures that the power switch is in the off state at power up. Whenever the input voltage falls below
approximately 2 V, the power switch is quickly turned off. This facilitates the design of hot-insertion systems
where it is not possible to turn off the power switch before input power is removed. The UVLO also keeps the
switch from being turned on until the power supply has reached at least 2 V, even if the switch is enabled. On
reinsertion, the power switch is turned on, with a controlled rise time to reduce EMI and voltage overshoots.
16 Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated
Product Folder Link(s): TPS2041B-Q1 TPS2042B-Q1 TPS2051B-Q1
IN
OC
EN
GND
0.1 µF
2, 3
5
4
6, 7, 8
0.1 µF 120 µF
GND
OUT
TPS2051B
Power Supply
D+
D-
V
BUS
Downstream
USB Ports
USB
Control
3.3 V 5 V
1
TPS2041B-Q1
TPS2042B-Q1
TPS2051B-Q1
www.ti.com
Universal Serial Bus (USB) Applications
The universal serial bus (USB) interface is a 12-Mb/s, or 1.5-Mb/s, multiplexed serial bus designed for
low-to-medium bandwidth PC peripherals (e.g., keyboards, printers, scanners, and mice). The four-wire USB
interface is conceived for dynamic attach-detach (hot plug-unplug) of peripherals. Two lines are provided for
differential data, and two lines are provided for 5-V power distribution.
USB data is a 3.3-V level signal, but power is distributed at 5 V to allow for voltage drops in cases where power
is distributed through more than one hub across long cables. Each function must provide its own regulated 3.3 V
from the 5-V input or its own internal power supply.
The USB specification defines the following five classes of devices, each differentiated by power-consumption
requirements:
• Hosts/self-powered hubs (SPHs)
• Bus-powered hubs (BPHs)
• Low-power bus-powered functions
• High-power bus-powered functions
• Self-powered functions
Self-powered and bus-powered hubs distribute data and power to downstream functions. The
TPS204xB/TPS205xB can provide power-distribution solutions to many of these classes of devices.
SLVS782B – NOVEMBER 2007–REVISED OCTOBER 2011
Hosts/Self-Powered Hubs and Bus-Powered Hubs
Hosts and self-powered hubs have a local power supply that powers the embedded functions and the
downstream ports (see Figure 25). This power supply must provide from 5.25 V to 4.75 V to the board side of the
downstream connection under full-load and no-load conditions. Hosts and SPHs are required to have
current-limit protection and must report overcurrent conditions to the USB controller. Typical SPHs are desktop
PCs, monitors, printers, and stand-alone hubs.
Figure 25. Typical One-Port USB Host/Self-Powered Hub
Bus-powered hubs obtain all power from upstream ports and often contain an embedded function. The hubs are
required to power up with less than one unit load. The BPH usually has one embedded function, and power is
always available to the controller of the hub. If the embedded function and hub require more than 100 mA on
power up, the power to the embedded function may need to be kept off until enumeration is completed. This can
be accomplished by removing power or by shutting off the clock to the embedded function. Power switching the
embedded function is not necessary if the aggregate power draw for the function and controller is less than one
unit load. The total current drawn by the bus-powered device is the sum of the current to the controller, the
embedded function, and the downstream ports, and it is limited to 500 mA from an upstream port.
Copyright © 2007–2011, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): TPS2041B-Q1 TPS2042B-Q1 TPS2051B-Q1
IN
OC1
OC2
2
8
3
5
4
7
0.1 µF 10 µF
Internal
Function
OUT1
Power Supply
3.3 V
EN1
6
0.1 µF 10 µF
OUT2
Internal
Function
0.1 µF
10 µF
USB
Control
GND
V
BUS
D−
D+
EN2
GND
1
TPS2042B
TPS2041B-Q1
TPS2042B-Q1
TPS2051B-Q1
SLVS782B – NOVEMBER 2007–REVISED OCTOBER 2011
Low-Power and High-Power Bus-Powered Functions
Both low-power and high-power bus-powered functions obtain all power from upstream ports; low-power
functions always draw less than 100 mA; high-power functions must draw less than 100 mA at power up and can
draw up to 500 mA after enumeration. If the load of the function is more than the parallel combination of 44 Ω
and 10 μF at power up, the device must implement inrush current limiting (see Figure 26).
www.ti.com
Figure 26. High-Power Bus-Powered Function (Example, TPS2042B)
USB Power-Distribution Requirements
USB can be implemented in several ways, and, regardless of the type of USB device being developed, several
power-distribution features must be implemented.
• Hosts/self-powered hubs must:
– Current-limit downstream ports
– Report overcurrent conditions on USB V
• Bus-powered hubs must:
– Enable/disable power to downstream ports
– Power up at <100 mA
– Limit inrush current (<44 Ω and 10 μF)
• Functions must:
– Limit inrush currents
– Power up at <100 mA
The feature set of the TPS204xB/TPS205xB allows them to meet each of these requirements. The integrated
current-limiting and overcurrent reporting is required by hosts and self-powered hubs. The logic-level enable and
controlled rise times meet the need of both input and output ports on bus-powered hubs, as well as the input
ports for bus-powered functions (see Figure 27 and Figure 28).
BUS
18 Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated
Product Folder Link(s): TPS2041B-Q1 TPS2042B-Q1 TPS2051B-Q1
DP1
DM1
DP2
DM2
DP3
DM3
DP4
PWRON1
OVRCUR1
PWRON2
OVRCUR2
PWRON3
OVRCUR3
PWRON4
OVRCUR4
DM4
DP0
DM0
V
CC
XTAL1
XTAL2
OCSOFF
SN75240
D +
D -
5 V
GND
D +
D -
5 V
D +
D -
5 V
D +
D -
5 V
48-MHz
Crystal
Downstream
Ports
TUSB2046
Hub Controller
Tuning
Circuit
ABC
D
33 µF
(see Note A)
SN75240
ABC
D
GND
GND
GND
D +
D -
Upstream
Port
TPS2051B
SN75240
A
B
5 V
GND
C
D
1 µF
IN
GND
Ferrite Beads
Ferrite Beads
Ferrite Beads
Ferrite Beads
BUSPWR
GANGED
Tie to TPS2051B EN Input
OC EN
OUT
5-V Power
Supply
IN
GND
3.3 V
4.7 µF
0.1 µF
4.7 µF
GND
EN
OC
IN
TPS2051B
OUT
EN
OC
IN
TPS2051B
OUT
EN
OC
IN
TPS2051B
OUT
EN
OC
IN
TPS2051B
OUT
TPS76333
0.1 µF
33 µF
(see Note A)
33 µF
(see Note A)
33 µF
(see Note A)
0.1 µF
0.1 µF
0.1 µF
www.ti.com
TPS2041B-Q1
TPS2042B-Q1
TPS2051B-Q1
SLVS782B – NOVEMBER 2007–REVISED OCTOBER 2011
Copyright © 2007–2011, Texas Instruments Incorporated Submit Documentation Feedback 19
A. USB rev 1.1 requires 120 μF per hub.
Figure 27. Hybrid Self-Powered/Bus-Powered Hub Implementation (TPS2051B)
Product Folder Link(s): TPS2041B-Q1 TPS2042B-Q1 TPS2051B-Q1
DP1
DM1
DP2
DM2
DP3
DM3
DP4
PWRON1
OVRCUR1
PWRON2
OVRCUR2
DM4
DP0
DM0
V
CC
XTAL1
XTAL2
OCSOFF
SN75240
D +
D -
5 V
GND
D +
D -
5 V
D +
D -
5 V
D +
D -
5 V
48-MHz
Crystal
Downstream
Ports
TUSB2046
Hub Controller
Tuning
Circuit
ABC
D
SN75240
ABC
D
GND
GND
GND
D +
D -
Upstream
Port
TPS2051B
SN75240
A
B
5 V
GND
C
D
IN
GND
Ferrite Beads
Ferrite Beads
Ferrite Beads
Ferrite Beads
BUSPWR
GANGED
Tie to TPS2051B EN Input
OC EN
OUT
5-V Power
Supply
IN
GND
3.3 V
EN1
IN
OC1
OUT1
TPS2042B
EN2
OC2
OUT2
GND
TPS76333
PWRON3
PWRON4
OVRCUR3
OVRCUR4
EN1
IN
OC1
OUT1
TPS2042B
EN2
OC2
OUT2
33 µF
(see Note A)
4.7 µF
0.1 µF
4.7 µF
0.1 µF
33 µF
(see Note A)
33 µF
(see Note A)
33 µF
(see Note A)
0.1 µF
TPS2041B-Q1
TPS2042B-Q1
TPS2051B-Q1
SLVS782B – NOVEMBER 2007–REVISED OCTOBER 2011
www.ti.com
A. USB rev 1.1 requires 120 μF per hub.
Figure 28. Hybrid Self-Powered/Bus-Powered Hub Implementation (TPS2042B)
20 Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated
Product Folder Link(s): TPS2041B-Q1 TPS2042B-Q1 TPS2051B-Q1
Power
Supply
0.1 µF
1000 µF
Optimum
2.7 V to 5.5 V
PC Board
Overcurrent Response
TPS2042B
OC1
GND
EN1
IN
EN2
OUT1
OUT2
OC2
Block of
Circuitry
Block of
Circuitry
TPS2041B-Q1
TPS2042B-Q1
TPS2051B-Q1
www.ti.com
Generic Hot-Plug Applications
In many applications, it may be necessary to remove modules or PC boards while the main unit is still operating.
These are considered hot-plug applications. Such implementations require the control of current surges seen by
the main power supply and the card being inserted. The most effective way to control these surges is to limit and
slowly ramp the current and voltage being applied to the card, similar to the way in which a power supply
normally turns on. Due to the controlled rise times and fall times of the TPS204xB/TPS205xB, these devices can
be used to provide a softer startup to devices being hot-plugged into a powered system. The UVLO feature of the
TPS204xB/TPS205xB also ensures that the switch is off after the card has been removed, and that the switch is
off during the next insertion. The UVLO feature ensures a soft start with a controlled rise time for every insertion
of the card or module.
SLVS782B – NOVEMBER 2007–REVISED OCTOBER 2011
Figure 29. Typical Hot-Plug Implementation (Example, TPS2042B)
By placing the TPS204xB/TPS205xB between the VCCinput and the rest of the circuitry, the input power reaches
these devices first after insertion. The typical rise time of the switch is approximately 1 ms, providing a slow
voltage ramp at the output of the device. This implementation controls system surge currents and provides a
hot-plugging mechanism for any device.
DETAILED DESCRIPTION
Power Switch
The power switch is an N-channel MOSFET with a low on-state resistance. Configured as a high-side switch, the
power switch prevents current flow from OUT to IN and IN to OUT when disabled. The power switch supplies a
minimum current of 500 mA.
Charge Pump
An internal charge pump supplies power to the driver circuit and provides the necessary voltage to pull the gate
of the MOSFET above the source. The charge pump operates from input voltages as low as 2.7 V and requires
little supply current.
Driver
The driver controls the gate voltage of the power switch. To limit large current surges and reduce the associated
electromagnetic interference (EMI) produced, the driver incorporates circuitry that controls the rise times and fall
times of the output voltage.
Enable (ENx)
The logic enable pin disables the power switch and the bias for the charge pump, driver, and other circuitry to
reduce the supply current. The supply current is reduced to less than 1 μA or 2 μA when a logic high is present
on EN. A logic zero input on EN restores bias to the drive and control circuits and turns the switch on. The
enable input is compatible with both TTL and CMOS logic levels.
Copyright © 2007–2011, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Link(s): TPS2041B-Q1 TPS2042B-Q1 TPS2051B-Q1
TPS2041B-Q1
TPS2042B-Q1
TPS2051B-Q1
SLVS782B – NOVEMBER 2007–REVISED OCTOBER 2011
Enable (EN)
The logic enable disables the power switch and the bias for the charge pump, driver, and other circuitry to reduce
the supply current. The supply current is reduced to less than 1 μA or 2 μA when a logic low is present on EN. A
logic high input on EN restores bias to the drive and control circuits and turns the switch on. The enable input is
compatible with both TTL and CMOS logic levels.
Overcurrent (OCx)
The OCx open-drain output is asserted (active low) when an overcurrent or overtemperature condition is
encountered. The output remains asserted until the overcurrent or overtemperature condition is removed. A
10-ms deglitch circuit prevents the OCx signal from oscillation or false triggering. If an overtemperature shutdown
occurs, the OCx is asserted instantaneously.
Current Sense
A sense FET monitors the current supplied to the load. The sense FET measures current more efficiently than
conventional resistance methods. When an overload or short circuit is encountered, the current-sense circuitry
sends a control signal to the driver. The driver in turn reduces the gate voltage and drives the power FET into its
saturation region, which switches the output into a constant-current mode and holds the current constant while
varying the voltage on the load.
www.ti.com
Thermal Sense
The TPS204xB/TPS205xB implements a thermal sensing to monitor the operating temperature of the power
distribution switch. In an overcurrent or short-circuit condition, the junction temperature rises. When the die
temperature rises to approximately 140°C due to overcurrent conditions, the internal thermal sense circuitry turns
off the switch, thus preventing the device from damage. Hysteresis is built into the thermal sense, and after the
device has cooled approximately 10 degrees, the switch turns back on. The switch continues to cycle off and on
until the fault is removed. The open-drain false reporting output (OCx) is asserted (active low) when an
overtemperature shutdown or overcurrent occurs.
Undervoltage Lockout (UVLO)
A voltage sense circuit monitors the input voltage. When the input voltage is below approximately 2 V, a control
signal turns off the power switch.
SPACER
REVISION HISTORY
Changes from Original (November 2007) to Revision A Page
• Added the TPS2041B-Q1 device information ....................................................................................................................... 1
Changes from Revision A (June 2010) to Revision B Page
• Changed orderable part number From: TPS2041QDBVRQ1 To: TPS2041BQDBVRQ1 .................................................... 2
22 Submit Documentation Feedback Copyright © 2007–2011, Texas Instruments Incorporated
Product Folder Link(s): TPS2041B-Q1 TPS2042B-Q1 TPS2051B-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device Status
TPS2041BQDBVRQ1 ACTIVE SOT-23 DBV 5 3000 Green (RoHS
TPS2042BQDRQ1 ACTIVE SOIC D 8 2500 Green (RoHS
TPS2051BQDRQ1 ACTIVE SOIC D 8 2500 Green (RoHS
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Package Type Package
(1)
Drawing
Pins Package
Qty
Eco Plan
(2)
& no Sb/Br)
& no Sb/Br)
& no Sb/Br)
Lead/Ball Finish MSL Peak Temp
(3)
CU NIPDAU Level-1-260C-UNLIM -40 to 125 PLIQ
CU NIPDAU Level-1-260C-UNLIM -40 to 125 2042B
CU NIPDAU Level-1-260C-UNLIM -40 to 125 2051BQ
Op Temp (°C) Top-Side Markings
(4)
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Samples
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
OTHER QUALIFIED VERSIONS OF TPS2041B-Q1, TPS2042B-Q1, TPS2051B-Q1 :
Catalog: TPS2041B, TPS2042B, TPS2051B
•
Enhanced Product: TPS2041B-EP
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Enhanced Product - Supports Defense, Aerospace and Medical Applications
•
11-Apr-2013
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Mar-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
TPS2041BQDBVRQ1 SOT-23 DBV 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TPS2051BQDRQ1 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
Type
Package
Drawing
Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm)B0(mm)K0(mm)P1(mm)W(mm)
Pin1
Quadrant
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Mar-2013
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS2041BQDBVRQ1 SOT-23 DBV 5 3000 203.0 203.0 35.0
TPS2051BQDRQ1 SOIC D 8 2500 340.5 338.1 20.6
Pack Materials-Page 2
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