Texas Instruments TMS46400PDJ-80, TMS46400PDJ-70, TMS46400PDJ-60, TMS46400PDGA-80, TMS46400PDGA-70 Datasheet
...
TMS44400, TMS44400P, TMS46400, TMS46400P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS562C – MAY 1995 – REVISED NOVEMBER 1996
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
D
Organization ...1048576 × 4
D
Single 5-V Power Supply for TMS44400/P
(±10% Tolerance)
D
Single 3.3-V Power Supply for TMS46400/P
(±10% Tolerance)
D
Low Power Dissipation (TMS46400P only)
200-µA CMOS Standby
200-µA Self Refresh
300-µA Extended-Refresh Battery
Backup
D
Performance Ranges:
ACCESS ACCESS ACCESS READ
TIME TIME TIME OR WRITE
(t
RAC
)(t
CAC
)(tAA) CYCLE
(MAX) (MAX) (MAX) (MIN)
’4x400/P-60 60 ns 15 ns 30 ns 110 ns
’4x400/P-70 70 ns 18 ns 35 ns 130 ns
’4x400/P-80 80 ns 20 ns 40 ns 150 ns
D
Enhanced Page-Mode Operation for Faster
Memory Access
D
CAS-Before-RAS (CBR) Refresh
D
Long Refresh Period
1024-Cycle Refresh in 16 ms
128 ms (MAX) for Low-Power,
Self-Refresh Version (TMS4x400P)
D
3-State Unlatched Output
D
T exas Instruments EPIC CMOS Process
D
Operating Free-Air Temperature Range
0°C to 70°C
AVAILABLE OPTIONS
DEVICE
POWER
SUPPLY
SELF-REFRESH
BATTERY
BACKUP
REFRESH
CYCLES
TMS44400 5 V — 1024 in 16 ms
TMS44400P 5 V Yes 1024 in 128 ms
TMS46400 3.3 V — 1024 in 16 ms
TMS46400P 3.3 V Yes 1024 in 128 ms
These devices feature maximum RAS access times of 60 ns, 70 ns, and 80 ns. All addresses and data-in lines
are latched on chip to simplify system design. Data out is unlatched to allow greater system flexibility.
The TMS4x400 and TMS4x400P are offered in a 20/26-lead plastic small-outline (TSOP) package (DGA suffix)
and a 300-mil 20/26-lead plastic surface-mount SOJ package (DJ suffix). Both packages are characterized for
operation from 0°C to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
ADVANCE INFORMATION concerns new products in the sampling or
preproduction phase of development. Characteristic data and other
specifications are subject to change without notice.
PIN NOMENCLATURE
A0–A9 Address Inputs
CAS
Column-Address Strobe
DQ1–DQ4 Data In
OE
Output Enable
RAS
Row-Address Strobe
V
CC
5-V or 3.3-V Supply
V
SS
Ground
W
Write Enable
DJ PACKAGE
(TOP VIEW)
V
SS
DQ4
DQ3
CAS
OE
A8
A7
A6
A5
A4
26
25
24
23
22
18
17
16
15
14
1
2
3
4
5
9
10
11
12
13
DGA PACKAGE
(TOP VIEW)
DQ1
DQ2
W
RAS
A9
A0
A1
A2
A3
V
CC
V
SS
DQ4
DQ3
CAS
OE
A8
A7
A6
A5
A4
26
25
24
23
22
18
17
16
15
14
1
2
3
4
5
9
10
11
12
13
DQ1
DQ2
W
RAS
A9
A0
A1
A2
A3
V
CC
EPIC is a trademark of Texas Instruments Incorporated.
ADVANCE INFORMATION
description
The TMS4x400 series is a set of high-speed,
4 194 304-bit dynamic random-access memories
(DRAMs), organized as 1 048576 words of four
bits each. The TMS4x400P series is a set of
high-speed, low-power, self-refresh with
extended-refresh, 4194304-bit DRAMs,
organized as 1 048 576 words of four bits each.
Both series employ state-of-the-art enhanced
performance implanted CMOS (EPIC
)
technology for high performance, reliability, and
low power.
Copyright 1996, Texas Instruments Incorporated
TMS44400, TMS44400P, TMS46400, TMS46400P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS562C – MAY 1995 – REVISED NOVEMBER 1996
2
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
logic symbol
†
A0
A1
A2
A3
A4
A5
A6
A7
A8
RAS
CAS
W
OE
9
10
11
12
14
15
16
17
18
4
23
3
22
20D10/21D0
20D19/21D9
C20 [ROW]
G23/[REFRESH ROW]
24 [PWR DWN]
C21[COLUMN]
G24
23C22
23,21D 24
,25 EN
G25
A
0
1048575
RAM 1024K × 4
&
A9
5
1
2
24
25
A,Z26
A,22D
26
DQ1
DQ2
DQ3
DQ4
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DJ package.
functional block diagram
A0
A1
A9
16
Timing and Control
ColumnAddress
Buffers
Row-
Address
Buffers
I/O
Buffers
1 of 16
Selection
Data-
In
Reg.
Data-
Out
Reg.
Column Decode
Sense Amplifiers
R
o
w
D
e
c
o
d
e
16
128K Array
128K Array
128K Array
128K Array
128K Array
128K Array
RAS
CAS W
DQ1–DQ4
4
4
OE
2
8
10
10
16
16
2
ADVANCE INFORMATION
TMS44400, TMS44400P, TMS46400, TMS46400P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS562C – MAY 1995 – REVISED NOVEMBER 1996
3
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
operation
enhanced page mode
Enhanced-page-mode operation allows faster memory access by keeping the same row address while
selecting random column addresses. The time for row-address setup and hold and address multiplex is
eliminated. The maximum number of columns that can be accessed is determined by the maximum RAS
low
time and the CAS
page cycle time used. With minimum CAS page cycle time, all 1024 columns specified by
column addresses A0 through A9 can be accessed without intervening RAS
cycles.
Unlike conventional page-mode DRAMs, the column-address buffers in this device are activated on the falling
edge of RAS
. The buffers act as transparent or flow-through latches while CAS is high. The falling edge of CAS
latches the column addresses. This feature allows the TMS4x400 to operate at a higher data bandwidth than
conventional page-mode parts because data retrieval begins as soon as the column address is valid rather than
when CAS
transitions low. This performance improvement is referred to as enhanced page mode. A valid
column address can be presented immediately after row-address hold time has been satisfied, usually well in
advance of the falling edge of CAS
. In this case, data is obtained after t
CAC
maximum (access time from CAS
low) if tAA maximum (access time from column address) has been satisfied. In the event that column addresses
for the next cycle are valid at the time CAS
goes high, access time for the next cycle is determined by the later
occurrence of t
CAC
(acces time from CAS low) or t
CPA
(access time from column precharge).
address (A0–A9)
Twenty address bits are required to decode any one of the 1048576 storage-cell locations. Ten row-address
bits are set up on inputs A0 through A9 and latched onto the chip by RAS
. The ten column-address bits are set
up on A0 through A9 and latched onto the chip by CAS
. All addresses must be stable on or before the falling
edges of RAS
and CAS. RAS is similar to a chip enable because it activates the sense amplifiers as well as the
row decoder. CAS
is used as a chip select, activating the output buffer , as well as latching the address bits into
the column-address buffer.
write enable (W
)
The read or write mode is selected through W
input. A logic high on W selects the read mode and a logic low
selects the write mode. W
can be driven from standard TTL circuits (TMS44400/P) or low voltage TTL circuits
(TMS46400/P) without a pullup resistor. The data input is disabled when the read mode is selected. When W
goes low prior to CAS (early write), data out remains in the high-impedance state for the entire cycle, permitting
a write operation independent of the state of OE
. This permits early-write operation to complete with OE
grounded.
data in/out (DQ1–DQ4)
Data out is the same polarity as data in. The output is in the high-impedance (floating) state until CAS
and OE
are brought low. In a read cycle, the output becomes valid after all access times are satisfied. The output remains
valid while CAS
and OE are low. CAS or OE going high returns the output to a high-impedance state. This is
accomplished by bringing OE
high prior to applying data, satisfying the OE to data delay hold time (t
OED
).
output enable (OE
)
OE
controls the impedance of the output buffers. When OE is high, the buffers remain in the high-impedance
state. Bringing OE
low during a normal cycle activates the output buffers, putting them in the low-impedance
state. It is necessary for both RAS
and CAS to be brought low for the output buffers to go into the low-impedance
state. They remain in the low-impedance state until either OE
or CAS is brought high.
ADVANCE INFORMATION
TMS44400, TMS44400P, TMS46400, TMS46400P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS562C – MAY 1995 – REVISED NOVEMBER 1996
4
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
refresh
A refresh operation must be performed at least once every 16 ms (128 ms for TMS4x400P) to retain data. This
can be achieved by strobing each of the 1024 rows (A0–A9). A normal read or write cycle refreshes all bits in
each row that is selected. A RAS
-only operation can be used by holding CAS at the high (inactive) level,
conserving power as the output buffer remains in the high-impedance state. Externally generated addresses
must be used for a RAS
-only refresh. Hidden refresh can be performed while maintaining valid data at the
output. This is accomplished by holding CAS
at VIL after a read operation and cycling RAS after a specified
precharge period, similar to a RAS
-only refresh cycle. The external address is ignored during the hidden-refresh
cycle.
CAS
-before-RAS (CBR) refresh
CBR refresh is utilized by bringing CAS
low earlier than RAS (see parameter t
CSR
) and holding it low after RAS
falls (see parameter t
CHR
). For successive CBR refresh cycles, CAS can remain low while cycling RAS. The
external address is ignored and the refresh address is generated internally.
A low-power battery-backup refresh mode that requires less than 300-µA (TMS46400P) or 500-µA
(TMS44400P) refresh current is available on the low-power devices. Data integrity is maintained using CBR
refresh with a period of 125 µs while holding RAS
low for less than 1 µs. To minimize current consumption, all
input levels need to be at CMOS levels (V
IL
≤ 0.2 V, VIH ≥ VCC – 0.2 V).
self refresh
The self-refresh mode is entered by dropping CAS
low prior to RAS going low. CAS and RAS are both held low
for a minimum of 100 µs. The chip is then refreshed by an on-board oscillator. No external address is required
since the CBR counter is used to keep track of the address. To exit the self-refresh mode, both RAS
and CAS
are brought high to satisfy t
CHS
. Upon exiting the self-refresh mode, a burst refresh (refresh a full set of row
addresses) must be executed before continuing with normal operation, to ensure that the DRAM is fully
refreshed.
power up
T o achieve proper device operation, an initial pause of 200 µs followed by a minimum of eight initialization cycles
is required after full V
CC
level is achieved. These eight initialization cycles must include at least one refresh
(RAS
-only or CBR) cycle.
test mode
The test mode is initiated with a CBR refresh cycle while simultaneously holding W
low (WCBR). The entry cycle
performs an internal refresh cycle while internally setting the device to perform parallel read or write on
subsequent cycles. While in test mode, any desired data sequence can be performed on the device. The device
exits test mode if a CBR refresh cycle with W
held high or a RAS-only refresh (ROR) cycle is performed.
The TMS4x400/P is configured as a 512K × 8 bit device in test mode, where each DQ pin has a separate 2-bit
parallel read- and write-data bus. During a read cycle, the two internal bits are compared for each DQ pin
separately . If the two bits agree, the DQ pin goes high; if not, the DQ pin goes low. The two bits are written to
reflect the state of their respective DQ pins during a parallel-write operation. Each DQ pin is independent of the
others, and any data pattern desired can be written on each DQ pin. Test time is reduced by a factor of 4 for
this series.
ADVANCE INFORMATION
TMS44400, TMS44400P, TMS46400, TMS46400P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS562C – MAY 1995 – REVISED NOVEMBER 1996
5
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
test mode (continued)
Test Mode Cycle
Entry Cycle
Exit Cycle
Normal
Mode
RAS
CAS
W
Figure 1. Test-Mode Cycle Timing
†
†
The states of W, data in, and address are defined by the type of cycle used during test mode.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
‡
Supply voltage range, V
CC
: TMS44400, TMS44400P – 1.0 V to 7.0 V. . . . . . . . . . . . . . . . . . . . . . .
TMS46400, TMS46400P – 0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . .
Voltage range on any pin (see Note 1) TMS44400, TMS44400P – 1.0 V to 7.0 V. . . . . . . . . . . . . . . . . . . . . . .
TMS46400, TMS46400P – 0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . .
Short-circuit output current 50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power dissipation 1 W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, T
A
0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–55°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.
recommended operating conditions
TMS44400/P TMS46400/P
MIN NOM MAX MIN NOM MAX
UNIT
V
CC
Supply voltage 4.5 5 5.5 3 3.3 3.6 V
V
IH
High-level input voltage 2.4 6.5 2 VCC + 0.3 V
V
IL
Low-level input voltage (see Note 2) –1 0.8 – 0.3 0.8 V
T
A
Operating free-air temperature 0 70 0 70
°C
NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only.
ADVANCE INFORMATION
TMS44400, TMS44400P, TMS46400, TMS46400P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS562C – MAY 1995 – REVISED NOVEMBER 1996
6
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
TEST
’44400-60
’44400P-60
’44400-70
’44400P-70
’44400-80
’44400P-80
UNIT
PARAMETER
CONDITIONS
MIN MAX MIN MAX MIN MAX
UNIT
V
OH
High-level output voltage IOH = – 5 mA 2.4 2.4 2.4 V
V
OL
Low-level output voltage IOL = 4.2 mA 0.4 0.4 0.4 V
I
I
Input current (leakage)
VCC = 5.5 V,
VI = 0 V to 6.5 V,
All others = 0 V to V
CC
± 10 ± 10 ± 10 µA
I
O
Output current (leakage)
VCC = 5.5 V, VO = 0 V to VCC,
CAS
high
± 10 ± 10 ± 10 µA
I
CC1
Read- or write-cycle current
(see Note 3)
VCC = 5.5 V, Minimum cycle 105 90 80 mA
After one memory cycle,
RAS
and CAS high,
VIH = 2.4 V (TTL)
2 2 2 mA
I
CC2
Standby current
After one memory
cycle, RAS
and CAS
’44400 1 1 1 mA
high
,
VIH = VCC – 0.2 V
(CMOS)
’44400P 500 500 500 µA
I
CC3
Average refresh current
(RAS
only or CBR)
(see Note 4)
VCC = 5.5 V, Minimum cycle,
RAS
cycling,
CAS
high (RAS only);
RAS
low after CAS low (CBR)
105 90 80 mA
I
CC4
Average page
current
(see Notes 3 and 5)
VCC = 5.5 V, tPC = MIN,
RAS
low, CAS cycling
90 80 70 mA
I
CC6
†
Self-refresh current
(see Note 3)
CAS ≤ 0.2 V , RAS < 0.2 V,
t
RAS
and t
CAS
> 1000 ms
500 500 500 µA
I
CC7
Standby current, outputs
enabled (see Note 3)
RAS = VIH, CAS = VIL,
Data out = enabled
5 5 5 mA
I
CC10
†
Battery-backup current
(with CBR)
tRC = 125 µs, t
RAS
≤ 1 ms,
VCC – 0.2 V ≤ VIH ≤ 6.5 V,
0 V ≤ VIL ≤ 0.2 V,
W
and OE = VIH,
Address and data stable
500 500 500 µA
†
For TMS44400P only
NOTES: 3. ICC MAX is specified with no load connected.
4. Measured with a maximum of one address change while RAS
= V
IL
5. Measured with a maximum of one address change while CAS
= V
IH
ADVANCE INFORMATION
TMS44400, TMS44400P, TMS46400, TMS46400P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS562C – MAY 1995 – REVISED NOVEMBER 1996
7
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
TEST
’46400-60
’46400P-60
’46400-70
’46400P-70
’46400-80
’46400P-80
UNIT
PARAMETER
CONDITIONS
MIN MAX MIN MAX MIN MAX
UNIT
High-level
IOH = – 2 mA (LVTTL) 2.4 2.4 2.4
V
OH
High level
output voltage
IOH = – 100 µA (LVCMOS)
VCC–0.2 VCC–0.2 VCC–0.2
V
Low-level
IOL = 2 mA (LVTTL) 0.4 0.4 0.4
V
OL
Low level
output voltage
IOL = 100 µA (LVCMOS)
0.2 0.2 0.2
V
I
I
Input current
(leakage)
VI = 0 V to 3.9 V, VCC = 3.6 V,
All others = 0 V to V
CC
± 10 ± 10 ± 10 µA
I
O
Output current
(leakage)
VO = 0 V to VCC,VCC = 3.6 V,
CAS
high
± 10 ± 10 ± 10 µA
I
CC1
Read- or
write-cycle
current
(see Note 3)
Minimum cycle, VCC = 3.6 V 70 60 50 mA
After one memory cycle,
RAS
and CAS high,
VIH = 2 V (LVTTL)
2 2 2 mA
I
CC2
Standby
current
After one memory
cycle, RAS
and CAS
’46400 300 300 300 µA
high
,
VIH = VCC – 0.2 V
(LVCMOS)
’46400P 200 200 200 µA
I
CC3
Average
refresh current
(RAS
only or
CBR)
(see Note 4)
Minimum cycle, VCC = 3.6 V,
RAS
cycling,
CAS
high (RAS only);
RAS
low after CAS low (CBR)
70 60 50 mA
I
CC4
Average page
current
(see Notes 3
and 5)
tPC = MIN, VCC = 3.6 V,
RAS
low, CAS cycling
60 50 40 mA
I
CC6
†
Self-refresh
current
(see Note 3)
CAS ≤ 0.2 V , RAS < 0.2 V,
t
RAS
and t
CAS
> 1000 ms
200 200 200 µA
I
CC7
Standby
current,
outputs
enabled
(see Note 3)
RAS = VIH, CAS = VIL,
Data out = enabled
5 5 5 mA
I
CC10
†
Battery-backup
current
(with CBR)
tRC = 125 µs, t
RAS
≤ 1 ms,
VCC – 0.2 V ≤ VIH ≤ 3.9 V,
0 V ≤ VIL ≤ 0.2 V,
W
and OE = VIH,
Address and data stable
300 300 300 µA
†
For TMS46400P only
NOTES: 3. ICC MAX is specified with no load connected.
4. Measured with a maximum of one address change while RAS
= V
IL
5. Measured with a maximum of one address change while CAS
= V
IH
ADVANCE INFORMATION
TMS44400, TMS44400P, TMS46400, TMS46400P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS562C – MAY 1995 – REVISED NOVEMBER 1996
8
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 6)
PARAMETER MIN MAX UNIT
C
i(A)
Input capacitance, A0–A10 5 pF
C
i(RC)
Input capacitance, CAS and RAS 7 pF
C
i(OE)
Input capacitance, OE 7 pF
C
i(W)
Input capacitance, W 7 pF
C
o
Output capacitance 7 pF
NOTE 6: VCC = 5 V ± .5 V for the TMS44400 devices, VCC = 3.3 V ± 0.3 V for the TMS46400 devices, and the bias on pins under test is 0 V .
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
PARAMETER
’4x400 - 60
’4x400P -60
’4x400 - 70
’4x400P -70
’4x400 - 80
’4x400P -80
UNIT
PARAMETER
MIN MAX MIN MAX MIN MAX
UNIT
t
AA
Access time from column address 30 35 40 ns
t
CAC
Access time from CAS low 15 18 20 ns
t
CPA
Access time from column precharge 35 40 45 ns
t
RAC
Access time from RAS low 60 70 80 ns
t
OEA
Access time from OE low 15 18 20 ns
t
CLZ
CAS to output in low impedance 0 0 0 ns
t
OFF
Output-disable time after CAS high (see Note 7) 0 15 0 18 0 20 ns
t
OEZ
Output-disable time after OE high (see Note 7) 0 15 0 18 0 20 ns
NOTE 7: t
OFF
is specified when the output is no longer driven.
ADVANCE INFORMATION
TMS44400, TMS44400P, TMS46400, TMS46400P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS562C – MAY 1995 – REVISED NOVEMBER 1996
9
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
’4x400-60
’4x400P-60
’4x400-70
’4x400P-70
’4x6400-80
’4x400P-80
UNIT
MIN MAX MIN MAX MIN MAX
UNIT
t
RC
Cycle time, random read or write (see Note 8) 110 130 150 ns
t
RWC
Cycle time, read-write 155 181 205 ns
t
PC
Cycle time, page-mode read or write (see Note 9) 40 45 50 ns
t
PRWC
Cycle time, page-mode read-write 85 96 105 ns
t
RASP
Pulse duration, RAS low, page mode (see Note 10) 60 100 000 70 100 000 80 100 000 ns
t
RAS
Pulse duration, RAS low, nonpage mode (see Note 10) 60 10 000 70 10 000 80 10 000 ns
t
RASS
Pulse duration, RAS low, self refresh 100 100 100 µs
t
CAS
Pulse duration, CAS low (see Note 11) 10 10 000 18 10 000 20 10 000 ns
t
CP
Pulse duration, CAS high 10 10 10 ns
t
RP
Pulse duration, RAS high (precharge) 40 50 60 ns
t
RPS
Precharge time after self refresh using RAS 110 130 150 ns
t
WP
Pulse duration, write 10 10 10 ns
t
ASC
Setup time, column address before CAS low 0 0 0 ns
t
ASR
Setup time, row address before RAS low 0 0 0 ns
t
DS
Setup time, data (see Note 12) 0 0 0 ns
t
RCS
Setup time, W high before CAS low 0 0 0 ns
t
CWL
Setup time, W low before CAS high 15 18 20 ns
t
RWL
Setup time, W low before RAS high 15 18 20 ns
t
WCS
Setup time, W low before CAS low (early-write operation only) 0 0 0 ns
t
WSR
Setup time, W high (CBR refresh only) 10 10 10 ns
t
WTS
Setup time, W low (test mode only) 10 10 10 ns
t
CAH
Hold time, column address after CAS low 10 15 15 ns
t
DHR
Hold time, data after RAS low (see Note 13) 50 55 60 ns
t
DH
Hold time, data (see Note 12) 10 15 15 ns
t
AR
Hold time, column address after RAS low (see Note 13) 50 55 60 ns
t
RAH
Hold time, row address after RAS low 10 10 10 ns
t
RCH
Hold time, W high after CAS high (see Note 14) 0 0 0 ns
t
RRH
Hold time, W high after RAS high (see Note 14) 0 0 0 ns
t
WCH
Hold time, W low after CAS low (early-write operation only) 10 15 15 ns
t
WCR
Hold time, W low after RAS low (see Note 13) 50 55 60 ns
t
WHR
Hold time, W high (CBR refresh only) 10 10 10 ns
t
WTH
Hold time, W low (test mode only) 10 10 10 ns
t
CHS
Hold time, CAS low after RAS high (self refresh) – 50 – 50 – 50 ns
t
OEH
Hold time, OE command 15 18 20 ns
t
OED
Hold time, OE to data delay 15 18 20 ns
NOTES: 8. All cycle times assume tT = 5 ns.
9. To ensure tPC min, t
ASC
should be ≥ tCP.
10. In a read-write cycle, t
RWD
and t
RWL
must be observed.
11. In a read-write cycle, t
CWD
and t
CWL
must be observed.
12. Referenced to the later of CAS
or W in write operations
13. The minimum value is measured when t
RCD
is set to t
RCD
min as a reference.
14. Either t
RRH
or t
RCH
must be satisfied for a read cycle.
ADVANCE INFORMATION
TMS44400, TMS44400P, TMS46400, TMS46400P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS562C – MAY 1995 – REVISED NOVEMBER 1996
10
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (continued)
’4x400-60
’4x400P-60
’4x400-70
’4x400P-70
’4x400-80
’4x400P-80
UNIT
MIN MAX MIN MAX MIN MAX
UNIT
t
ROH
Hold time, RAS referenced to OE 10 10 10 ns
t
AWD
Delay time, column address to W low (read-write operation only) 55 63 70 ns
t
CHR
Delay time, RAS low to CAS high (CBR refresh only) 10 10 10 ns
t
CRP
Delay time, CAS high to RAS low 0 0 0 ns
t
CSH
Delay time, RAS low to CAS high 60 70 80 ns
t
CSR
Delay time, CAS low to RAS low (CBR refresh only) 5 5 5 ns
t
CWD
Delay time, CAS low to W low (read-write operation only) 40 46 50 ns
t
RAD
Delay time, RAS low to column address (see Note 15) 15 30 15 35 15 40 ns
t
RAL
Delay time, column address to RAS high 30 35 40 ns
t
CAL
Delay time, column address to CAS high 30 35 40 ns
t
RCD
Delay time, RAS low to CAS low (see Note 15) 20 45 20 52 20 60 ns
t
RPC
Delay time, RAS high to CAS low 0 0 0 ns
t
RSH
Delay time, CAS low to RAS high 15 18 20 ns
t
RWD
Delay time, RAS low to W low (read-write operation only) 85 98 110 ns
t
TAA
Access time from address (test mode) 35 40 45 ns
t
TCPA
Access time from column precharge (test mode) 40 45 50 ns
t
TRAC
Access time from RAS (test mode) 65 75 85 ns
’4x400 16 16 16 ms
t
REF
Ref
resh time interva
l
’4x400P 128 128 128 ms
t
T
Transition time 2 30 2 30 2 30 ns
NOTE 15: The maximum value is specified only to ensure access time.
PARAMETER MEASUREMENT INFORMATION
1.31 V VCC = 5 V
CL = 100 pF
(see Note A)
Output Under TestOutput Under Test
CL = 100 pF
(see Note A)
(b) ALTERNATE LOAD CIRCUIT(a) LOAD CIRCUIT
RL = 218 Ω R1 = 828 Ω
R2 = 295 Ω
NOTE A: CL includes probe and fixture capacitance.
Figure 2. Load Circuits for Timing Parameters
ADVANCE INFORMATION
TMS44400, TMS44400P, TMS46400, TMS46400P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS562C – MAY 1995 – REVISED NOVEMBER 1996
11
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
PARAMETER MEASUREMENT INFORMATION
1.4 V VCC = 3.3 V
CL = 100 pF
(see Note A)
Output Under Test
Output Under Test
CL = 100 pF
(see Note A)
(b) ALTERNATE LOAD CIRCUIT(a) LOAD CIRCUIT
RL = 500 Ω
R1 = 1178 Ω
R2 = 868 Ω
NOTE A: CL includes probe and fixture capacitance.
Figure 3. Low-Voltage Load Circuits for Timing Parameters
RAS
CAS
A0–A9
W
DQ1–DQ4
t
RC
Row Column
Don’t Care
Don’t Care Don’t Care
t
RAS
t
RP
t
CSH
t
RCD
t
RSH
t
CRP
t
CAS
t
RAD
t
ASC
t
RAL
t
ASR
t
RCS
t
CAH
t
RRH
t
RCH
t
CAC
t
OFF
t
AA
t
CLZ
t
RAC
t
CP
See Note A
Hi-Z
t
AR
t
RAH
t
CAL
Valid Data Out
Don’t Care
t
OEZ
t
ROH
t
OEA
Don’t Care
OE
t
T
NOTE A: Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
Figure 4. Read-Cycle Timing
ADVANCE INFORMATION
TMS44400, TMS44400P, TMS46400, TMS46400P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS562C – MAY 1995 – REVISED NOVEMBER 1996
12
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
PARAMETER MEASUREMENT INFORMATION
RAS
CAS
A0–A9
W
DQ1–DQ4
t
RC
Row Column
Don’t Care
Don’t Care Don’t Care
Valid Data
Don’t Care
t
RP
t
RAS
t
RSH
t
CRP
t
CAS
t
RCD
t
T
t
CSH
t
ASC
t
ASR
t
RAH
t
CAH
t
CP
t
RAD
t
CWL
t
RWL
t
WCH
t
WCS
t
WP
t
DH
t
DS
t
DHR
t
WCR
t
AR
t
CAL
t
RAL
Don’t Care
OE
Figure 5. Early-Write-Cycle Timing
ADVANCE INFORMATION
TMS44400, TMS44400P, TMS46400, TMS46400P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS562C – MAY 1995 – REVISED NOVEMBER 1996
13
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
PARAMETER MEASUREMENT INFORMATION
RAS
CAS
A0–A9
W
DQ1–DQ4
t
RC
Row Column
Don’t Care
Don’t Care Don’t Care
Valid Data
Don’t CareDon’t Care
t
RAS
t
RP
t
RSH
t
CRP
t
CAS
t
RCD
t
CSH
t
T
t
ASR
t
RAH
t
ASC
t
RAL
t
CAH
t
RAD
t
CWL
t
RWL
t
WP
t
DS
t
DH
t
CP
t
DHR
t
WCR
t
AR
t
OEH
t
CAL
OE
Don’t Care Don’t Care
t
OED
Figure 6. Write-Cycle Timing
ADVANCE INFORMATION
TMS44400, TMS44400P, TMS46400, TMS46400P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS562C – MAY 1995 – REVISED NOVEMBER 1996
14
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
PARAMETER MEASUREMENT INFORMATION
DQ1–DQ4
RAS
CAS
A0–A9
W
OE
t
RWC
t
RAS
t
RP
t
CRP
t
CAS
t
T
t
RCD
t
ASR
t
RAH
t
RAD
t
AR
t
ASC
t
CAH
t
CP
t
T
t
CWL
t
RWL
t
WP
t
RCS
t
RWD
t
AWD
t
CWD
t
CAC
t
AA
t
CLZ
t
DS
t
DH
t
RAC
t
OEH
t
OED
t
OEZ
t
OEH
Don’t Care
Don’t Care
Don’t Care
Don’t CareDon’t Care
Row Column
See Note A
Data
In
Data
Out
NOTE A: Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
Figure 7. Read-Write-Cycle Timing
ADVANCE INFORMATION
TMS44400, TMS44400P, TMS46400, TMS46400P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS562C – MAY 1995 – REVISED NOVEMBER 1996
15
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
PARAMETER MEASUREMENT INFORMATION
RAS
CAS
A0–A9
W
DQ1–DQ4
t
RP
Row Column
Don’t Care
Valid
Out
See Note B
Valid
Out
t
RASP
t
RCD
t
CSH
t
CAS
t
CP
t
PC
t
RSH
t
CRP
t
RAH
t
ASC
t
RAL
t
ASR
t
RRH
t
RCH
t
RAD
t
CAC
t
AA
t
RAC
t
CLZ
t
OFF
Column
t
AR
t
CAH
t
RCS
t
CAL
t
T
Don’t Care
OE
t
OEA
t
OEZ
t
OEA
t
OEZ
t
CPA
(see Note A)
t
AA
(see Note A)
NOTES: A. Access time is t
CPA
or tAA dependent.
B. Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
Figure 8. Enhanced-Page-Mode Read-Cycle Timing
ADVANCE INFORMATION
TMS44400, TMS44400P, TMS46400, TMS46400P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS562C – MAY 1995 – REVISED NOVEMBER 1996
16
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
PARAMETER MEASUREMENT INFORMATION
RAS
CAS
A0–A9
W
Row Column Don’t Care
See Note A
See Note A
Valid
In
t
RP
Valid Data In Don’t Care
Don’t Care Don’t Care Don’t Care
Column
t
RASP
t
CSH
t
PC
t
CRP
t
RSH
t
CAS
t
RCD
t
RAH
t
CAH
t
CP
t
RAD
t
CWL
t
WP
t
RWL
t
DH
t
DH
t
DS
t
DS
t
RAL
t
AR
t
DHR
t
WCR
See Note A
t
CAL
DQ1–DQ4
Don’t Care Don’t CareOE
t
OEH
t
OED
t
OEH
t
ASR
t
ASC
t
CWL
NOTES: A. Referenced to CAS
or W, whichever occurs last
B. A read cycle or a read-write cycle can be intermixed with write cycles as long as read and read-write timing specifications are not
violated.
Figure 9. Enhanced-Page-Mode Write-Cycle Timing
ADVANCE INFORMATION
TMS44400, TMS44400P, TMS46400, TMS46400P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS562C – MAY 1995 – REVISED NOVEMBER 1996
17
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
PARAMETER MEASUREMENT INFORMATION
t
RASP
t
RP
RAS
CAS
A0–A9
W
DQ1–DQ4
OE
t
CSH
t
PRWC
t
RCD
t
CAS
t
RSH
t
CRP
t
CP
t
ASR
t
ASC
t
AR
t
RAD
t
CAH
Row Column Column
Don’t Care
t
CWL
t
RWL
t
RAH
t
CWD
t
AWD
t
RWD
t
WP
t
RCS
t
AA
t
RAC
t
CAC
t
CPA
t
DH
Valid Out
(see Note A)
Valid Out
Valid In V alid In
t
CLZ
t
OEA
t
OEZ
t
OEH
t
OED
t
OEH
t
DS
NOTES: A. Output can go from the high-impedance state to an invalid-data state prior to the specified access time.
B. A read or write cycle can be intermixed with read-write cycles as long as the read and write timing specifications are not violated.
Figure 10. Enhanced-Page-Mode Read-Write-Cycle Timing
ADVANCE INFORMATION
TMS44400, TMS44400P, TMS46400, TMS46400P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS562C – MAY 1995 – REVISED NOVEMBER 1996
18
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
PARAMETER MEASUREMENT INFORMATION
t
RC
t
RAS
t
RP
t
T
t
ASR
t
RAH
t
CRP
RAS
CAS
A0–A9
W
DQ1–DQ4
OE
Don’t Care
Don’t Care Row RowDon’t Care
Don’t Care
Don’t Care
t
RPC
Don’t Care
Figure 11. RAS-Only Refresh-Cycle Timing
ADVANCE INFORMATION
TMS44400, TMS44400P, TMS46400, TMS46400P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS562C – MAY 1995 – REVISED NOVEMBER 1996
19
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
PARAMETER MEASUREMENT INFORMATION
RAS
CAS
W
A0–A9
DQ1–DQ4
t
RC
Don’t Care
Don’t Care
Hi-Z
t
RAS
t
RP
t
CSR
t
RPC
t
T
t
CHR
t
WSR
t
WHR
OE
Figure 12. Automatic-CBR-Refresh-Cycle Timing
RAS
CAS
W
A0–A9
DQ1–DQ4
Don’t Care
Don’t Care
Hi-Z
t
RASS
t
RP
t
CSR
t
RPC
t
T
t
CHS
t
WSR
t
WHR
OE
t
RPS
Figure 13. Self-Refresh-Cycle Timing
ADVANCE INFORMATION
TMS44400, TMS44400P, TMS46400, TMS46400P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS562C – MAY 1995 – REVISED NOVEMBER 1996
20
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
PARAMETER MEASUREMENT INFORMATION
RAS
CAS
A0–A10
Row Col
Don’t Care
W
DQ1–DQ4
OE
Valid Data
t
RAS
t
RP
t
RP
t
RAS
t
CAS
t
CAH
t
ASC
t
WHR
t
WHR
t
CAC
t
AA
t
OFF
t
CHR
Refresh Cycle
Refresh Cycle
Memory Cycle
t
AR
t
WHR
t
CLZ
t
OEZ
t
RAH
t
ASR
t
WSR
t
WSR
t
WSR
t
RAC
t
RCS
t
RRH
t
OEA
Figure 14. Hidden-Refresh-Cycle (Read) Timing
ADVANCE INFORMATION
TMS44400, TMS44400P, TMS46400, TMS46400P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS562C – MAY 1995 – REVISED NOVEMBER 1996
21
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
PARAMETER MEASUREMENT INFORMATION
t
DHR
RAS
CAS
A0–A9
W
DQ1–DQ4
OE
Row Col Don’t Care
Don’t Care
Refresh Cycle
Memory Cycle
Refresh Cycle
t
RAS
t
RP
t
RAS
t
RP
t
CHR
t
CAS
t
CAH
t
ASC
t
RAH
t
WP
t
WSR
t
WHR
t
DH
t
DS
t
WCH
t
AR
t
WCR
Valid Data
Don’t Care
t
RRH
t
WCS
t
ASR
Figure 15. Hidden-Refresh-Cycle (Write) Timing
ADVANCE INFORMATION
TMS44400, TMS44400P, TMS46400, TMS46400P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS562C – MAY 1995 – REVISED NOVEMBER 1996
22
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
PARAMETER MEASUREMENT INFORMATION
RAS
CAS
W
A0–A9
OE
DQ1–DQ4
t
RC
Don’t Care
Don’t Care
Hi-Z
t
RAS
t
RP
t
CSR
t
RPC
t
T
t
CHR
t
WTS
Don’t Care
t
WTH
Figure 16. Test-Mode Entry-Cycle Timing
device symbolization (TMS44400 illustrated)
Speed ( -60, - 70, -80)
Package Code
Low-Power/Self-Refresh Designator (Blank or P)
-SS
TMS44400 DJ
Assembly Site Code
Lot Traceability Code
Year Code
Die Revision Code
Wafer Fab Code
PLLLYBW M
Month Code
ADVANCE INFORMATION
TMS44400, TMS44400P, TMS46400, TMS46400P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS562C – MAY 1995 – REVISED NOVEMBER 1996
23
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
PARAMETER MEASUREMENT INFORMATION
DJ (R-PDSO-J20/26) PLASTIC SMALL-OUTLINE J-LEAD PACKAGE
4040092-2/B 10/94
0.330 (8,38)
0.340 (8,64)
0.106 (2,69) MAX
0.008 (0,20) NOM
0.260 (6,60)
0.275 (6,99)
Seating Plane
14
139
22
5
0.032 (0,81)
0.026 (0,66)
18
0.680 (17,27)
0.670 (17,02)
26
1
0.148 (3,76)
0.016 (0,41)
0.020 (0,51)
0.128 (3,25)
0.305 (7,75)
0.295 (7,49)
0.004 (0,10)
M
0.007 (0,18)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Plastic body dimensions do not include mold protrusion. Maximum mold protrusion is 0.005 (0,125).
ADVANCE INFORMATION
TMS44400, TMS44400P, TMS46400, TMS46400P
1048576-WORD BY 4-BIT
DYNAMIC RANDOM-ACCESS MEMORIES
SMHS562C – MAY 1995 – REVISED NOVEMBER 1996
24
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
MECHANICAL DATA
DGA (R-PDSO-G20/26) PLASTIC SMALL-OUTLINE PACKAGE
4040265-2/B 10/94
0.304 (7,72)
0.296 (7,52)
0.050 (1,27) MAX
0.004 (0,10) MIN
1
26
0.671 (17,04)
0.679 (17,24)
13
0.012 (0,30)
0.020 (0,50)
14
0.016 (0,40)
Seating Plane
0.006 (0,15) NOM
0.355 (9,02)
0.371 (9,42)
Gage Plane
0.010 (0,25)
0.024 (0,60)
0.004 (0,10)
M
0.008 (0,21)
0.050 (1,27)
0°–ā5°
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
ADVANCE INFORMATION
IMPORTANT NOTICE
T exas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor
product or service without notice, and advises its customers to obtain the latest version of relevant information
to verify, before placing orders, that the information being relied on is current.
TI warrants performance of its semiconductor products and related software to the specifications applicable at
the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are
utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each
device is not necessarily performed, except those mandated by government requirements.
Certain applications using semiconductor products may involve potential risks of death, personal injury, or
severe property or environmental damage (“Critical Applications”).
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED
TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER
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Inclusion of TI products in such applications is understood to be fully at the risk of the customer. Use of TI
products in such applications requires the written approval of an appropriate TI officer. Questions concerning
potential risk applications should be directed to TI through a local SC sales office.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards should be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance, customer product design, software performance, or
infringement of patents or services described herein. Nor does TI warrant or represent that any license, either
express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property
right of TI covering or relating to any combination, machine, or process in which such semiconductor products
or services might be or are used.
Copyright 1996, Texas Instruments Incorporated
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