Texas Instruments TMS320F20x, TMS320F24x DSP User Manual

TMS320F20x/F24x DSP

Embedded Flash Memory

Technical Reference

This document contains preliminary data

current as of publication date and is subject

to change without notice.

Literature Number: SPRU282

September 1998

Printed on Recycled Paper

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Copyright  1998, Texas Instruments Incorporated

PRELIMINARY

About This Manual

This reference guide describes the operation of the embedded flash EEPROM
module on the TMS320F20x/F24x digital signal processor (DSP) devices and
provides sample code that you can use in developing your own software. The
performance specifications of the embedded flash memory have been evalu­ated using the algorithms and techniques described in this guide. TI does not
recommend deviation from these algorithms and techniques, since doing so
could affect device performance. The book does not describe the use of any
specific flash programming tool nor does it describe the external interface to
the DSP. For information about any aspect of the TMS320F20x/F24x devices
other than the embedded flash EEPROM module, see

tion from Texas Instruments

How to Use This Manual

Preface

Read This First

Related Documenta-

on page v.

PRELIMINARY

There are several stand-alone flash programming tools for TMS320F20x/
F24x generation of DSPs. Using one of these stand-alone tools with the
TMS320F20x/F24x requires only a basic understanding of the flash opera­tions. More information about these flash programming tools is available on
the TI web page, http://www.ti.com. This guide is intended to provide a
complete understanding of the flash operations. This level of understanding
is necessary for making modifications to existing flash programming tools
or for developing alternative programming schemes.

If you are looking for in­formation about:

Algorithms Chapter 3,

Erasing the flash array Section 1.1,

T urn to these locations:

Algorithm Implementations and

Software Considerations

Basic Concepts of Flash Memory

Technology

Section 2.1,

TMS320F20x/F24x Flash Array

Section 2.6,
Section 3.3,

Modifying the Contents of the
Erase Operation

Erase Algorithm

iii

If you are looking for in­formation about:

T urn to these locations:

PRELIMINARY

Over-erasure (depletion) and
recovery

Programming the flash array Section 1.1,

Sample code Appendix A,

Notational Conventions

This document uses the following conventions.

- The flash EEPROM is referred to as flash memory or the flash module.

Section 1.1,

Technology

Section 2.7,

(Flash-Write Operation)

Section 3.4,

Technology

Section 2.1,

TMS320F20x/F24x Flash Array

Section 2.5,
Section 3.2,

Program Examples

Basic Concepts of Flash Memory
Recovering From Over-Erasure
Flash-Write Algorithm

Basic Concepts of Flash Memory
Modifying the Contents of the
Program Operation

Programming Algorithm

Assembly Source Listings and

The term flash array refers to the actual memory array within the flash
module. The flash module includes the flash memory array and the associ­ated control circuitry.

- The DSP generation and devices are abbreviated as follows:
J TMS320F20x/24x generation: ’F20x/24x
J TMS320F20x devices: ’F20x
J TMS320F24x devices: ’F24x

- Program listings and code examples are shown in a special type-

face.
Here is a sample program listing:

0011 0005 0001 .field 1, 2
0012 0005 0003 .field 3, 4
0013 0005 0006 .field 6, 3
0014 0006 .even

iv

PRELIMINARY

PRELIMINARY

Related Documentation From Texas Instruments

The following books describe the ’F20x/24x and related support tools. To ob­tain a copy of any of these TI documents, call the T exas Instruments Literature
Response Center at (800) 477–8924. When ordering, please identify the book
by its title and literature number.

TMS320C24x DSP Controllers Reference Set, Volume 1: CPU, System,

and Instruction Set

TMS320C24x 16-bit, fixed-point, digital signal processor controller.
Covered are its architecture, internal register structure, data and
program addressing, and instruction set. Also includes instruction set
comparisons and design considerations for using the XDS510 emulator .

TMS320C24x DSP Controllers Reference Set Volume 2: Peripheral

Library and Specific Devices

the peripherals available on the TMS320C24x digital signal processor
controllers and their operation. Also described are specific device
configurations of the ’C24x family.

(literature number SPRU160) describes the

Related Documentation From Texas Instruments

(literature number SPRU161) describes

TMS320C240, TMS320F240 DSP Controllers

data sheet contains the electrical and timing specifications for these
devices, as well as signal descriptions and pinouts for all of the available
packages.

(literature number SPRS042)

TMS320C2x/C2xx/C5x Optimizing C Compiler User’s Guide

number SPRU024) describes the ’C2x/C2xx/C5x C compiler. This C
compiler accepts ANSI standard C source code and produces TMS320
assembly language source code for the ’C2x, ’C2xx, and ’C5x genera­tions of devices.

TMS320F206 Digital Signal Processor

sheet contains the electrical and timing specifications for the ’F206
device, as well as signal descriptions and the pinout.

(literature number SPRS050) data

TMS320F241, TMS320C241, TMS320C242 DSP Controllers

number SPRS063) data sheet contains the electrical and timing
specifications for the ’F241, ’C241, and ’C242 devices, as well as signal
descriptions and pinouts.

TMS320F243 DSP Controller

contains the electrical and timing specifications for the ’F243 device, as
well as signal descriptions and the pinout.

TMS320C2xx User’s Guide

hardware aspects of the ’C2xx 16-bit, fixed-point digital signal proces­sors. It describes the architecture, the instruction set, and the on-chip pe­ripherals.

(literature number SPRS064) data sheet

(literature number SPRU127) discusses the

(literature

(literature

PRELIMINARY

Read This First

v

Related Documentation From Texas Instruments

PRELIMINARY

TMS320C2xx C Source Debugger User’s Guide

SPRU151) tells you how to invoke the ’C2xx emulator and simulator ver­sions of the C source debugger interface. This book discusses various
aspects of the debugger interface, including window management, com­mand entry , code execution, data management, and breakpoints. It also
includes a tutorial that introduces basic debugger functionality.

(literature number

vi

PRELIMINARY

PRELIMINARY

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Product Information Center +0120-81-0026 (in Japan) Fax: [phone] (in Japan)

DSP Hotline [phone] or (INTL) 813-3769-8735 Fax: [phone] or (INTL) 813-3457-7071
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- Documentation

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page: the full title of the book, the publication date, and the literature number.

Mail: Texas Instruments Incorporated Email: [e-mail]

Technical Documentation Services, MS 702
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Note: When calling a Literature Response Center to order documentation, please specify the literature number of the

book.

PRELIMINARY

+03-3457-0972 or (INTL) 813-3457-0972 Fax: [phone] or (INTL) 813-3457-1259

Read This First

vii

PRELIMINARY

viii

PRELIMINARY

Contents

Contents

1 Introduction 1Ć1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Discusses basic flash memory technology; summarizes the features and benefits of the
TMS320F20x/F24x flash module

1.1 Basic Concepts of Flash Memory Technology 1Ć2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2 TMS320F20x/F24x Flash Module 1Ć3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3 Benefits of Embedded Flash Memory in a DSP System 1Ć5. . . . . . . . . . . . . . . . . . . . . . . . . .

2 Flash Operations and Control Registers 2Ć1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Describes the operations that modify the content of the flash module; explains the role of the
control registers

2.1 Operations that Modify the Contents of the ’F20x/F24x Flash Array 2Ć2. . . . . . . . . . . . . . .

2.2 Accessing the Flash Module 2Ć5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.1 TMS320F206 Flash Access-Control Register 2Ć6. . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.2 TMS320F24x Flash Access-Control Register 2Ć7. . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3 Flash Module Control Registers 2Ć8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.1 Segment Control Register (SEG_CTR) 2Ć8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.2 Flash Test Register (TST) 2Ć10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.3 Write Address Register (WADRS) 2Ć10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.4 Write Data Register (WDATA) 2Ć11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4 Read Modes 2Ć12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5 Program Operation 2Ć13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6 Erase Operation 2Ć14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.7 Recovering From Over-Erasure (Flash-Write Operation) 2Ć15. . . . . . . . . . . . . . . . . . . . . . . .

2.8 Reading From the Flash Array 2Ć16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.9 Protecting the Array 2Ć16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3 Algorithm Implementations and Software Considerations 3

Describes the algorithms used for the programming, erase, and flash-write operations; dis­cusses considerations necessary for developing your software

3.1 How the Algorithms Fit Into the Program-Erase-Reprogram Flow 3Ć2. . . . . . . . . . . . . . . . .

3.2 Programming (or Clear) Algorithm 3Ć4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3 Erase Algorithm 3Ć10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.4 Flash-Write Algorithm 3Ć14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A Assembly Source Listings and Program Examples AĆ1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A.1 Assembly Source for Algorithms AĆ2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Ć1. . . . . . . . . . . . . . . . . . . . . . . . . .

ix

Contents

A.1.1 Header File for Constants and Variables, SVAR20.H AĆ2. . . . . . . . . . . . . . . . . . . . .

A.1.2 Clear Algorithm, SCLR20.ASM AĆ5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A.1.3 Erase Algorithm, SERA20.ASM AĆ10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A.1.4 Flash-Write Algorithm, SFLW20.ASM AĆ15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A.1.5 Programming Algorithm, SPGM20.ASM AĆ19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A.1.6 Subroutines Used By All Four Algorithms, SUTILS20.ASM AĆ25. . . . . . . . . . . . . . .

A.2 C-Callable Interface to Flash Algorithms AĆ27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A.3 Sample Assembly Code to Erase and Reprogram the TMS320F206 AĆ32. . . . . . . . . . . . . .

A.3.1 Assembly Code for TMS320F206 AĆ32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A.3.2 Linker Command File for TMS320F206 Sample Assembly Code AĆ35. . . . . . . . . .

A.4 Sample C Code to Erase and Reprogram the TMS320F206 AĆ37. . . . . . . . . . . . . . . . . . . . .

A.4.1 C Code That Calls the Interface to Flash Algorithms for TMS320F206 AĆ37. . . . .

A.4.2 Linker Command File for TMS320F206 Sample C Code AĆ38. . . . . . . . . . . . . . . . .

A.5 Sample Assembly Code to Erase and Reprogram the TMS320F240 AĆ40. . . . . . . . . . . . . .

A.5.1 Assembly Code for TMS320F240 AĆ40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A.5.2 Linker Command File for TMS320F240 Sample Assembly Code AĆ45. . . . . . . . . .

A.6 Using the Algorithms With C Code to Erase and Reprogram the ’F240 AĆ47. . . . . . . . . . . .

A.6.1 C Code That Calls the Interface to Flash Algorithms for TMS320F240 AĆ47. . . . .

A.6.2 Linker Command File for TMS320F240 Sample C Code AĆ48. . . . . . . . . . . . . . . . .

A.6.3 C Function for Disabling TMS320F240 Watchdog Timer AĆ50. . . . . . . . . . . . . . . . .

A.6.4 C Functions for Initializing the TMS320F240 AĆ51. . . . . . . . . . . . . . . . . . . . . . . . . . .

x

Figures

Figures

1–1 TMS320F20x/F24x Program Space Memory Maps 1Ć4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–1 Flash Memory Logic Levels During Programming and Erasing 2Ć4. . . . . . . . . . . . . . . . . . . . . .

2–2 Memory Maps in Register and Array Access Modes 2Ć6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–3 Segment Control Register (SEG_CTR) 2Ć8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–1 Algorithms in the Overall Flow 3Ć3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–2 The Programming Algorithm in the Overall Flow 3Ć4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–3 Programming or Clear Algorithm Flow 3-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–4 Erase Algorithm in the Overall Flow 3Ć10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–5 Erase Algorithm Flow 3Ć13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–6 Flash-Write Algorithm in the Overall Flow 3Ć14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–7 Flash-Write Algorithm Flow 3Ć16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contents

xi

Tables

Tables

1–1 TMS320 Devices With On-Chip Flash EEPROM 1Ć3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–1 Operations that Modify the Contents of the Flash Array 2Ć4. . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–2 Flash Module Control Registers 2Ć8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–3 Segment Control Register Field Descriptions 2Ć9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–4 Flash Array Segments Summary 2Ć10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–1 Steps for Verifying Programmed Bits and Applying One Program or Clear Pulse 3Ć8. . . . . .

3–2 Steps for Applying One Erase Pulse 3Ć11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–3 Steps for Applying One Flash-Write Pulse 3Ć15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

xii

PRELIMINARY

Chapter 1

Introduction

The TMS320F20x/F24x digital signal processors (DSPs) contain on-chip flash
EEPROM (electrically-erasable programmable read-only memory). The em­bedded flash memory provides an attractive alternative to masked program
ROM. Like ROM, flash memory is nonvolatile, but it has an advantage over

in-system

ROM:
This chapter discusses basic flash memory technology, introduces the flash

memory module of the ’F20x/F24x DSP , and lists the benefits of flash memory
embedded in a DSP chip.

reprogrammability.

Topic Page

1.1 Basic Concepts of Flash Memory Technology 1-2. . . . . . . . . . . . . . . . . . .

1.2 TMS320F20x/F24x Flash Module 1-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3 Benefits of Embedded Flash Memory in a DSP System 1-5. . . . . . . . . . .

PRELIMINARY

1-1

Basic Concepts of Flash Memory Technology

1.1 Basic Concepts of Flash Memory Technology

The term flash in this EEPROM technology refers to the speed of some of the
operations performed on the memory (these operations will be described in
greater detail later in this document). An entire block of bits is affected simulta-

block

or

neously in a
time. In contrast, writing data to the flash memory cannot be a block operation,
since normally a selection of ones and zeroes are written (all bits are not the
same value). Writing selected bits to create a desired pattern is known as pro­gramming the flash memory, and a written bit is called a programmed bit.

Several different types of program and erase operations are performed on the
flash memory in order to properly produce the desired pattern of ones and ze­roes in the memory. It should be noted that, under some conditions, flash
memory may become overerased, resulting in a condition known as depletion.
The ’F20x/F24x algorithms avoid overerasure by using an approach that
erases in small increments until complete erasure is achieved.

The ’F20x/F24x flash EEPROM includes a special operation, flash-write, that
is used only to recover from over-erasure. Because of the implementation of
the flash memory, when over-erasure occurs, any particular bit in depletion
mode is difficult to identify. For this reason, the ’F20x/F24x simply writes an
entire block of bits simultaneously; hence, the name flash-write.

flash operation

, rather than being affected one bit at a

PRELIMINARY

1-2

The program and erase operations in flash memory must provide sufficient
charge margin on 1s and 0s to ensure data retention, so the ’F20x/F24x flash
module includes a hardware mechanism that provides margin for erasing or
programming. This mechanism implements voltage reference levels which
ensure this logic level margin when modifying the contents of the flash
memory.

PRELIMINARY

PRELIMINARY

1.2 TMS320F20x/F24x Flash Module

The ’F20x/F24x flash EEPROM is implemented with one or two independent
flash memory modules of 8K or 16K words. Each flash module is composed
of a flash memory array , four control registers, and circuitry that produces ana­log voltages for programming and erasing. The flash array size of the
TMS320F206 and TMS320F240 is 16K × 16 bits, while the TMS320F241 and
TMS320F243 incorporate an 8K × 16-bit flash array (see Table 1–1). Unlike
most discrete flash memories, the ’F20x/F24x flash module does not require
a dedicated state machine, because the algorithms for programming and eras­ing the flash are executed in software by the DSP core. The use of these so­phisticated, adaptive programming algorithms results in reduced chip size and
greater programming flexibility . In addition, the application code can manage
the use of the flash memory without the requirement of external programming
equipment.

Table 1–1. TMS320 Devices With On-Chip Flash EEPROM

Device Array Size T otal Flash Memory

TMS320F20x/F24x Flash Module

TMS320F206 16K 32K
TMS320F240 16K 16K
TMS320F241 8K 8K
TMS320F243

†

Each array can be independently erased.

8K 8K

†

PRELIMINARY

Introduction

1-3

TMS320F20x/F24x Flash Module

Simplified memory maps for the program space of the TMS320F20x/F24x de­vices are shown in Figure 1–1 to illustrate the location of the flash modules.

Figure 1–1. TMS320F20x/F24x Program Space Memory Maps

PRELIMINARY

0000h

3FFFh

4000h

7FFFh

8000h

FFFFh

TMS320F206

MP/MC = 0

Flash0

Flash1

0000h

3FFFh

4000h

FFFFh

TMS320F240

MP/MC = 0

0000h

1FFFhFlash0

TMS320F241

Flash0

no external memory available

0000h

1FFFh

FFFFh

TMS320F243

MP/MC = 0

Flash0

1-4

PRELIMINARY

PRELIMINARY

Benefits of Embedded Flash Memory in a DSP System

1.3 Benefits of Embedded Flash Memory in a DSP System

The circuitry density of flash memory is about half that of conventional EE­PROM memory, making it possible to approach DRAM densities with flash
memory. This increased density allows flash memory to be integrated with a
CPU and other peripherals in a single ’F20x/F24x DSP chip. Embedded flash
memory expands the capabilities of the ’F20x/F24x DSPs in the areas of proto­typing, integrated solutions, and field upgradeable designs.

Embedded flash memory facilitates system development and early field test­ing. Throughout the development process, the system software can be up­dated and reprogrammed into the flash memory for testing at various stages.
Since flash is a non-volatile memory type, the resulting standalone prototype
can be tested in the appropriate environment without the need for battery
backup. In addition to its nonvolatile nature, embedded flash memory has the
advantage of in-system programming. Unlike some discrete flash or EEPROM
chips, embedded flash memory can be programmed without removing the de­vice from the system board. In fact, the embedded flash memory of ’F20x/F24x
DSPs can be programmed using hardware emulators which are already an in­tegral part of the DSP development process; no external programming equip­ment is required.

The embedded flash memory of ’F20x/F24x DSPs also makes these devices
ideal for highly integrated, low-cost systems. The initial investment involved
with making a ROM memory is not justifiable for certain low-cost applications.
Accordingly , when on-chip ROM is not an option, DSP system designers usu­ally resort to using expensive static RAM (SRAM), to store system software
and data. The SRAM provides the fast access times required by the DSP, but
has the disadvantage of being a volatile memory type. To address the issue
of memory volatility , designers often use a low-cost EPROM or flash device to
load the SRAM after system power-up. This approach is very expensive, and
the increased chip count is often prohibitive. The ’F20x/F24x DSPs, with their
on-chip flash memory modules, provide a single chip solution with nonvolatile
memory that supports full speed DSP access rates.

Another benefit of embedded flash memory in a DSP system is remote repro­grammability. Field upgradeability is an extremely useful feature for em­bedded systems. For example, many modem manufacturers offer algorithm
upgrades remotely , without requiring the modem to be removed from the host
computer system. The same type of feature is also being offered for many
handheld consumer products. Adding this capability to a product requires the
addition of EEPROM or flash devices, which increase chip count and system
cost. Since no external equipment is required to program the embedded flash
memory of the ’F20x/F24x DSPs, these devices enable field upgradeability
without impacting system cost.

PRELIMINARY

Introduction

1-5

PRELIMINARY

1-6

PRELIMINARY

PRELIMINARY

Flash Operations and Control Registers

Chapter 2

The operations that modify the contents of the ’F20x/F24x flash array are per­formed in software through the use of dedicated programming algorithms. This
chapter introduces the operations performed by these algorithms and explains
the role of the control registers in this process. The actual algorithms are dis­cussed in Chapter 3.

Topic Page

2.1 Operations that Modify the Contents of the ’F20x/F24x

Flash Array 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2 Accessing the Flash Module 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3 Flash Module Control Registers 2-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4 Read Modes 2-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5 Program Operation 2-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6 Erase Operation 2-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.7 Recovering From Over-Erasure (Flash-Write Operation) 2-15. . . . . . . . .

2.8 Reading From the Flash Array 2-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.9 Protecting the Array 2-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PRELIMINARY

2-1

Operations that Modify the Contents of the ’F20x/F24x Flash Array

PRELIMINARY

2.1 Operations that Modify the Contents of the ’F20x/F24x Flash Array

Operations that modify the contents of the flash array are generically referred
to as either “programming,” which drives one or more bits toward the logic zero
state, or “erasing,” which drives all bits towards the logic one state. It should
be noted that since these operations are performed incrementally, a single
“programming” or “erasing” operation does not ALW A YS result in a valid logic
one or zero. The result of each of these types of operations depends on the
initial state of the bit(s) prior to the operation. This is described in more detail
below.

Within these two basic types of operations (which are related to the fact that
there are only two valid logic levels in the F20x/F24x device) are four distinctly
different types of functions which are actually performed.

In the category of “programming” operations, there are three actual types of
functions that are performed:

 Clear – which is used to write ALL array bits to a zero state,
 Program – which is used to write SELECTED array bits to zero, and
 Flash-Write – which is used to recover ALL array bits from depletion

In the category of “erase” operations, there is only one type of operation:

 Erase – which is used to write ALL array bits to a one state.

Clear, Program, Flash-Write, and Erase are the only four functions that are
used to modify the flash array.

Assuming that the intent of a modification of the contents of the flash array is
to program the array with a selection of ones and zeroes, the following se­quence of operations must be performed for proper operation of the flash
memory:

1) The array is first CLEARED to all zeroes.

2) The array is then ERASED to all ones.

3) The array is then checked for depletion and recovered using FLASH­WRITE if necessary (note that if Flash-Write is used to recover from deple­tion, this sequence must be started over again with the Clear and Erase
functions).

4) Once the array is properly cleared and erased, and verified not to be in
depletion, the array is then PROGRAMMED with the desired selection of
zero bits.

2-2

PRELIMINARY

PRELIMINARY

Operations that Modify the Contents of the ’F20x/F24x Flash Array

This procedure is discussed in complete detail in Chapter 3.
During these operations that are used to modify the contents of the flash array ,

three special read modes, and a corresponding set of reference voltage levels,
are used when reading back data values to verify programming and erase op­erations.

These read modes and reference levels are:

 VER0 – which is used to verify the logic zero level including margin,
 VER1 – which is used to verify the logic one level including margin, and
 Inverse Erase – which is used to verify depletion recovery.

These concepts are illustrated graphically in Figure 2–1 and summarized in
Table 2–1.

Note that ONL Y the Erase and the Flash-Write functions are truly “flash” in the
sense that these functions actually affect all bits in the array simultaneously.
In contrast, bit programming levels in the Program and Clear functions can be
controlled individually on a bit-by-bit basis.

Therefore, when using the Erase or Flash-Write functions, the whole array is
modified, and then the whole array is read, word by word, to verify whether all
words have reached the same value (if not, further iterations of the Erase or
Flash-Write functions continue).

In these cases, as mentioned previously , all the bits in the array are modified
simultaneously , but some bits may react more quickly, potentially resulting in
variation in actual levels on different bits. Therefore, when performing an
Erase, it is possible that some bits may reach depletion even before other bits
reach the logic one reference level (VER1).

The reason that it is critical to clear the array to a consistent zero level before
erasing the array is to give maximum immunity to depletion when erasing.
Note, however, that even when following this sequence, some flash arrays
may experience depletion, and may require recovery using the Flash-Write
function.

In contrast to the true “flash” operations Erase and Flash-Write, after each in­cremental Program or Clear operation, each bit is tested against the VER0 ref­erence level to determine the exact point at which it has reached the proper
value, following which, no further incremental adjustment of the level is made
on that bit. Therefore, when the Program or Clear operation is complete, all bits
are at the same zero level, which greatly increases proper data retention and
depletion immunity for the device. Again, note that the programming and erase
operations are discussed in complete detail in Chapter 3.

PRELIMINARY

Flash Operations and Control Registers

2-3

Operations that Modify the Contents of the ’F20x/F24x Flash Array

Figure 2–1. Flash Memory Logic Levels During Programming and Erasing

Depletion Mode

Inverse Erase
Reference Level

Logic 1

Program operations

Clear



Program



Flash Write



(Towards logic

zero level)

Erase



(Towards logic

one level)

Erase operation

VER1
Reference Level

1 Margin

PRELIMINARY

0 Margin

VER0

Reference
level

Logic 0

Table 2–1. Operations that Modify the Contents of the Flash Array

Change in Bit Level

Towards Logic 1 Towards Logic 0

Function Reference

Level

Erase (all bits) VER1

Function Reference

Program (selected bits) VER0
Clear (all bits) VER0
Flash-Write (all bits) Inverse Erase

Level

2-4

PRELIMINARY

PRELIMINARY

2.2 Accessing the Flash Module

In addition to the flash memory array , each flash module has four registers that
control operations on the flash array. These registers are:

 Segment control register (SEG_CTR)
 Test register (TST)
 Write address register (WADRS)
 Write data register (WDATA)

The flash module operates in one of two modes: one in which the flash memory
is accessed directly by the CPU, and one in which the memory array cannot
be accessed directly , but the four control registers are accessible. This mode
is used for programming. Each flash module has a flash access-control regis­ter that selects between these two access modes. The register is a single-bit,
I/O-mapped register.

The two access modes are summarized as follows:

Accessing the Flash Module

 Array-access mode. Y ou can access the flash array in the memory space

decoded for the flash module. The flash module remains in this mode most
of the time, because it allows the DSP core to read from the memory array .

 Register-access mode. You can access the four control registers in the

memory space decoded for the flash module. This mode is used for pro­gramming. When the flash module is in register-access mode, the regis­ters are repeated every four address locations within the flash module’s
address range.

The flash array is not directly accessible as memory in register-access mode,
and the control registers are not directly accessible in array-access mode.

Figure 2–2 shows memory maps of the flash array in register and array access
modes.

PRELIMINARY

Flash Operations and Control Registers

2-5

Accessing the Flash Module

Figure 2–2. Memory Maps in Register and Array Access Modes

Flash access control register

(single bit)

MODE = 1: Array-access mode
MODE = 0: Register access mode

PRELIMINARY

0100 ... 010
0100 ... 01 1

Flash memory

array

1 110 ...110
01 10 ...111

2.2.1 TMS320F206 Flash Access-Control Register

Because each flash module has an access-control register associated with it,
the ’F206 has two access-control registers. These registers are standard I/O­mapped registers that can be read with an IN instruction and must be modified
with an OUT instruction.

SEG_CTR register

TST register

WADRS register

WDATA register

4 registers duplicated

4 registers duplicated

4 registers duplicated

2-6

 F_ACCESS0 is mapped in I/O space at 0FFE0h.
 F_ACCESS1 is mapped in I/O space at 0FFE1h.

The MODE bit (bit 0) of the access-control register selects the access mode:

MODE = 0 Register-access mode
MODE = 1 Array-access mode

Bits 15–1 of each access-control register are always read as 0 and are unaf­fected by writes.

PRELIMINARY

PRELIMINARY

Although the function is the same, the access control registers of the ’F206 de­vice are mapped at different addresses from that of the ’F24x devices, and
their values are modified in a different way.

2.2.2 TMS320F24x Flash Access-Control Register

The access-control register of the ’F24x devices is a special type of I/O­mapped register that cannot be read. The register is mapped at I/O address
0FF0Fh, and it functions as indicated below.

Note:

For both the IN and OUT instructions, the data operand (dummy) is not used,
and can be any valid memory location.

An OUT instruction using the register address as an I/O port places the flash
module in register-access mode.

For example:

OUT dummy, 0FF0Fh ;Selects register-access mode

Accessing the Flash Module

An IN instruction using the register address as an I/O port places the flash
module in array-access mode.

The data operand (dummy) is not used, and can be any valid memory location.
For example:

IN dummy, 0FF0Fh;Selects array-access mode

PRELIMINARY

Flash Operations and Control Registers

2-7

Flash Module Control Registers

Relati

Regi

2.3 Flash Module Control Registers

T able 2–2 lists the control registers and their relative addresses within the four
locations that repeat throughout the module’s address range.

Table 2–2. Flash Module Control Registers

PRELIMINARY

ve

Address

0 SEG_CTR Segment control register. The eight MSBs enable spe-

1 TST Test register. Reserved for test; not accessible to the

2 WADRS Write address register. Holds the address for a write

3

ster

Name

WDATA Write data register . Holds the data for a write operation. 2.3.4 2-8

Description

cific segments for programming. Setting a bit to 1 en­ables the segment. The eight LSBs control the pro­gram, erase, and verify operations of the module.

user.

operation.

2.3.1 Segment Control Register (SEG_CTR)

SEG_CTR is a 16-bit register that initiates and monitors the programming and
erasing of the flash array . This register contains the bits that initiate the active
operations (the WRITE/ERASE field and EXE bit), those used for verification
(VER0 and VER1), and those used for protection (KEY0, KEY1, and
SEG7–SEG0). All bits of SEG_CTR register are cleared to 0 upon reset.

Described in ...

Section

2.3.1 2-5

2.3.2 2-8

2.3.3 2-8

Page

SEG_CTR is shown in Figure 2–3 and the fields are described in Table 2–3.

Figure 2–3. Segment Control Register (SEG_CTR)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 Res KEY1 KEY0 VER0 VER1

RW–0 RW–0 RW–0 RW–0 RW–0 RW–0 RW–0 RW–0 X RW–0 RW–0 RW–0 RW–0 RW–0 RW–0

Legend: R = read

2-8

W = write
–0 = value after reset
X = don’t care

WRITE/
ERASE

PRELIMINARY

EXE

PRELIMINARY

Flash Module Control Registers

Table 2–3. Segment Control Register Field Descriptions

Bits Name Description

15–8 SEG7–SEG0 Segment enable bits. Each of these bits protects the specified segment against pro-

gramming or enables programming for the specified segment in the array . Any number
of segments (from 0 to 7 in any combination) can be enabled at any one time. See
T able 2–4 for segment address ranges. EXE must be cleared to modify the SEGx bits.

SEGx = 1 enables programming of the corresponding segment.

SEGx = 0 protects the segment from programming.
7 Reserved This bit is not affected by writes, and reads of this bit are undefined.
6–5 KEY1, KEY0 Execute key bits. A binary value of 10 must be written to these bits in the same DSP

core access in which the EXE bit is set for the selected operation (erase, program, or

flash-write) to start. KEY1 and KEY0 must be cleared in the same write access that

clears EXE. These bits are used as additional protection against inadvertent program-

ming or erasure of the array. These bits are read as 0s.
4–3 VER0, VER1 Verify bits. These bits select special read modes used to verify proper erasure or pro-

gramming.

Possible values:

00: Normal read mode

01: Verify 1s (VER1) read mode to verify margin of 1s for proper erasure

10: Verify 0s (VER0) read mode to verify margin of 0s for proper programming

1 1: Inverse-read mode; tests for bits erased into depletion
2–1 WRITE/ERASE Write/erase enable field. These bits select the program, erase, or flash-write operation.

However, modification of the array data does not actually start until the EXE bit is set.

Reset clears these bits to zero.

Possible values:

00: Read operation is enabled. These bit values are required to read the array.

01: Erase operation is enabled

10: Write operation is enabled

1 1: Flash-write operation is enabled
0

EXE Execute bit. In conjunction with WRITE/ERASE, KEY1, and KEY0, this bit controls the

program, erase, and flash-write operations. Setting EXE starts and stops program-

ming and erasing of the flash array. The KEY1 and KEY0 bits must be written in the

same write access that sets EXE, and EXE must be cleared in the same write access

that clears KEY1 and KEY0. EXE must be cleared to modify the SEGx bits.

Note: The segment enable bits are not intended for protection during the erase or flash-write operations. During these opera-

PRELIMINARY

all

segments must be enabled.

tions,

Flash Operations and Control Registers

2-9

Flash Module Control Registers

3

Segme

F241/F243

Array Segment

Table 2–4. Flash Array Segments Summary

PRELIMINARY

SEG7–SEG0 Bits ’F206/F240 Flash Module

15 14 13 12 11 10 9 8 Flash0 Flash1

0 0 0 0 0 0 1 0000–07FFh 4000–47FFh 0000–03FFh 0

0
000000100800–0FFFh 4800–4FFFh 0400–07FFh 1
000001001000–17FFh 5000–57FFh 0800–0BFFh 2
000010001800–1FFFh 5800–5FFFh 0C00–0FFFh 3
000100002000–27FFh 6000–67FFh 1000–13FFh 4
001000002800–2FFFh 6800–6FFFh 1400–17FFh 5
010000003000–37FFh 7000–77FFh 1800–1BFFh 6

0 0 0 0 0 0 0 3800–3FFFh 7800–7FFFh 1C00–1FFFh 7

1

†

The TMS320F206 has two flash modules. The TMS320F240 device uses the address ranges shown for Flash0.

†

’F241/F24

Flash Module

Array

Although segmentation is not supported during erase (i.e., the entire array
must be erased simultaneously), the segment enable bits can be used to pro­tect portions of the array against unintentional programming. This is useful for
applications in which different portions of the array are programmed at differ­ent times. For example, an application might program the flash module with
a large table in 2K × 16 blocks. Some time after the first block is programmed,
the next block is programmed. The segment enable bits can be used to prevent
corruption of the first block while the second block is being programmed.

nt

Enabled

2.3.2 Flash Test Register (TST)

The flash test register (TST) is a 5-bit register used during manufacturing test
of the flash array. This register is not accessible to the DSP core.

2.3.3 Write Address Register (WADRS)

The write address register (WADRS) is a 16-bit register that holds the latched
write address for a programming operation. In array-access mode, this regis­ter is loaded with the value on the address bus when you are writing a data
value to the flash module. It can be loaded directly in register-access mode by
writing to it.

2-10

PRELIMINARY

PRELIMINARY

2.3.4 Write Data Register (WDATA)

The write data register (WDA TA) is a 16-bit register that contains the latched
write data for a programming operation. In array-access mode, this register
can be loaded by writing a data value to the flash module. It can be loaded di­rectly in register-access mode by writing to it. The WDATA register must be
loaded with the value FFFFh before an erase operation starts.

Flash Module Control Registers

PRELIMINARY

Flash Operations and Control Registers

2-11

Read Modes

2.4 Read Modes

PRELIMINARY

The ’F20x/F24x flash module uses four read modes and corresponding sets
of reference levels:

 Standard
 Verify 0s (VER0)
 Verify 1s (VER1)
 Inverse-erase

Read mode selection is accomplished through the verify bits (bits 3 and 4) in
SEG_CTR during execution of the algorithms.

In the standard read mode of the ’F20x/F24x flash module, the supply voltage
(VDD) is internally applied to the cell to select it for reading. The VER0, VER1,
and inverse-erase read modes differ from the standard read mode in the inter­nal voltage level applied to the flash cell.

Because the program and erase operations must provide sufficient margin on
1s and 0s to ensure data retention, the verify 0s (VER0) and verify 1s (VER1),
are provided on the flash module to check for sufficient margin.

The VER0 and VER1 read modes provide a method for adjusting the level on
the cells during programming or erasing, beyond the point required for reading
a 0 or a 1, creating the required logic level margin. In VER0 mode, a voltage
closer to an ideal logic zero level than necessary to read a logic zero is internal­ly applied to the cell to select it for reading. This is the worst-case condition for
reading a programmed cell, and if a cell can be read as 0 in VER0 mode, then
it can also be read as 0 in standard read mode. Similarly, in the VER1 read
mode, a voltage closer to an ideal logic one level than necessary to read a logic
one is internally applied to the cell to select it for reading. This is the worst-case
condition for reading an erased cell, and if a cell can be read as 1 in the VER1
mode, then it can be read as 1 in standard read mode.

The inverse-erase read mode detects flash bits that are in depletion mode.
This read mode applies a voltage to all array cells so that all cells are dese­lected. The entire array can be tested for bits in depletion mode by reading the
first row (32 words) of the array in inverse-erase read mode. If there are no bits
in depletion mode, all 32 words are read as 0000h.

2-12

PRELIMINARY