Texas Instruments TMDS 351 INSTALLATION INSTRUCTIONS

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STB

DigitalTV

DVDPlayer

Game

Console

TMDS351

3-to-1

PHY SX

2.5 Gbps 3-TO-1 DVI/HDMI SWITCH

TMDS351

SLLS840 – MAY 2007

FEATURES

• Compatible with HDMI 1.3a

• Supports 2.5 Gbps Signaling Rate for 480i/p,

• HBM ESD Protection Exceeds 8 kV to TMDS

Inputs

• 3.3-V Fixed Supply to TMDS I/Os

720i/p, and 1080i/p Resolutions up to 12-Bit • 5-V Fixed Supply to HPD, DDC, and Source
Color Depth Selection Circuits

• Integrated Receiver Termination • 64-Pin TQFP Package

• Selectable Receiver Equalization to • ROHS Compatible and 260 ° C Reflow Rated

Accommodate to Different Input Cable
Lengths

• Intra-Pair Skew < 40 ps

• Inter-Pair Skew < 65 ps

APPLICATIONS

• Digital TV

• Digital Projector

DESCRIPTION

The TMDS351 is a 3-port digital video interface (DVI) or high-definition multimedia interface (HDMI) switch that
allows up to 3 DVI or HDMI ports to be switched to a single display terminal. Four TMDS channels, one hot plug
detector, and a digital display control (DDC) interface are supported on each port. Each TMDS channel supports
signaling rates up to 2.5 Gbps to allow 1080p resolution in 12-bit color depth.

When S1 is high and S2 is low, all input terminations are disconnected, TMDS inputs are high impedance with
standard TMDS terminations, all internal MOSFETs are turned off to disable the DDC links, and all HPD outputs
are connected to the HPD_SINK. This allows the initiation of the HDMI physical address discovery process.

Termination resistors (50- Ω ), pulled up to V
are not required. A precision resistor is connected externally from the VSADJ pin to ground for setting the
differential output voltage to be compliant with the TMDS standard.

The TMDS351 provides two levels of receiver input equalization for different ranges of cable lengths. Each
TMDS receiver owns frequency responsive equalization circuits. When EQ sets low, the receiver supports the
input connection in short range HDMI cables. When EQ sets high, the receiver supports the input connection in
long range HDMI cables. The TMDS351 supports power saving operation. When a system is under standby
mode and there is no digital audio/visual content from a connected source, the 3.3-V supply voltage, V
be powered off to minimize power consumption from the TMDS inputs, outputs, and internal switching circuits.
The HPD, DDC, and source selection circuits are powered up by the 5-V supply voltage, V
system hot plug detect response, the DDC link from the selected source to the sink under system standby
operation. The device is characterized for operation from 0 ° C to 70 ° C.

, are integrated at each TMDS receiver input. External terminations

CC

, to maintain the

DD

CC

, can

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Typical Application

Copyright © 2007, Texas Instruments Incorporated

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SCL_SINK
SDA_SINK

HPD_SINK

S1

S2

.

.

.

.

.

.

.

.

.

Control

Logic

Y4

Z4

VSADJ

TMDS
Driver

TMDS
Driver

TMDS
Driver

TMDS
Driver

EQ

V

DD

Vcc

R

INT

TMDS

Rx

R

INT

Vcc

R

INT

TMDS

Rx

R

INT

Vcc

R

INT

TMDS

Rx

R

INT

Vcc

R

INT

TMDS

Rx

R

INT

Vcc

R

INT

TMDS

Rx

R

INT

Vcc

R

INT

TMDS

Rx

R

INT

Vcc

R

INT

TMDS

Rx

R

INT

Vcc

R

INT

TMDS

Rx

R

INT

Vc c

R
INT

TMDS

Rx

R
INT

Vc c

R
INT

TMDS

Rx

R
INT

Vc c

R
INT

TMDS

Rx

R
INT

Vc c

R
INT

TMDS

Rx

R
INT

B11

A1
1

B12

A12

B13

A13

B14

A14

A24

B24

A23

B23

A22

B22

A21

B21

A34

B34

A33

B33

A32

B32

A31

B31

HPD1

HPD2

HPD3

SCL1

SDA1

SCL2

SDA2

SCL3

SDA3

Y3

Z3

Y1

Z1

Y2

Z2

HPD/DDC

PowerSupply

TMDS351

SLLS840 – MAY 2007

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

FUNCTIONAL BLOCK DIAGRAM

2

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1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

TMDS351

64-pin TQFP

SDA3

SCL3

GND

B31
A31

Vcc
B32
A32

GND

B33
A33

Vcc
B34
A34

GND

VSADJ

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

Y4

Z4

Vcc

Y3

Z3

GND

Y2

Z2

Vcc

Y1

Z1

GND

SCL_SINK

SDA_SINK

HPD_SINK

S1

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

A14
B14
Vcc
A13
B13
GND
A12
B12
Vcc
A11
B11
SCL1
SDA1
HPD1
EQ
S2

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

HPD3

A24

B24

Vcc

A23

B23

GND

A22

B22

Vcc

A21

B21

SCL2

SDA2

HPD2

VDD

TMDS351

SLLS840 – MAY 2007

PFC PACKAGE

(TOP VIEW)

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TMDS351

SLLS840 – MAY 2007

TERMINAL FUNCTIONS

TERMINAL

NAME NO.

A11, A12, A13, A14 39, 42, 45, 48 I Source port 1 TMDS positive inputs
A21, A22, A23, A24 54, 57, 60, 63 I Source port 2 TMDS positive inputs
A31, A32, A33, A34 5, 8, 11, 14 I Source port 3 TMDS positive inputs
B11, B12, B13, B14 38, 41, 44, 47 I Source port 1 TMDS negative inputs
B21, B22, B23, B24 53, 56, 59, 62 I Source port 2 TMDS negative inputs
B31, B32, B33, B34 4, 7, 10, 13 I Source port 3 TMDS negative inputs

GND Ground

EQ 34 I EQ = Low – HDMI 1.3 compliant cable

HPD1 35 O Source port 1 hot plug detector output (status pin)
HPD2 50 O Source port 2 hot plug detector output (status pin)
HPD3 64 O Source port 3 hot plug detector output (status pin)
HPD_SINK 31 I Sink port hot plug detector input (status pin)
SCL1 37 I/O Source port 1 DDC I2C clock line
SCL2 52 I/O Source port 2 DDC I2C clock line
SCL3 2 I/O Source port 3 DDC I2C clock line
SCL_SINK 29 I/O Sink port DDC I2C clock line
SDA1 36 I/O Source port 1 DDC I2C data line
SDA2 51 I/O Source port 2 DDC I2C data line
SDA3 1 I/O Source port 3 DDC I2C data line
SDA_SINK 30 I/O Sink port DDC I2C data line
S1, S2 32. 33 I Source selector

V

CC

V

DD

VSADJ 16 I TMDS compliant voltage swing control (control pin)
Y1, Y2, Y3, Y4 26,23,20,17 O Sink port TMDS positive outputs
Z1, Z2, Z3, Z4 27,24,21,18 O Sink port TMDS negative outputs

3, 9, 15, 22, 28,

43, 58

6, 12, 19, 25, 40,

46, 55, 61

49 HPD/DDC Power supply

I/O DESCRIPTION

TMDS Input equalization selector (control pin)
EQ = High – 10m 28 AWG HDMI cable

Power supply

4

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Table 1. Source Selection Lookup

CONTROL PINS I/O SELECTED HOT PLUG DETECT STATUS
S1 S2 Y/Z HPD1 HPD2 HPD3

A1/B1 SCL1

H H HPD_SINK L L

H L L HPD_SINK L

L L L L HPD_SINK

L H None (Z) None (Z) HPD_SINK HPD_SINK HPD_SINK

(1) H: Logic high; L: Logic low; X: Don't care; Z: High impedance

Terminations of A2/B2 SDA1

and A3/B3 are

disconnected

A2/B2 SCL2

Terminations of A1/B1 SDA2

and A3/B3 are

disconnected

A3/B3 SCL3

Terminations of A1/B1 SDA3

and A2/B2 are

disconnected

All terminations are Are pulled HIGH by

disconnected external pull-up

SCL_SINK

SDA_SINK

termination

(1)

TMDS351

SLLS840 – MAY 2007

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TMDSInputStage

A B

V

CC

50 W

Z

TMDSOutputStage

Y

10mA

StatusandSourceSelector

HPD_SINK

S1
S2

V

DD

ControlInputStage

EQ

V

CC

SCL/SCA

Source

DDCpassgate

HPDoutputstage

HPD1
HPD2
HPD3

V

DD

50 W

V

DD

SCL/SCA

Sink

V

CC

TMDS351

SLLS840 – MAY 2007

EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS

6

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TMDS351

SLLS840 – MAY 2007

ORDERING INFORMATION

PART NUMBER PART MARKING PACKAGE

TMDS351PAG TMDS351 64-PIN TQFP

TMDS351PAGR TMDS351 64-PIN TQFP Tape/Reel

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

Supply voltage V

(2)

range

Voltage range Ym, Zm, VSADJ, EQ –0.5V to 4 V

Electrostatic
discharge

Continuous power dissipation

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
(3) n = 1, 2, 3; m = 1, 2, 3, 4
(4) Tested in accordance with JEDEC Standard 22, Test Method A114-B
(5) Tested in accordance with JEDEC Standard 22, Test Method C101-A
(6) Tested in accordance with JEDEC Standard 22, Test Method A115-A

CC

V

DD

(3)

Anm

, Bnm 2.5 V to 4 V

SCLn, SCL_SINK, SDAn, SDA_SINK, HPDn, HPD_SINK, S1, S2 –0.5 V to 6 V

Human body model

Charged-device model
Machine model

(4)

(5)

(all pins) ± 1500 V

(6)

(all pins) ± 200 V

(1)

Anm, Bnm ± 8000 V
All pins ± 4000 V

(1)

UNIT

–0.5 V to 4 V
–0.5 V to 6 V

See Dissipation Rating

Table

DISSIPATION RATINGS

PACKAGE TA≤ 25 ° C

64-TQFP PAG

PCB JEDEC DERATING FACTOR
STANDARD ABOVE TA= 25 ° C POWER RATING

Low-K 1111 mW 11.19 mW/ ° C 611 mW

High-K 1492 mW 14.92 820 mW

(1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.

(1)

THERMAL CHARACTERISTICS

over operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX

R

Junction-to-board thermal

θ JB

resistance

R

Junction- to-case thermal

θ JC

resistance

P

Device power dissipation Am/Bm(2:4) = 2.5-Gbps HDMI data pattern, 590 750 mW

D

Am/Bm(1) = 250-MHz clock

(1) The maximum rating is simulation under 3.6-V VCC, 5.5-V VDD, and 600 mV VID.

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VIH= VCC, VIL= V

- 0.6 V, RT= 50 Ω , AV

CC

= 3.3V,

CC

TA= 70 ° C

(1)

33.4 ° C/W

15.6 ° C/W

UNIT

7

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TMDS351

SLLS840 – MAY 2007

RECOMMENDED OPERATING CONDITIONS

V

CC

V

DD

T

A

TMDS DIFFERENTIAL PINS

V

IC

V

ID

R

VSADJ

AV

CC

R

T

CONTROL PINS

V

IH

V

IL

DDC I/O PINS

V

I(DDC)

STATUS and SOURCE SELECTOR PINS

V

IH

V

IL

Supply voltage 3 3.3 3.6 V
Standby supply voltage 4.5 5 5.5 V
Operating free-air temperature 0 70 ° C

Input common mode voltage VCC–0.4 VCC+0.01 V
Receiver peak-to-peak differential input voltage 150 1560 mVp-p
Resistor for TMDS compliant voltage swing range 3.66 4.02 4.47 k Ω
TMDS output termination voltage, see Figure 1 3 3.3 3.6 V
Termination resistance, see Figure 1 45 50 55 Ω
Signaling rate 0 2.5 Gbps

LVTTL High-level input voltage 2 V
LVTTL Low-level input voltage GND 0.8 V

DDC Input voltage GND V

LVTTL High-level input voltage 2 V
LVTTL Low-level input voltage GND 0.8 V

MIN NOM MAX UNIT

V

CC

V

DD

V

DD

ELECTRICAL CHARACTERISTICS

over recommended operating conditions (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP

VIH= VCC, VIL= VCC– 0.6 V, S1/S2 =
RT= 50 Ω , AV

I

CC

I

DD

Supply current mA

Power supply current, 5-V 2 5 mA

TMDS DIFFERENTIAL PINS

V

OH

V

OL

V

swing

V

OD(O)

V

OD(U)

∆ V
I

(OS)

V

I(open)

R

Single-ended high-level output voltage AV
Single-ended low-level output voltage AV
Single-ended output swing voltage 400 600 mV
Overshoot of output differential voltage 15% 2 × V
Undershoot of output differential voltage 25% 2 × V
Change in steady-state common-mode

OC(SS)

output voltage between logic states
Short circuit output current See Figure 3 -12 12 mA
Single-ended input voltage under high

impedance input or open input
Input termination resistance VIN= 2.9 V 45 50 55 Ω

INT

CONTROL PINS

I

IH

I

IL

High-level digital input current
Low-level digital input current

DDC I/O PINS

I

lkg

C

Input leakage current VI= 0.1 VDDto 0.9 VDDto isolated DDC inputs -10 10 µA
Input/output capacitance V

IO

(2)

(2)

Am/Bm(2:4) = 2.5 Gbps HDMI data Low/High,
pattern High/High
Am/Bm(1) = 250 MHz clock

VIH= VCC, VIL= VCC– 0.6 V,
RT= 50 Ω , AV
Am/Bm(2:4) = 2.5 Gbps HDMI data pattern
Am/Bm(1) = 250 MHz clock

See Figure 2 , AV
RT= 50 Ω

II= 10 µA VCC–10 VCC+10 mV

VIH= 2 V or V
VIL= GND or 0.8 V -10 10 µA

= 1 V, 100 kHz 10 pF

I(pp)

= 3.3 V Low/Low,

CC

= 3.3 V

CC

= 3.3 V,

CC

CC

S1/S2 =
High/Low

(1)

176 200

8 20

–10 AV

CC

–600 AV

CC

CC

-10 10 µA

MAX UNIT

+10 mV

CC

–400 mV

swing
swing

5 mV

(1) All typical values are at 25 ° C and with a 3.3-V supply.
(2) IIHand IILspecifications are not applicable to the VSADJ pin.

8

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