TEXAS INSTRUMENTS TLV571 Technical data

TLV571

2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,

PARALLEL ANALOG-TO-DIGITAL CONVERTER

SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000

features

D

Fast Throughput Rate: 1.25 MSPS at 5 V,

625 KSPS at 3 V

D

Wide Analog Input: 0 V to AV

D

Differential Nonlinearity Error: < ± 0.5 LSB

D

Integral Nonlinearity Error: < ± 0.5 LSB

D

Single 2.7-V to 5.5-V Supply Operation

D

Low Power: 12 mW at 3 V and 35 mW at 5 V

D

Auto Power Down of 1 mA Max

D

Software Power Down: 10 µA Max

D

Internal OSC

D

Hardware Configurable

D

DSP and Microcontroller Compatible

DD

Parallel Interface

D

Binary/Twos Complement Output

D

Hardware Controlled Extended Sampling

D

Hardware or Software Start of Conversion

description

The TLV571 is an 8-bit data acquisition system

applications

D

Mass Storage and HDD

D

Automotive

D

Digital Servos

D

Process Control

D

General-Purpose DSP

D

Image Sensor Processing

DW OR PW PACKAGE

(TOP VIEW)

CS

WR

RD

CLK

DGND

DV

DD

INT/EOC

DGND
DGND

D0
D1
D2

NC – No internal connection

1
2
3
4
5
6
7
8
9
10
11
12

24
23
22
21
20
19
18
17
16
15
14
13

NC
AIN
AV
AGND
REFM
REFP
CSTART
A1/D7
A0/D6
D5
D4
D3

that combines a high-speed 8-bit ADC and a
parallel interface. The device contains two on-chip control registers allowing control of software conversion start
and power down via the bidirectional parallel port. The control registers can be set to a default mode using a
dummy RD

while WR is tied low allowing the registers to be hardware configurable.

DD

The TL V571 operates from a single 2.7-V to 5.5-V power supply. It accepts an analog input range from 0 V to
AVDD and digitizes the input at a maximum 1.25 MSPS throughput rate at 5 V . The power dissipations are only
12 mW with a 3-V supply or 35 mW with a 5-V supply. The device features an auto power-down mode that
automatically powers down to 1 mA 50 ns after conversion is performed. In software power-down mode, the
ADC is further powered down to only 10 µA.

Very high throughput rate, simple parallel interface, and low power consumption make the TLV571 an ideal
choice for high-speed digital signal processing.

AVAILABLE OPTIONS

PACKAGE

T

A

–40°C to 85°C TLV571IPW TLV571IDW

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

24 TSSOP

(PW)

24 SOIC

(DW)

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  2000, Texas Instruments Incorporated

1

TLV571

I/O

DESCRIPTION

2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTER

SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000

functional block diagram

CLK

CS
RD

WR

CSTART

Internal

Clock

MUX

AV

DD

AIN

Input Registers

and Control Logic

REFP

8-BIT

SAR ADC

REFM DV

Three

State

Latch

DGNDAGND

DD

D0 – D5

D6/A0
D7/A1

INT/EOC

Terminal Functions

TERMINAL

NAME NO.

AGND 21 Analog ground
AIN 23 I ADC analog input
AV

DD

A0/D6 16 I/O Bidirectional 3-state data bus. D6/A0 along with D7/A1 is used as address lines to access CR0 and CR1 for

A1/D7 17 I/O Bidirectional 3-state data bus. D7/A1 along with D6/A0 is used as address lines to access CR0 and CR1 for

CLK 4 I External clock input
CS 1 I Chip select. A logic low on CS enables the TLV571.
CSTAR T 18 I Hardware sample and conversion start input. The falling edge of CSTAR T starts sampling and the rising edge

DGND 5, 8, 9 Digital ground
DV

DD

D0 – D5 10–15 I/O Bidirectional 3-state data bus
INT/EOC

NC 24 Not connected
RD

REFM 20 I Lower reference voltage (nominally ground). REFM must be supplied or REFM pin must be grounded.
REFP 19 I Upper reference voltage (nominally AVDD). The maximum input voltage range is determined by the difference

WR

22 Analog supply voltage, 2.7 V to 5.5 V

initialization.

initialization.

of CSTART

6 Digital supply voltage, 2.7 V to 5.5 V

7 O End-of-conversion/interrupt

3 I Read data. A falling edge on RD enables a read operation on the data bus when CS is low.

between the voltage applied to REFP and REFM.

2 I Write data. A rising edge on the WR latches in configuration data when CS is low. When using software

conversion start, a rising edge on WR
the ADC in nonprogrammable (hardware configuration mode).

starts conversion.

also initiates an internal sampling start pulse. When WR is tied to ground,

2

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detailed description

analog-to-digital SAR converter

Ain

TLV571

2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,

PARALLEL ANALOG-TO-DIGITAL CONVERTER

SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000

Charge

Redistribution

DAC

_
+

REFM

SAR

Register

Control

Logic

ADC Code

Figure 1

The TLV571 is a successive-approximation ADC utilizing a charge redistribution DAC. Figure 1 shows a
simplified version of the ADC.

The sampling capacitor acquires the signal on Ain during the sampling period. When the conversion process
starts, the SAR control logic and charge redistribution DAC are used to add and subtract fixed amounts of charge
from the sampling capacitor to bring the comparator into a balanced condition. When the comparator is
balanced, the conversion is complete and the ADC output code is generated.

sampling frequency, f

s

The TLV571 requires 16 CLKs for each conversion, therefore the equivalent maximum sampling frequency
achievable with a given CLK frequency is:

f

s(max)

= (1/16) f

CLK

The TL V571 is software configurable. The first two MSB bits, D(7,6) are used to address which register to set.
The remaining six bits are used as control data bits. There are two control registers, CR0 and CR1, that are user
configurable. All of the register bits are written to the control register during write cycles. A description of the
control registers is shown in Figure 2.

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3

TLV571

2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTER

SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000

detailed description (continued)

control registers

A1 A0 D4 D3 D2 D1 D0D5

Control Register Zero (CR0)

A(1:0)=00

STARTSEL

D4D5 D3 D2 D1 D0

PROGEOC

CLKSEL SWPWDN Don’t Care

Don’t Care

0:
HARDWARE
START
(CSTART)

1:
SOFTWARE
START

Control Register One (CR1)

A(1:0)=01

Reserved

0:
Reserved
Bit
Always
Write 0

hardware configuration option

0:
INT

1:
EOC

D4D5 D1 D0

OSCSPD 0 Reserved 0 Reserved OUTCODE Reserved

0:
INT. OSC.
SLOW
1:
INT. OSC.
FAST

0:
Internal
Clock

1:
External
Clock

0:
Reserved
Bit
Always
Write 0

0:
NORMAL

1:
Powerdown

D3 D2

0:
Reserved
Bit,
Always
Write 0

Don’t Care

0:
Binary

1:
2’s
Complement

Don’t Care

0:
Reserved
Bit,
Always
Write 0

Figure 2. Input Data Format

The TLV571 can configure itself. This option is enabled when the WR

pin is tied to ground and a dummy RD
signal is applied. The ADC is now fully configured. Zeros or default values are applied to both control registers.
The ADC is configured ideally for 3-V operation, which means the internal OSC is set at 10 MHz and hardware
start of conversion using CSTART.

ADC conversion modes

The TLV571 provides two start of conversion modes. Table 1 explains these modes in more detail.

4

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REGISTER

D5D4D3D2D1

D0

COMMENT

detailed description (continued)

TLV571

2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,

PARALLEL ANALOG-TO-DIGITAL CONVERTER

SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000

Table 1. Conversion Modes

START OF

CONVERSION

Hardware start

(CSTAR T)

CR0.D5 = 0

Software start

CR0.D5 = 1

• Repeated conversions from AIN

• CSTART

• CSTART

• If in INT mode, one INT

• If in EOC mode, EOC will go high to low at start of conversion, and return high

at end of conversion.

• Repeated conversions from AIN

• WR

rising edge of RD

• Conversion begins after 6 clocks after sampling has begun. Thereafter, if in INT
mode, one INT

• If in EOC mode, EOC will go high to low at start of conversion and return high at
end of conversion.

falling edge to start sampling
rising edge to start conversion

rising edge to start sampling initially. Thereafter, sampling occurs at the

.

pulse generated after each conversion

OPERATION COMMENTS – FOR INPUT

CSTAR T rising edge must be applied
a minimum of 5 ns before or after CLK
rising edge.

pulse generated after each conversion

With external clock, WR and RD rising
edge must be a minimum 5 ns before
or after CLK rising edge.

configure the device

The device can be configured by writing to control registers CR0 and CR1.

Table 2. TLV571 Programming Examples

INDEX

D7 D6

EXAMPLE1

CR0 0 0 0 0 0 0 0 0 Normal, INT OSC
CR1 0 1 0 0 0 0 0 0 Binary

EXAMPLE2

CR0 0 0 0 1 1 1 0 0 Power down, EXT OSC
CR1 0 1 0 0 0 0 1 0 2’s complement output

power down

The TLV571 offers two power down modes, auto power down and software power down. This device will
automatically proceed to auto power down mode if RD is not present one clock after conversion. Software power
down is controlled directly by the user by pulling CS to DVDD.

Table 3. Power Down Modes

PARAMETERS/MODES AUTO POWER DOWN

Maximum power down dissipation current 1 mA 10 µA
Comparator Power down Power down
Clock buffer Power down Power down
Control registers Saved Saved
Minimum power down time 1 CLK 2 CLK
Minimum resume time 1 CLK 2 CLK

SOFTWARE POWER DOWN

(CS

= DVDD)

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5

TLV571

2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTER

SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000

detailed description (continued)

reference voltage input

The TL V571 has two reference input pins: REFP and REFM. The voltage levels applied to these pins establish
the upper and lower limits of the analog inputs to produce a full-scale and zero-scale reading respectively . The
values of REFP, REFM, and the analog input should not exceed the positive supply or be less than GND
consistent with the specified absolute maximum ratings. The digital output is at full scale when the input signal
is equal to or higher than REFP and is at zero when the input signal is equal to or lower than REFM.

sampling/conversion

All sampling, conversion, and data output in the device are started by a trigger. This could be the RD, WR, or
CSTART signal depending on the mode of conversion and configuration. The rising edge of RD, WR, and
CSTART signal are extremely important, since they are used to start the conversion. These edges need to stay
close to the rising edge of the external clock (if it is used as CLK). The minimum setup and hold time with respect
to the rising edge of the external clock should be 5 ns minimum. When the internal clock is used, this is not an
issue since these two edges will start the internal clock automatically . Therefore, the setup time is always met.
Software controlled sampling lasts 6 clock cycles. This is done via the CLK input or the internal oscillator if
enabled. The input clock frequency can be 1 MHz to 20 MHz, translating into a sampling time from 0.6 µs to

0.3 µs. The internal oscillator frequency is 9 MHz minimum (ocillator frequency is between 9 MHz to 22 MHz),
translating into a sampling time from 0.6 µs to 0.3 µs. Conversion begins immediately after sampling and lasts
10 clock cycles. This is again done using the external clock input (1 MHz–20 MHz) or the internal oscillator
(9 MHz minimum) if enabled. Hardware controlled sampling, via CST AR T
length of the active CSTART

signal. This allows more control over the sampling time, which is useful when
sampling sources with large output impedances. On rising CSTART, conversion begins. Conversion in
hardware controlled mode also lasts 10 clock cycles. This is done using the external clock input (1 MHz–20 MHz)
or the internal oscillator (9 MHz minimum) as is the case in software controlled mode.

, begins on falling CST AR T lasts the

ExtClk

WR

OR

RD

OR

t

d(EXTCLK_CSTARTL)

CSTART

NOTE: tsu = setup time, th = hold time

Figure 3. Trigger Timing – Software Start Mode Using External Clock

≥5 ns

t

h(WRL_EXTCLKH)

t

h(RDL_EXTCLKH)

t

h(CSTARTL_EXTCLKH)

≥5 ns

t

su(WRH_EXTCLKH)

≥5 ns

t

su(RDH_EXTCLKH)

t

su(CSTARTH_EXTCLKH)

≥5 ns

≥5 ns

≥5 ns

≥5 ns

6

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2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,

PARALLEL ANALOG-TO-DIGITAL CONVERTER

SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000

start of conversion mechanism

There are two ways to convert data: hardware and software. In the hardware conversion mode the ADC begins
sampling at the falling edge of CSTART and begins conversion at the rising edge of CSTART. Software start
mode ADC samples for 6 clocks, then conversion occurs for ten clocks. The total sampling and conversion
process lasts only 16 clocks in this case. If RD
proceeds to a power-down state. Data is valid on the rising edge of INT in both conversion modes.

hardware CST ART conversion

external clock

With CS low and WR low, data is written into the ADC. The sampling begins at the falling edge of CSTART and
conversion begins at the rising edge of CST AR T. At the end of conversion, EOC goes from low to high, telling
the host that conversion is ready to be read out. The external clock is active and is used as the reference at all
times. With this mode, it is required that CST ART is not applied at the rising edge of the clock (see Figure 4).

is not detected during the next clock cycle, the ADC automatically

TLV571

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

7

8

start of conversion mechanism (continued)

CLK

t

su(CSL_WRL)

SLAS239A – SEPTEMBER 1999 – REVISED FEBRUAR Y 2000

TLV571

2.7 V to 5.5 V, 1-CHANNEL, 8-BIT

RARALLEL ANALOG-TO-DIGITAL CONVERTER

POST OFFICE BOX 655303 DALLAS, TEXAS 75265

•

OR

CS

WR

CSTART

RD

D[0:7]

INT

EOC

t

h(WRH_CSH)

t

d(CSH_CSTARTL)

t

(sample)

t

su(DAV_WRH)

Config

Data

t

h(WRH_DAV)

t

c

(10 CLKs)

t

su(CSL_RDL)

t

h(RDH_CSH)

t

c

t

(sample)

t

dis(RDH_DAV)

ADC ADC

t

en(RDL_DAV)

t

en(RDL_DAV)

t

su(CSL_RDL)

Figure 4. Input Conversion – Hardware CSTART, External Clock

Auto Powerdown

POST OFFICE BOX 655303 DALLAS, TEXAS 75265

• 9

internal clock

With CS low and WR low, data is written into the ADC. The sampling begins at the falling edge of CST AR T , and conversion begins at the rising
edge of CSTART. The internal clock turns on at the rising edge of CSTART. The internal clock is disabled after each conversion.

t

su(CSL_WRL)

CS

WR

CSTART

INTCLK

RD

D[0:7]

Config

Data

t

t

h(WRH_CSH)

t

d(CSH_CSTARTL)

t

(sample)

su(DAV_WRH)

t

h(WRH_DAV)

10

t

(STARTOSC)

10

9

t

su(CSL_RDL)

t

h(RDH_CSH)

t

dis(RDH_DAV)

ADC
Data

t

en(RDL_DAV)

t

(STARTOSC)

t

c

t

su(CSL_RDL)

ADC
Data

t

en(RDL_DAV)

P ARALLEL ANALOG-T O-DIGITAL CONVERTER

SLAS239A – SEPTEMBER 1999 – REVISED FEBRUAR Y 2000

2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT

OR

INT

EOC

t

c

Auto Powerdown

Figure 5. Input Conversion – Hardware CSTART, Internal Clock

TLV571

Auto Powerdown

10

software START conversion

external clock

With CS low and WR low, data is written into the ADC. Sampling begins at the rising edge of WR. The conversion process begins 6 clocks
after sampling begins. At the end of conversion, the INT goes low telling the host that conversion is ready to be read out. EOC B low during
the conversion. The external clock is active and used as the reference at all times. With this mode, WR and RD should not be applied at the
rising edge of the clock (see Figure 3).

TLV571

2.7 V to 5.5 V, 1-CHANNEL, 8-BIT

RARALLEL ANALOG-TO-DIGITAL CONVERTER

SLAS239A – SEPTEMBER 1999 – REVISED FEBRUAR Y 2000

POST OFFICE BOX 655303 DALLAS, TEXAS 75265

•

OR

CLK

CS

WR

RD

D[0:7]

INT

EOC

015671516

t

su(CSL_WRL)

t

h(WRH_CSH)

t

su(DAV_WRH)

Config

Data

t

(sample)

t

h(WRH_DAV)

04515

t

su(CSL_RDL)

t

h(RDH_CSH)

t

c

t

(sample)

t

dis(RDH_DAV)

ADC Data ADC Data

t

en(RDL_DAV)

t

c

t

su(CSL_RDL)

t

en(RDL_DAV)

Figure 6. Input Conversion – Software Start, External Clock

Auto Powerdown

software START conversion (continued)

internal clock

With CS low and WR low, data is written into the ADC. Sampling begins at the rising edge of WR. Conversion begins 6 clocks after sampling
begins. The internal clock begins at the rising edge of WR. The internal clock is disabled after each conversion. Subsequent sampling begins
at the rising edge of RD.

t

su(CSL_RDL)

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• 11

OR

CS

WR

RD

INTCLK

D[0:7]

INT

t

su(CSL_WRL)

t

h(WRH_CSH)

t

su(DAV_WRH)

Config

Data

t

(STARTOSC)

456 045015 15

t

(sample)

t

h(WRH_DAV)

t

h(RDH_CSH)

t

(STARTOSC)

P ARALLEL ANALOG-T O-DIGITAL CONVERTER

t

(sample)

SLAS239A – SEPTEMBER 1999 – REVISED FEBRUAR Y 2000

t

c

t

dis(RDH_DAV)

ADC
Data

t

en(RDL_DAV)

t

c

ADC

2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT

EOC

Auto Powerdown

Figure 7. Input Conversion – Software Start, Internal Clock

Auto Powerdown

TLV571

TLV571

2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTER

SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000

software START conversion (continued)
system clock source

The TL V571 internally derives multiple clocks from the SYSCLK for dif ferent tasks. SYSCLK is used for most
conversion subtasks. The source of SYSCLK is programmable via control register zero, bit 3. The source of
SYSCLK is changed at the rising edge of WR

internal clock (CR0.D3 = 0, SYSCLK = internal OSC)

The TLV571 has a built-in 10 MHz OSC. When the internal OSC is selected as the source of SYSCLK, the
internal clock starts with a delay (one half of the OSC period max) after the falling edge of the conversion trigger
(either WR, RD, or CST ART). The OSC speed can be set to 10 ± 1 MHz or 20 ± 2 MHz by setting register bit
CR1.D4.

external clock (CR0.D3 = 1, SYSCLK = external clock)

The TLV571 is designed to accept an external clock input (CMOS/TTL logic) with frequencies from 1 MHz to
20 MHz.

host processor interface

The TLV571 provides a generic high-speed parallel interface that is compatible with high-performance DSPs
and general-purpose microprocessors. The interface includes D(0–7), INT/EOC, RD, and WR.

of the cycle when CR0.D3 is programmed.

output format

The data output format is unipolar (code 0 to 255). The output code format can be either binary or twos
complement by setting register bit CR1.D1.

power up and initialization

After power up, CS
cycles to configure the two control registers. The first conversion after the device has returned from the power
down state may be invalid and should be disregarded.

must be low to begin an I/O cycle. INT/EOC is initially high. The TL V571 requires two write

definitions of specifications and terminology

integral nonlinearity

Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through full scale.
The point used as zero occurs 1/2 LSB before the first code transition. The full-scale point is defined as level
1/2 LSB beyond the last code transition. The deviation is measured from the center of each particular code to
the true straight line between these two points.

differential nonlinearity

An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value.
A differential nonlinearity error of less than ±1 LSB ensures no missing codes.

zero offset

The major carry transition should occur when the analog input is at zero volts. Zero error is defined as the
deviation of the actual transition from that point.

gain error

The first code transition should occur at an analog value 1/2 LSB above negative full scale. The last transition
should occur at an analog value 1 1/2 LSB below the nominal full scale. Gain error is the deviation of the actual
difference between first and last code transitions and the ideal difference between first and last code transitions.

12

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2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,

PARALLEL ANALOG-TO-DIGITAL CONVERTER

SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000

software START conversion (continued)
signal-to-noise ratio + distortion (SINAD)

Signal-to-noise ratio + disortion is the ratio of the rms value of the measured input signal to the rms sum of all
other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for
SINAD is expressed in decibels.

effective number of bits (ENOB)

For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula,

N = (SINAD – 1.76)/6.02

it is possible to get a measure of performance expressed as N, the effective number of bits. Thus, the effective
number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its
measured SINAD.

total harmonic distortion (THD)

T otal harmonic distortion is the ratio of the rms sum of the first six harmonic components to the rms value of the
measured input signal and is expressed as a percentage or in decibels.

spurious free dynamic range (SFDR)

TLV571

Spurious free dynamic range is the difference in dB between the rms amplitude of the input signal and the peak
spurious signal.

DSP interface

The TL V571 is a 8-bit single input channel analog-to-digital converter with throughput up to 1.25 MSPS at 5 V
and up to 625 KSPS at 3 V . To achieve 1.25 MSPS throughput, the ADC must be clocked at 20 MHz. Likewise
to achieve 625 KSPS throughout, the ADC must be clocked at 10 MHz. The TL V571 can be easily interfaced
to microcontrollers, ASICs, and DSPs. Figure 8 shows the pin connections to interface the TLV571 to the
TMS320C6x DSP.

TMS320C6X

A0–A15

TLV571

Address

HW

HR

INTx

D0–D15

EN

Decoder

CS

WR
RD
EOC
D0–D7

AIN

REF

REFP

REFM

Figure 8. TMS320C6x DSP Interface

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13

TLV571

2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTER

SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000

grounding and decoupling considerations

General practices should apply to the PCB design to limit high frequency transients and noise that are fed back
into the supply and reference lines. This requires that the supply and reference pins be sufficiently bypassed.
In most cases 0.1-µF ceramic chip capacitors are adequate to keep the impedance low over a wide frequency
range. Since their effectiveness depends largely on the proximity to the individual supply pin, they should be
placed as close to the supply pins as possible.

To reduce high frequency and noise coupling, it is highly recommended that digital and analog grounds be
shorted immediately outside the package. This can be accomplished by running a low impedance line between
DGND and AGND under the package.

DD

REFP

AV

DD

100 nF

100 nF

V

REFP

V

REFM

100 nF

DV

DD

DV

DD

DGND

TLV571

AV

AGND

REFM

Figure 9. Placement for Decoupling Capacitors

power supply ground layout

Printed-circuit boards that use separate analog and digital ground planes offer the best system performance.
Wire-wrap boards do not perform well and should not be used. The two ground planes should be connected
together at the low-impedance power-supply source. The best ground connection may be achieved by
connecting the ADC AGND terminal to the system analog ground plane making sure that analog ground
currents are well managed.

Driving Source

†

R

s

V

V

S

I

AIN

TLV571

R

i(ADC)

V

C

C
15 pF

VI= Input Voltage at AIN
VS= External Driving Source Voltage
Rs= Source Resistance
R
Ci= Input Capacitance
VC= Capacitance Charging Voltage

i

= Input Resistance of ADC

i(ADC)

14

†

Driving source requirements:

• Noise and distortion for the source must be equivalent to the resolution of the converter.

• Rs must be real at the input frequency.

Figure 10. Equivalent Input Circuit Including the Driving Source

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simplified analog input analysis

TLV571

2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,

PARALLEL ANALOG-TO-DIGITAL CONVERTER

SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000

Using the equivalent circuit in Figure 10, the time required to charge the analog input capacitance from 0 to V
within 1/2 LSB, tch(1/2 LSB), can be derived as follows.

The capacitance charging voltage is given by:

–tchń

RtC

+

V

i(ADC)

ǒ

VSń

ǒ

1–e

S

i

512Ǔ+

V

C(t)

Where

R

= Rs + R

t

Ri = R
tch = Charge time

The input impedance Ri is 718 Ω at 5 V , and is higher (~ 1.25 kΩ) at 2.7 V. The final voltage to 1/2 LSB is given
by:

VC (1/2 LSB) = VS – (VS/512)

Equating equation 1 to equation 2 and solving for cycle time tc gives:

VS*

and time to change to 1/2 LSB (minimum sampling time) is:

t

(1/2 LSB) = Rt × Ci × ln(512)

ch

Where

i

Ǔ

(1)

(2)

–tchń

RtC

ǒ

V

1–e

S

i

Ǔ

(3)

S

ln(512) = 6.238

Therefore, with the values given, the time for the analog input signal to settle is:

tch (1/2 LSB) = (Rs + 718 Ω) × 15 pF × ln(512)

This time must be less than the converter sample time shown in the timing diagrams. Which is 6x SCLK.

tch (1/2 LSB) ≤ 6x 1/f

Therefore the maximum SCLK frequency is:

Max(f

(SCLK)

) = 6/tch (1/2 LSB) = 6/(ln(512) × Rt × Ci)

(SCLK)

(4)

(5)

(6)

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

15

TLV571

Input CLK frequenc

Pulse duration, CLK high, t

Pulse duration, CLK low, t

(CLKL)

ns

VREFP

VREFM

2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTER

SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, GND to VCC –0.3 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Analog input voltage range –0.3 V to AVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reference input voltage range AVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Digital input voltage range –0.3 V to DV

DD

+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating virtual junction temperature range, TJ –40°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, TA, –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

power supplies

MIN MAX UNIT

Analog supply voltage, A V
Digital supply voltage, DV

NOTE 1: Abs (AVDD – DVDD) < 0.5 V

DD

DD

analog inputs

Analog input voltage, AIN AGND VREFP V

2.7 5.5 V

2.7 5.5 V

MIN MAX UNIT

†

digital inputs

High-level input voltage, V
Low level input voltage, V

p

Rise time, I/O and control, CLK, CS 50 pF output load 4
Fall time, I/O and control, CLK, CS 50 pF output load 4

IH

IL

y

w(CLKH)

w

DVDD = 2.7 V to 5.5 V 2.1 2.4 V
DVDD = 2.7 V to 5.5 V 0.8 V
DVDD = 4.5 V to 5.5 V 20 MHz
DVDD = 2.7 V to 3.3 V 10 MHz
DVDD = 4.5 V to 5.5 V, f
DVDD = 2.7 V to 3.3 V, f
DVDD = 4.5 V to 5.5 V, f
DVDD = 2.7 V to 3.3 V, f

= 20 MHz 23 ns

CLK

= 10 MHz 46 ns

CLK

= 20 MHz 23 ns

CLK

= 10 MHz 46 ns

CLK

reference specifications

MIN NOM MAX UNIT

AVDD = 3 V 2 AV
AVDD = 5 V 2.5 AV

External reference voltage

VREFP – VREFM 2 AVDD–AGND V

AVDD = 3 V AGND 1 V
AVDD = 5 V AGND 2 V

MIN NOM MAX UNIT

DD
DD

V
V

16

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Internal clock

MHz

CiInput capacitance

Operating supply current, I

I

PD

Power dissipation

Software

I

I

IPDSupply current in power-down mode

Auto

I

I

TLV571

2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,

PARALLEL ANALOG-TO-DIGITAL CONVERTER

SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000

electrical characteristics over recommended operating free-air temperature range, supply
voltages, and reference voltages (unless otherwise noted)

digital specifications

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Logic inputs

I

High-level input current DVDD = 5 V, DVDD = 3 V, Input = DV

IH

I

Low-level input current DVDD = 5 V, DVDD = 3 V, Input = 0 V –1 1 µA

IL

C

Input capacitance 10 15 pF

i

Logic outputs

V

High-level output voltage IOH = 50 µA to 0.5 mA DVDD–0.4 V

OH

V

Low-level output voltage IOL = 50 µA to 0.5 mA 0.4 V

OL

I

High-impedance-state output current DVDD = 5 V, DVDD = 3 V, Input = DV

OZ

I

Low-impedance-state output current DVDD = 5 V, DVDD = 3 V, Input = 0 V –1 µA

OL

C

Output capacitance 5 pF

o

dc specifications

Resolution 8 Bits

Accuracy

Integral nonlinearity, INL Best fit ±0.3 ±0.5 LSB
Differential nonlinearity , DNL ±0.3 ±0.5 LSB
Missing codes 0

E

Offset error ±0.15% ±0.3% FSR

O

E

Gain error ±0.2% ±0.4% FSR

G

Analog input

p

p

I

Input leakage current V

lkg

Voltage reference input

r

Input resistance 2 kΩ

i

C

Input capacitance 300 pF

i

Power supply

p

p

pp

DD

DD

3 V, AVDD = DV
5 V, AVDD = DV

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

pp

p

DD

+

REF

DD
DD

AIN, AVDD = 3 V, AVDD = 5 V 15 pF
MUX input, AVDD = 3 V, AVDD = 5 V 25 pF

= 0 to AV

AIN

AVDD = DVDD = 3 V, f
AVDD = DVDD = 5 V, f
AVDD+DVDD = 3 V 12 17 mW
AVDD+DVDD = 5 V 35 43 mW

+

DD

+

DD

REF

REF

DD

= 10 MHz 4 5.5 mA

CLK

= 20 MHz

CLK

AVDD = 3 V 1 8 µA
AVDD = 5 V 2 10 µA
AVDD = 3 V 0.5 1 mA
AVDD = 5 V 0.5 1 mA

–1 1 µA

1 µA

9 10 11

18 20 22

±1 µA

7 8.5 mA

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

17

TLV571

Signal-to-noise ratio, SNR

I

,

Signal-to-noise ratio

distortion, SINAD

I

,

Total harmonic distortion, THD

I

,

Effective number of bits, ENOB

I

,

Spurious free dynamic range, SFDR

I

,

Full-power bandwidth

Small-signal bandwidth

Sam ling rate, f

2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTER

SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000

electrical characteristics over recommended operating free-air temperature range, supply
voltages, and reference voltages (unless otherwise noted) (continued)

ac specifications, AVDD = DVDD = 5 V (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

fs = 1.25 MSPS, A VDD = 5 V 47 49 dB
fs = 625 KSPS, AVDD = 3 V 47 49 dB
fs = 1.25 MSPS, A VDD = 5 V 47 49 dB
fs = 625 KSPS, AVDD = 3 V 47 49 dB
fs = 1.25 MSPS, A VDD = 5 V –64 –52 dB
fs = 625 KSPS, AVDD = 3 V –62 –52 dB
fs = 1.25 MSPS, A VDD = 5 V 7.5 7.9 Bits
fs = 625 KSPS, AVDD = 3 V 7.5 7.9 Bits
fs = 1.25 MSPS, A VDD = 5 V –65 –51 dB
fs = 625 KSPS, AVDD = 3 V –64 –51 dB

p

Analog input

f

= 100 kHz,

80% of FS
f

+

p

p

s

–1 dB Full-scale 0 dB input sine wave 12 18 MHz
–3 dB Full-scale 0 dB input sine wave 30 MHz
–1 dB –20 dB input sine wave 15 20 MHz
–3 dB –20 dB input sine wave 35 MHz

= 100 kHz,

80% of FS
f

= 100 kHz,

80% of FS
f

= 100 kHz,

80% of FS
f

= 100 kHz,

80% of FS

AVDD = 4.5 V to 5.5 V 0.0625 1.25 MSPS
AVDD = 2.7 V to 3.3 V 0.0625 0.625 MSPS

18

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

t

(CLK)

In ut clock Cycle time

t

(RDL_DAV)

Enable time, data out

t

dis(RDH_DAV)

Disable time, data out

2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,

PARALLEL ANALOG-TO-DIGITAL CONVERTER

SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000

timing requirements, AVDD = DVDD = 5 V (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

c

t

(sample)

t

c

t

wL(EOC)

t

wL(INT)

t

(STARTOSC)

t

d(CSH_CSTARTL)

en

t

su(CSL_WRL)

t

h(WRH_CSH)

t

w(WR)

t

w(RD)

t

su(DAV_WRH)

t

h(WRH_DAV)

t

su(CSL_RDL)

t

h(RDH_CSH)

t

h(WRL_EXTXLKH)

t

h(RDL_EXTCLKH)

t

h(CSTARTL_EXTCLKH)

t

su(WRH_EXTCLKH)

t

su(RDH_EXTCLKH)

t

su(CSTARTH_EXTCLKH)

t

d(EXTCLK_CSTARTL)

NOTE: Specifications subject to change without notice.

Data valid is denoted as DAV.

p

Reset and sampling time 6

Total conversion time 10

Pulse width, end of conversion, EOC 10

Pulse width, interrupt 1
Start-up time, internal oscillator 100 ns

Delay time, CS high to CSTART low 10 ns

Setup time, CS to WR 5 ns
Hold time, CS to WR 5 ns

Pulse width, write 1

Pulse width, read 1
Setup time, data valid to WR 10 ns

Hold time, data valid to WR 5 ns
Setup time, CS to RD 5 ns
Hold time, CS to RD 5 ns
Hold time WR to clock high 5 ns
Hold time RD to clock high 5 ns
Hold time CSTAR T to clock high 5 ns
Setup time WR high to clock high 5 ns
Setup time RD high to clock high 5 ns
Setup time CSTAR T high to clock high 5 ns
Delay time clock low to CSTART low 5 ns

DVDD = 4.5 V to 5.5 V 50 ns
DVDD = 2.7 V to 3.3 V 100 ns

DVDD = 5 V at 50 pF 20 ns
DVDD = 3 V at 50 pF 40 ns
DVDD = 5 V at 50 pF 5 ns
DVDD = 3 V at 50 pF 10 ns

TLV571

SYSCLK

Cycles

SYSCLK

Cycles

SYSCLK

Cycles

SYSCLK

Cycles

Clock

Period

Clock

Period

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

19

TLV571

2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTER

SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000

TYPICAL CHARACTERISTICS

SUPPLY CURRENT

FREE AIR TEMPERATURE

8.0

7.5

7.0

6.5

6.0

5.5

5.0

4.5

4.0

3.5

3.0

– Supply Current – mA

2.5

CC

I

2.0

1.5

1.0

0.5

0.0
–40 –30 –20 –10 0 10 20 30 40 50 60 70 80

AVDD = DVDD = 5 V, 20 MHz

AVDD = DVDD = 3 V, 10 MHz

TA – Free Air Temperature – °C

Figure 11

vs

SUPPLY CURRENT

vs

CLOCK FREQUENCY

7

6

5

4

3

– Supply Current – mA

2

CC

I

1

0

0 2 4 6 8 101214161820

AVDD = DVDD = 5 V

AVDD = DVDD = 3 V

f

– Clock Frequency – MHz

clock

Figure 12

ANALOG INPUT BANDWIDTH

FREQUENCY

1

0

–1

–2

–3

AVDD = DVDD = 5 V,

–4

Analog Input Bandwidth – dB

AIN = 90% of FS,
REF = 5 V,

–5

TA = 25°C

–6

0.1 1
f – Frequency – MHz

Figure 13

vs

10 100

20

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV571

2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,

PARALLEL ANALOG-TO-DIGITAL CONVERTER

SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000

TYPICAL CHARACTERISTICS

DIFFERENTIAL NONLINEARITY

vs

DIGITAL OUTPUT CODE

0.15

0.10

0.05

–0.00

–0.05

–0.10

–0.15

DNL – Differential Nonlinearity – LSB

0 64 128 192 256

Digital Output Code

Figure 14

AVDD = DVDD = 3 V,
External Ref = 3 V,
CLK = 10 MHz,
TA = 25°C

INTEGRAL NONLINEARITY

vs

DIGITAL OUTPUT CODE

0.14

0.12

0.10

0.08

0.06

0.04

0.02

0.00
–0.02
–0.04

INL – Integral Nonlinearity – LSB

–0.06

0 64 128 192 256

AVDD = DVDD = 3 V,
External Ref = 3 V,
CLK = 10 MHz,
TA = 25°C

Digital Output Code

Figure 15

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

21

TLV571

2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTER

SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000

TYPICAL CHARACTERISTICS

DIFFERENTIAL NONLINEARITY

vs

DIGITAL OUTPUT CODE

0.12

0.10

0.08

0.06

0.04

0.02

0.00
–0.02
–0.04
–0.06
–0.08

DNL – Differential Nonlinearity – LSB

0 64 128 192 256

Digital Output Code

Figure 16

AVDD = DVDD = 5 V,
External Ref = 5 V,
CLK = 20 MHz,
TA = 25

°C

INTEGRAL NONLINEARITY

vs

DIGITAL OUTPUT CODE

0.14

AVDD = DVDD = 5 V,

0.12

External Ref = 5 V,

0.10

CLK = 20 MHz,

0.08

TA = 25°C

0.06

0.04

0.02

0.00
–0.02
–0.04
–0.06

INL – Integral Nonlinearity – LSB

–0.08

0 64 128 192 256

Digital Output Code

Figure 17

22

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV571

2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,

PARALLEL ANALOG-TO-DIGITAL CONVERTER

SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000

TYPICAL CHARACTERISTICS

EFFECTIVE NUMBER OF BITS

vs

FREQUENCY

10

9

8

7

6

ENOB – Effective Number of Bits – BITS

5

0 100 200 300

AVDD = DVDD = 3 V,
External Ref = 3 V

f – Frequency – kHz

Figure 18

EFFECTIVE NUMBER OF BITS

vs

FREQUENCY

10

9

8

7

6

ENOB – Effective Number of Bits – BITS

5

0 200 400 600

AVDD = DVDD = 5 V,
External Ref = 5 V

f – Frequency – kHz

Figure 19

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

23

TLV571

2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTER

SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000

TYPICAL CHARACTERISTICS

FAST FOURIER TRANSFORM

vs

FREQUENCY

20

0
–20
–40
–60
–80

Magnitude – dB

–100
–120
–140

AIN = 200 KHz
CLK = 10 MHz
AVDD = DVDD = 3 V
External Ref = 3 V

0 100000 200000 300000

f – Frequency – Hz

Figure 20

20

0
–20
–40
–60
–80

Magnitude – dB

–100
–120
–140

0 200000 400000 600000

FAST FOURIER TRANSFORM

vs

FREQUENCY

AIN = 200 KHz
CLK = 20 MHz
AVDD = DVDD = 5 V
External Ref = 5 V

f – Frequency – Hz

Figure 21

24

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV571

2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,

PARALLEL ANALOG-TO-DIGITAL CONVERTER

SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000

MECHANICAL DATA

DW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

16 PINS SHOWN

0.050 (1,27)

16

1

0.020 (0,51)

0.014 (0,35)
9

0.299 (7,59)

0.293 (7,45)

8

A

0.010 (0,25)

0.419 (10,65)

0.400 (10,15)

M

0.010 (0,25) NOM

0°–8°

Gage Plane

0.010 (0,25)

0.050 (1,27)

0.016 (0,40)

0.104 (2,65) MAX

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-013

0.012 (0,30)

0.004 (0,10)

DIM

A MAX

A MIN

PINS **

16

0.410

(10,41)

0.400

(10,16)

Seating Plane

0.004 (0,10)

20

0.510

(12,95)

0.500

(12,70)

0.610

(15,49)

0.600

(15,24)

24

28

0.710

(18,03)

0.700

(17,78)

4040000/C 07/96

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

25

TLV571

2.7 V TO 5.5 V, 1-CHANNEL, 8-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTER

SLAS239A – SEPTEMBER 1999 – REVISED FEBRUARY 2000

MECHANICAL DATA

PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,65

1,20 MAX

14

0,30
0,19

8

4,50
4,30

PINS **

7

Seating Plane

0,15
0,05

8

1

A

DIM

6,60
6,20

14

0,10

0,10

M

0,15 NOM

Gage Plane

0,25

0°–8°

2016

24

28

0,75
0,50

A MAX

A MIN

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153

3,10

2,90

5,10

4,90

5,10

4,90

6,60

6,40

7,90

7,70

9,80

9,60

4040064/F 01/97

26

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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