Texas Instruments TLV5639IPWR, TLV5639IPW, TLV5639IDWR, TLV5639IDW, TLV5639CPWR Datasheet

TLV5639C, TLV5639I

2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG

CONVERTERS WITH INTERNAL REFERENCE AND POWER DOWN

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D

12-Bit Voltage Output DAC

D

Programmable Internal Reference

D

Programmable Settling Time vs Power
Consumption

1 µs in Fast Mode

3.5 µs in Slow Mode

D

Compatible With TMS320

D

Differential Nonlinearity...<0.5 LSB Typ

D

Voltage Output Range ... 2x the
Reference V oltage

D

Monotonic Over Temperature

applications

D

Digital Servo Control Loops

D

Digital Offset and Gain Adjustment

D

Industrial Process Control

D

Machine and Motion Control Devices

D

Mass Storage Devices

description

The TLV5639 is a 12-bit voltage output digital-to-analog converter (DAC) with a microprocessor compatible
parallel interface. It is programmed with a 16-bit data word containing 4 control and 12 data bits. Developed for
a wide range of supply voltages, the TLV5639 can be operated from 2.7 V to 5.5 V.

The resistor string output voltage is buffered by a x2 gain rail-to-rail output buffer . The buffer features a Class AB
output stage to improve stability and reduce settling time. The programmable settling time of the DAC allows
the designer to optimize speed versus power dissipation. Because of its ability to source up to 1 mA, the internal
reference can also be used as a system reference. With its on-chip programmable precision voltage reference,
the TLV5639 simplifies overall system design. The settling time and the reference voltage can be chosen by
the control bits within the 16-bit data word.

Implemented with a CMOS process, the device is designed for single supply operation from 2.7 V to 5.5 V. It
is available in 20-pin SOIC and TSSOP packages in standard commercial and industrial temperature ranges.

AVAILABLE OPTIONS

PACKAGE

T

A

SOIC
(DW)

TSSOP

(PW)

0°C to 70°C TLV5639CDW TLV5639CPW

–40°C to 85°C TLV5639IDW TLV5639IPW

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Copyright  1999, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

1
2
3
4
5
6
7
8
9
10

20
19
18
17
16
15
14
13
12
11

D2
D3
D4
D5
D6
D7
D8

D9
D10
D11

D1
D0
CS
WE
LDAC
REG
AGND
OUT
REF
V

DD

DW OR PW PACKAGE

(TOP VIEW)

TLV5639C, TLV5639I

2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG
CONVERTERS WITH INTERNAL REFERENCE AND POWER DOWN

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functional block diagram

Interface

Control

12-Bit

DAC

Holding

Latch

D(0–11)

CS

REG

WE

OUT

Power-On

Reset

x2

12

4-Bit

Control

Latch

4

Powerdown

and Speed

Control

2

Voltage

Bandgap

PGA With

Output Enable

12-Bit

DAC

Register

12 12

REF AGND V

DD

LDAC

Terminal Functions

TERMINAL

NAME NO.

I/O/P

DESCRIPTION

AGND 14 P Ground
CS 18 I Chip select. Digital input active low, used to enable/disable inputs
D0 – D11 1 – 10,

19, 20

I Data input

LDAC 16 I Load DAC. Digital input active low, used to load DAC output
OUT 13 O DAC analog voltage output
REG 15 I Register select. Digital input, used to access control register
REF 12 I/O Analog reference voltage input/output
V

DD

11 P Positive power supply

WE 17 I Write enable. Digital input active low, used to latch data

TLV5639C, TLV5639I

2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG

CONVERTERS WITH INTERNAL REFERENCE AND POWER DOWN

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absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage (V

DD

to AGND) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reference input voltage range – 0.3 V to V

DD

+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Digital input voltage range – 0.3 V to V

DD

+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, T

A

: TLV5639C 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TLV5639I –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150° C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

MIN NOM MAX UNIT

pp

VDD = 5 V 4.5 5 5.5 V

Suppl

y v

oltage, V

DD

VDD = 3 V 2.7 3 3.3 V
Power on threshold voltage, POR 0.55 2 V
High-level digital input voltage, V

IH

VDD = 2.7 V to 5.5 V 2 V
Low-level digital input voltage, V

IL

VDD = 2.7 V to 5.5 V 0.8 V
Reference voltage, V

ref

to REF terminal VDD = 5 V (see Note 1) AGND 2.048 VDD–1.5 V

Reference voltage, V

ref

to REF terminal VDD = 3 V (see Note 1) AGND 1.024 VDD–1.5 V

Load resistance, R

L

2 kΩ

Load capacitance, C

L

100 pF

p

p

TLV5639C 0 70

°

Operating free-air temperature, T

A

TLV5639I –40 85

°C

NOTE 1: Due to the x2 output buffer , a reference input voltage ≥ V

DD/2

causes clipping of the transfer function. The output buffer of the internal

reference must be disabled, if an external reference is used.

TLV5639C, TLV5639I

2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG
CONVERTERS WITH INTERNAL REFERENCE AND POWER DOWN

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electrical characteristics over recommended operating free-air temperature range, V

ref

= 2.048 V,

V

ref

= 1.024 V (unless otherwise noted)

power supply

PARAMETER TEST CONDITIONS MIN TYP MAX

UNIT

REF

Fast 2.3 2.8 mA

on

Slow 1.3 1.6 mA

V

DD

= 5

V

REF

Fast 1.9 2.4 mA

pp

No load,

p

off

Slow 0.9 1.2 mA

IDDPower supply current

All inputs

=

AGND or V

DD

,

DAC latch = 0x800

REF

Fast 2.1 2.6 mA

on

Slow 1.2 1.5 mA

V

DD

=

3 V

REF

Fast 1.8 2.3 mA

off

Slow 0.9 1.1 mA

Power down supply current 0.01 1 µA

pp

Zero scale, See Note 2, External reference –60

PSRR

Power supply rejection ratio

Full scale, See Note 3, External reference –60

dB

NOTES: 2. Power supply rejection ratio at zero scale is measured by varying VDD and is given by:

PSRR = 20 log [(EZS(VDDmax) – EZS(VDDmin))/VDDmax]

3. Power supply rejection ratio at full scale is measured by varying VDD and is given by:
PSRR = 20 log [(EG(VDDmax) – EG(VDDmin))/VDDmax]

static DAC specifications

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Resolution 12 bits
INL Integral nonlinearity , end point adjusted RL = 10 kΩ, CL = 100 pF, See Note 4 ±1.2 ±3 LSB
DNL Differential nonlinearity RL = 10 kΩ, CL = 100 pF, See Note 5 ±0.3 ±0.5 LSB
E

ZS

Zero-scale error (offset error at zero scale) See Note 6 ±12 LSB
EZS TC Zero-scale-error temperature coefficient See Note 7 20 ppm/°C

E

G

Gain error See Note 8 ±0.3

% full

scale V

EG TCGain error temperature coefficient See Note 9 20 ppm/°C

NOTES: 4. The relative accuracy or integral nonlinearity (INL) sometimes referred to as linearity error, is the maximum deviation of the output

from the line between zero and full scale excluding the effects of zero code and full-scale errors (see text).

5. The differential nonlinearity (DNL) sometimes referred to as differential error, is the dif ference between the measured and ideal 1
LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains
constant) as a change in the digital input code.

6. Zero-scale error is the deviation from zero voltage output when the digital input code is zero (see text).

7. Zero-scale-error temperature coefficient is given by: EZSTC = [EZS(T

max

) – EZS(T

min

)]/2V

ref

× 106/(T

max

– T

min

).

8. Gain error is the deviation from the ideal output (2V

ref

– 1 LSB) with an output load of 10 k excluding the effects of the zero-error.

9. Gain temperature coefficient is given by: EGTC = [EG(T

max

) – EG (T

min

)]/2V

ref

× 106/(T

max

– T

min

).

output specifications

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

O

Output voltage RL = 10 kΩ VDD–0.4 V
Output load regulation accuracy VO = 4.096 V , 2.048 V RL = 2 kΩ ±0.29

% full

scale V

TLV5639C, TLV5639I

2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG

CONVERTERS WITH INTERNAL REFERENCE AND POWER DOWN

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electrical characteristics over recommended operating free-air temperature range, V

ref

= 2.048 V,

V

ref

= 1.024 V (unless otherwise noted) (Continued)

reference pin configured as output (REF)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

ref(OUTL)

Low reference voltage 1.003 1.024 1.045 V

V

ref(OUTH)

High reference voltage VDD > 4.75 V 2.027 2.048 2.069 V

I

ref(source)

Output source current 1 mA

I

ref(sink)

Output sink current –1 mA

PSRR Power supply rejection ratio –48 dB

reference pin configured as input (REF)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VIInput voltage 0 V

DD–1.5

V
RIInput resistance 10 MΩ
CIInput capacitance 5 pF

p

Fast 900

Reference input bandwidth

REF

= 0.2

V

pp

+ 1.

024 V dc

Slow 500

kH

z

Fast –87

10 kH

z

Slow –77

dB

Harmonic distortion, reference

p

REF = 1 Vpp + 2.048 V dc, VDD = 5 V

Fast –74

in ut

50 kH

z

Slow –61

dB

100 kHz Fast –66 dB

Reference feedthrough REF = 1 Vpp at 1 kHz + 1.024 V dc (see Note 10) –80 dB

NOTE 10: Reference feedthrough is measured at the DAC output with an input code = 0x000.

digital inputs

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

I

IH

High-level digital input current VI = V

DD

1 µA

I

IL

Low-level digital input current VI = 0 V –1 µA

C

i

Input capacitance 8 pF

TLV5639C, TLV5639I

2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG
CONVERTERS WITH INTERNAL REFERENCE AND POWER DOWN

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operating characteristics over recommended operating free-air temperature range, V

ref

= 2.048 V ,

and V

ref

= 1.024 V, (unless otherwise noted)

analog output dynamic performance

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

p

R

= 10 kΩ,C

= 100 pF,

Fast 1 3

t

s(FS)

Output settling time, full scale

L

,

L

,

See Note 11

Slow 3.5 7

µ

s

p

R

= 10 kΩ,C

= 100 pF,

Fast 0.5 1.5

t

s(CC)

Output settling time, code to code

L

,

L

,

See Note 12

Slow 1 2

µ

s

R

= 10 kΩ,C

= 100 pF,

Fast 6 10

SR

Slew rate

L

,

L

,

See Note 13

Slow 1.2 1.7

V/µs

Glitch energy

DIN = 0 to 1, f

CLK

= 100 kHz,

CS

= V

DD

5 nV–S

SNR Signal-to-noise ratio 73 78
SINAD Signal-to-noise + distortion

fs = 480 kSPS, f

out

= 1 kHz,

61 67

THD Total harmonic distortion

f

B

=

20 kH

z,

R

L

=

10 kΩ

,

C

= 100 pF

–69 –62

dB

SFDR Spurious free dynamic range

C

L

=

100 F

63 74

NOTES: 11. Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change

of 0x020 to 0xFDF or 0xFDF to 0x020.

12. Settling time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change
of one count.

13. Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage.

digital input timing requirements

MIN NOM MAX UNIT

t

su(CS–WE)

Setup time, CS low before negative WE edge 15 ns

t

su(D)

Setup time, data ready before positive WE edge 10 ns

t

su(R)

Setup time, REG ready before positive WE edge 20 ns

t

h(DR)

Hold time, data and REG held valid after positive WE edge 5 ns

t

su(WE-LD)

Setup time, positive WE edge before LDAC low 5 ns

t

wH(WE)

Pulse duration, WE high 20 ns

t

w(LD)

Pulse duration, LDAC low 23 ns