Texas Instruments TLV5638QDR, TLV5638QD, TLV5638MJGB, TLV5638MFKB, TLV5638MJG Datasheet

TLV5638

2.7 V TO 5.5 V LOW POWER DUAL 12-BIT DIGITAL-TO-ANALOG

CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN

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features

D

Dual 12-Bit Voltage Output DAC

D

Programmable Internal Reference

D

Programmable Settling Time:

1 µs in Fast Mode,

3.5 µs in Slow Mode

D

Compatible With TMS320 and SPI Serial
Ports

D

Differential Nonlinearity <0.5 LSB Typ

D

Monotonic Over Temperature

applications

D

Digital Servo Control Loops

D

Digital Offset and Gain Adjustment

D

Industrial Process Control

D

Machine and Motion Control Devices

D

Mass Storage Devices

description

The TLV5638 is a dual 12-bit voltage output DAC
with a flexible 3-wire serial interface. The serial
interface allows glueless interface to TMS320 and
SPI, QSPI, and Microwire serial ports. It is programmed with a 16-bit serial string containing 4 control and
12 data bits.

The resistor string output voltage is buffered by a x2 gain rail-to-rail output buffer. The buffer features a Class
AB output stage to improve stability and reduce settling time. The programmable settling time of the DAC allows
the designer to optimize speed vs power dissipation. With its on-chip programmable precision voltage
reference, the TLV5638 simplifies overall system design.

Because of its ability to source up to 1 mA, the reference can also be used as a system reference. Implemented
with a CMOS process, the device is designed for single supply operation from 2.7 V to 5.5 V. It is available in
an 8-pin SOIC package to reduce board space in standard commercial, industrial, and automotive temperature
ranges. It is also available in JG and FK packages in the military temperature range.

AVAILABLE OPTIONS

PACKAGE

T

A

SOIC

(D)

CERAMIC DIP

(JG)

20 PAD LCCC

(FK)

0°C to 70°C TLV5638CD — —

–40°C to 85°C TLV5638ID — —

–40°C to 125°C

TLV5638QD

TLV5638QDR

— —

–55°C to 125°C — TLV5638MJG TLV5638MFK

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Copyright  2000, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

1
2
3
4

8
7
6
5

DIN

SCLK

CS

OUTA

V

DD

OUTB
REF
AGND

D, JG PACKAGE

(TOP VIEW)

1920132

17

18

16
15
14

1312119 10

5

4

6
7
8

NC
OUTB
NC
REF
NC

NC

SCLK

NC
CS
NC

NC

DINNCV

NC

OUTA

NC

AGND

NC

NC

FK PACKAGE

(TOP VIEW)

DD

On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.

SPI and QSPI are trademarks of Motorola, Inc.
Microwire is a trademark of National Semiconductor Corporation.

TLV5638

2.7 V TO 5.5 V LOW POWER DUAL 12-BIT DIGITAL-TO-ANALOG
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functional block diagram

Serial

Interface

and

Control

12-Bit

DAC B

Latch

SCLK

DIN

CS

OUTA

Power-On

Reset

x2

12

2-Bit

Control

Latch

Power

and Speed

Control

2

Voltage

Bandgap

PGA With

Output Enable

12-Bit

DAC A

Latch

12

REF AGND V

DD

2

12 12

OUTB

x2

Buffer

12

Terminal Functions

TERMINAL

NAME NO.

I/O/P

DESCRIPTION

AGND 5 P Ground
CS 3 I Chip select. Digital input active low, used to enable/disable inputs
DIN 1 I Digital serial data input
OUT A 4 O DAC A analog voltage output
OUT B 7 O DAC B analog voltage output
REF 6 I/O Analog reference voltage input/output
SCLK 2 I Digital serial clock input
V

DD

8 P Positive power supply

TLV5638

2.7 V TO 5.5 V LOW POWER DUAL 12-BIT DIGITAL-TO-ANALOG

CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN

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absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage (VDD to AGND) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reference input voltage range –0.3 V to VDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Digital input voltage range –0.3 V to V

DD

+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, TA: TLV5638C 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TLV5638I –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TLV5638Q –40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TLV5638M –55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

DISSIPATION RATING TABLE

T

≤ 25°C DERA TING FACTOR T

= 70°C T

= 85°C T

= 125°C

PACKAGE

A

POWER RATING ABOVE TA = 25°C

‡

A

POWER RATINGAPOWER RATINGAPOWER RATING

D 635 mW 5.08 mW/°C 407 mW 330 mW 127 mW
FK 1375 mW 11.00 mW/°C 880 mW 715 mW 275 mW
JG 1050 mW 8.40 mW/°C 672 mW 546 mW 210 mW

‡

This is the inverse of the traditional Junction-to-Ambient thermal Resistance (RΘJA). Thermal Resistances are not production tested and are for
informational purposes only.

recommended operating conditions

MIN NOM MAX UNIT

pp

VDD = 5 V 4.5 5 5.5 V

Suppl

y v

oltage, V

DD

VDD = 3 V 2.7 3 3.3 V
Power on reset, POR *0.55 *2 V
High-level digital input voltage, V

IH

VDD = 2.7 V to 5.5 V 2 V
Low-level digital input voltage, V

IL

VDD = 2.7 V to 5.5 V 0.8 V
Reference voltage, V

ref

to REF terminal VDD = 5 V (see Note 1) AGND 2.048 VDD–1.5 V

Reference voltage, V

ref

to REF terminal VDD = 3 V (see Note 1) AGND 1.024 VDD–1.5 V

Load resistance, R

L

2 kΩ

Load capacitance, C

L

100 pF

Clock frequency, f

CLK

20 MHz

TLV5638C 0 70

p

p

TLV5638I –40 85

°

Operating free-air temperature, T

A

TLV5638Q –40 125

°C

TLV5638M –55 125

*This parameter is not tested for Q and M suffix devices.
NOTE 1: Due to the x2 output buffer , a reference input voltage ≥ (VDD–0.4 V)/2 causes clipping of the transfer function. The output buffer of the

internal reference must be disabled, if an external reference is used.

TLV5638

2.7 V TO 5.5 V LOW POWER DUAL 12-BIT DIGITAL-TO-ANALOG
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electrical characteristics over recommended operating conditions, V

ref

= 2.048 V, V

ref

= 1.024 V

(unless otherwise noted)

power supply

PARAMETER TEST CONDITIONS

TLV5638C,

TLV5638I

TLV5638Q,

TLV5638M

UNIT

MIN TYP MAX MIN TYP MAX

VDD = 5 V,

Fast 4.3 5.2 4.3 5.4

DD

Int. ref.

Slow 2.2 2.7 2.2 2.7

mA

VDD = 3 V,

Fast 3.8 4.7 3.8 4.9

pp

No load

,

All inputs = AGND

DD

Int. ref.

Slow 1.8 2.3 1.8 2.3

mA

IDDPower supply current

or VDD,

VDD = 5 V,

Fast 3.9 4.8 3.9 5.0

DAC latch

= 0x

800

DD

Ext. ref.

Slow 1.8 2.2 1.8 2.2

mA

VDD = 3 V,

Fast 3.5 4.3 3.5 4.5

DD

Ext. ref.

Slow 1.5 1.9 1.5 1.9

mA

Power-down supply current 0.01 10 0.01 10 µA

pp

Zero scale, See Note 2 –65 –65

PSRR

Power supply rejection ratio

Full scale, See Note 3 –65 –65

dB

NOTES: 2. Power supply rejection ratio at zero scale is measured by varying VDD and is given by:

PSRR = 20 log [(EZS(VDDmax) – EZS(VDDmin))/VDDmax]

3. Power supply rejection ratio at full scale is measured by varying VDD and is given by:
PSRR = 20 log [(EG(VDDmax) – EG(VDDmin))/VDDmax]

static DAC specifications

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Resolution 12 bits

p

C and I suffixes ±1.7 ±4 LSB

INL

Integral nonlinearit

y,

end point adjusted

See Note 4

Q and M suffixes ±1.7 ±6 LSB
DNL Differential nonlinearity See Note 5 ±0.4 ±1 LSB
E

ZS

Zero-scale error (offset error at zero scale) See Note 6 ±24 mV

EZS TC Zero-scale-error temperature coefficient See Note 7 10 ppm/°C
E

G

Gain error See Note 8 ±0.6

% full

scale V

EG TCGain error temperature coefficient See Note 9 10 ppm/°C

NOTES: 4. The relative accuracy or integral nonlinearity (INL) sometimes referred to as linearity error, is the maximum deviation of the output

from the line between zero and full scale excluding the effects of zero code and full-scale errors. Tested from code 32 to 4095.

5. The differential nonlinearity (DNL) sometimes referred to as differential error, is the dif ference between the measured and ideal 1
LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains
constant) as a change in the digital input code.

6. Zero-scale error is the deviation from zero voltage output when the digital input code is zero.

7. Zero-scale-error temperature coefficient is given by: EZSTC = [EZS(T

max

) – EZS(T

min

)]/V

ref

× 106/(T

max

– T

min

).

8. Gain error is the deviation from the ideal output (2V

ref

– 1 LSB) with an output load of 10 kΩ excluding the effects of the zero-error .

9. Gain temperature coefficient is given by: EGTC = [EG(T

max

) – EG (T

min

)]/V

ref

× 106/(T

max

– T

min

).

TLV5638

2.7 V TO 5.5 V LOW POWER DUAL 12-BIT DIGITAL-TO-ANALOG

CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN

SLAS225A – JUNE 1999 – REVISED JANUARY 2000

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electrical characteristics over recommended operating conditions, V

ref

= 2.048 V, V

ref

= 1.024 V

(unless otherwise noted) (continued)

output specifications

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

O

Output voltage RL = 10 kΩ 0 VDD–0.4 V
Output load regulation accuracy VO = 4.096 V , 2.048 V, RL = 2 kΩ ±0.25

% full

scale V

reference pin configured as output (REF)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

ref(OUTL)

Low reference voltage 1.003 1.024 1.045 V

V

ref(OUTH)

High reference voltage VDD > 4.75 V 2.027 2.048 2.069 V

I

ref(source)

Output source current 1 mA

I

ref(sink)

Output sink current –1 mA
Load capacitance 100 pF

PSRR Power supply rejection ratio –65 dB

reference pin configured as input (REF)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VIInput voltage 0 V

DD–1.5

V
RIInput resistance 10 MΩ
CIInput capacitance 5 pF

p

Fast 1.3 MHz

Reference input bandwidth

REF

= 0.2

V

pp

+ 1.

024 V dc

Slow 525 kHz

Reference feedthrough REF = 1 Vpp at 1 kHz + 1.024 V dc (see Note 10) –80 dB

NOTE 10: Reference feedthrough is measured at the DAC output with an input code = 0x000.

TLV5638

2.7 V TO 5.5 V LOW POWER DUAL 12-BIT DIGITAL-TO-ANALOG
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electrical characteristics over recommended operating conditions (unless otherwise noted)
(Continued)

digital inputs

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

I

IH

High-level digital input current VI = V

DD

1 µA

I

IL

Low-level digital input current VI = 0 V –1 µA

C

i

Input capacitance 8 pF

analog output dynamic performance

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

p

R

= 10 kΩ,C

= 100 pF,

Fast 1 3

t

s(FS)

Output settling time, full scale

L

,

L

,

See Note 11

Slow 3.5 7

µ

s

p

R

= 10 kΩ,C

= 100 pF,

Fast 0.5 1.5

t

s(CC)

Output settling time, code to code

L

,

L

,

See Note 12

Slow 1 2

µ

s

R

= 10 kΩ,C

= 100 pF,

Fast 12

SR

Slew rate

L

,

L

,

See Note 13

Slow 1.8

V/µs

Glitch energy

DIN = 0 to 1, FCLK = 100 kHz,
CS

= V

DD

5 nV–s

SNR Signal-to-noise ratio 69 74
S/(N+D) Signal-to-noise + distortion

f

= 480 kSPS, f

= 1 kHz,

58 67

THD Total harmonic distortion

s

,

out

,

RL = 10 kΩ,CL = 100 pF

–69 –57

dB

Spurious free dynamic range 57 72

NOTES: 11. Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change

of 0x020 to 0xFDF and 0xFDF to 0x020 respectively. Not tested, assured by design.

12. Settling time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change
of one count. Not tested, assured by design.

13. Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage.

digital input timing requirements

MIN NOM MAX UNIT

t

su(CS–CK)

Setup time, CS low before first negative SCLK edge 10 ns

t

su(C16-CS)

Setup time, 16th negative SCLK edge (when D0 is sampled) before CS rising edge 10 ns

t

wH

SCLK pulse width high 25 ns

t

wL

SCLK pulse width low 25 ns

t

su(D)

Setup time, data ready before SCLK falling edge 10 ns

t

h(D)

Hold time, data held valid after SCLK falling edge 5 ns