Texas Instruments TLC5615IP, TLC5615IDR, TLC5615ID, TLC5615CP, TLC5615CDR Datasheet

...
TLC5615C, TLC5615I
10-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS142C – OCTOBER 1996 – REVISED MARCH 2000
D
10-Bit CMOS Voltage Output DAC in an 8-T erminal Package
D
5-V Single Supply Operation
D
3-Wire Serial Interface
D
High-Impedance Reference Inputs
D
Voltage Output Range ...2 Times the Reference Input Voltage
D
Internal Power-On Reset
D
Low Power Consumption . . . 1.75 mW Max
D
Update Rate of 1.21 MHz
D
Settling Time to 0.5 LSB . . . 12.5 µs Typ
D
Monotonic Over Temperature
D
Pin Compatible With the Maxim MAX515
description
The TLC5615 is a 10-bit voltage output digital-to-analog converter (DAC) with a buffered reference input (high impedance). The DAC has an output voltage range that is two times the reference voltage, and the DAC is monotonic. The device is simple to use, running from a single supply of 5 V. A power-on-reset function is incorporated to ensure repeatable start-up conditions.
applications
D
Battery-Powered T est Instruments
D
Digital Offset and Gain Adjustment
D
Battery Operated/Remote Industrial Controls
D
Machine and Motion Control Devices
D
Cellular Telephones
D, P, OR DGK PACKAGE
(TOP VIEW)
DIN
SCLK
CS
DOUT
1 2 3 4
8 7 6 5
V
DD
OUT REFIN AGND
Digital control of the TLC5615 is over a three-wire serial bus that is CMOS compatible and easily interfaced to industry standard microprocessor and microcontroller devices. The device receives a 16-bit data word to produce the analog output. The digital inputs feature Schmitt triggers for high noise immunity. Digital communication protocols include the SPI, QSPI, and Microwire standards.
The 8-terminal small-outline D package allows digital control of analog functions in space-critical applications. The TLC5615C is characterized for operation from 0°C to 70°C. The TLC5615I is characterized for operation from –40°C to 85°C.
AVAILABLE OPTIONS
PACKAGE
T
A
0°C to 70°C TLC5615CD TLC5615CDGK TLC5615CP
–40°C to 85°C TLC5615ID TLC5615IDGK TLC5615IP
Available in tape and reel as the TLC5615CDR and the TLC5615IDR
SMALL OUTLINE
(D)
PLASTIC SMALL OUTLINE
(DGK)
PLASTIC DIP
(P)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SPI and QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor Corporation.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2000, Texas Instruments Incorporated
1
TLC5615C, TLC5615I
I/O
DESCRIPTION
10-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS142C – OCTOBER 1996 – REVISED MARCH 2000
functional block diagram
_
REFIN
AGND
CS
SCLK
DIN
+
Power-ON
Reset
Control
Logic
DAC
RR
10-Bit DAC Register
2
(LSB) (MSB)
0s
10 Data Bits
16-Bit Shift Register
+ _
2
Dummy
OUT (Voltage Output)
4
Bits
DOUT
Terminal Functions
TERMINAL
NAME NO.
DIN 1 I Serial data input SCLK 2 I Serial clock input CS 3 I Chip select, active low DOUT 4 O Serial data output for daisy chaining AGND 5 Analog ground REFIN 6 I Reference input OUT 7 O DAC analog voltage output V
DD
8 Positive power supply
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage (VDD to AGND) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital input voltage range to AGND – 0.3 V to VDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference input voltage range to AGND – 0.3 V to VDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage at OUT from external source V
Continuous current at any terminal ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, T
: TLC5615C 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A
TLC5615I –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DD
+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Operating free-air temperature, T
PSRR
Power-supply rejection ratio
See Notes 7 and 8
dB
TLC5615C, TLC5615I
10-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS142C – OCTOBER 1996 – REVISED MARCH 2000
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, V High-level digital input voltage, V Low-level digital input voltage, V Reference voltage, V Load resistance, R
p
DD
IH
IL
to REFIN terminal 2 2.048 VDD–2 V
ref
L
p
A
TLC5615C 0 70 °C TLC5615I –40 85 °C
electrical characteristics over recommended operating free-air temperature range, VDD = 5 V ±5%,
= 2.048 V (unless otherwise noted)
V
ref
static DAC specifications
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Resolution 10 bits Integral nonlinearity, end point adjusted (INL) V Differential nonlinearity (DNL) V
E
E
NOTES: 1. The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum deviation of the output
Zero-scale error (offset error at zero scale) V
ZS
Zero-scale-error temperature coefficient V Gain error V
G
Gain-error temperature coefficient V
pp
Analog full scale output RL = 100 k 2V
from the line between zero and full scale excluding the effects of zero code and full-scale errors (see text).
2. The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code.
3. Zero-scale error is the deviation from zero-voltage output when the digital input code is zero (see text).
4. Zero-scale-error temperature coefficient is given by: EZSTC = [EZS(T
5. Gain error is the deviation from the ideal output (V error.
6. Gain temperature coefficient is given by: EGTC = [EG(T
7. Zero-scale-error rejection ratio (EZS-RR) is measured by varying the VDD from 4.5 V to 5.5 V dc and measuring the proportion of this signal imposed on the zero-code output voltage.
8. Gain-error rejection ratio (EG-RR) is measured by varying the VDD from 4.5 V to 5.5 V dc and measuring the proportion of this signal imposed on the full-scale output voltage after subtracting the zero-scale change.
Zero scale Gain
= 2.048 V, See Note 1 ±1 LSB
ref
= 2.048 V, See Note 2 ±0.1 ±0.5 LSB
ref
= 2.048 V, See Note 3 ±3 LSB
ref
= 2.048 V, See Note 4 3 ppm/°C
ref
= 2.048 V, See Note 5 ±3 LSB
ref
= 2.048 V, See Note 6 1 ppm/°C
ref
80 80
) – EZS(T
– 1 LSB) with an output load of 10 kexcluding the effects of the zero-scale
ref
) – EG (T
max
max
min
)]/V
× 106/(T
ref
min
4.5 5 5.5 V
2.4 V
2 k
(1023/1024) V
ref
)]/V
max
× 106/(T
ref
– T
min
– T
max
).
0.8 V
).
min
voltage output (OUT)
V
O
I
OSC
V
OL(low)
V
OH(high)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Voltage output range RL = 10 k 0 VDD–0.4 V Output load regulation accuracy V Output short circuit current OUT to VDD or AGND 20 mA
Output voltage, low-level I Output voltage, high-level I
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O(OUT) O(OUT)
= 2 V, RL = 2 k 0.5 LSB
O(OUT)
5 mA 0.25 V –5 mA 4.75 V
3
TLC5615C, TLC5615I
IDDPower supply current
10-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS142C – OCTOBER 1996 – REVISED MARCH 2000
electrical characteristics over recommended operating free-air temperature range, VDD = 5 V ±5%, V
= 2.048 V (unless otherwise noted) (continued)
ref
reference input (REFIN)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
Input voltage 0 VDD–2 V
I
r
Input resistance 10 M
i
C
Input capacitance 5 pF
i
digital inputs (DIN, SCLK, CS)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
High-level digital input voltage 2.4 V
IH
V
Low-level digital input voltage 0.8 V
IL
I
High-level digital input current VI = V
IH
I
Low-level digital input current VI = 0 ±1 µA
IL
C
Input capacitance 8 pF
i
digital output (DOUT)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
Output voltage, high-level IO = –2 mA VDD–1 V
OH
V
Output voltage, low-level IO = 2 mA 0.4 V
OL
DD
±1 µA
power supply
PARAMETER TEST CONDITIONS MIN TYP MAX
V
Supply voltage 4.5 5 5.5 V
DD
VDD = 5.5 V,
pp
No load, All inputs = 0 V or V
VDD = 5.5 V, No load, All inputs = 0 V or V
DD
DD
V
= 0 150 250 µA
ref
V
= 2.048 V 230 350 µA
ref
analog output dynamic performance
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
= 1 Vpp at 1 kHz + 2.048 Vdc,
ref
Signal-to-noise + distortion, S/(N+D)
NOTE 9: The limiting frequency value at 1 Vpp is determined by the output-amplifier slew rate.
code = 11 1111 111 1, See Note 9
UNIT
60 dB
4
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TLC5615C, TLC5615I
10-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS142C – OCTOBER 1996 – REVISED MARCH 2000
digital input timing requirements (see Figure 1)
PARAMETER MIN NOM MAX UNIT
t
su(DS)
t
h(DH)
t
su(CSS)
t
su(CS1)
t
h(CSH0)
t
h(CSH1)
t
w(CS)
t
w(CL)
t
w(CH)
output switching characteristic
t
pd(DOUT)
operating characteristics over recommended operating free-air temperature range, VDD = 5 V ±5%, V
ref
Setup time, DIN before SCLK high 45 ns Hold time, DIN valid after SCLK high 0 ns Setup time, CS low to SCLK high 1 ns Setup time, CS high to SCLK high 50 ns Hold time, SCLK low to CS low 1 ns Hold time, SCLK low to CS high 0 ns Pulse duration, minimum chip select pulse width high 20 ns
Pulse duration, SCLK low 25 ns Pulse duration, SCLK high 25 ns
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
Propagation delay time, DOUT CL = 50 pF 50 ns
= 2.048 V (unless otherwise noted)
analog output dynamic performance
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SR Output slew rate
t
Output settling time
s
Glitch energy DIN = All 0s to all 1s 5
NOTE 10: Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change of
000 hex to 3FF hex or 3FF hex to 000 hex.
CL = 100 pF, TA = 25°C
To 0.5 LSB, RL = 10 kΩ,
RL = 10 kΩ,
CL = 100 pF, See Note 10
0.3 0.5 V/µs
12.5 µs nVs
reference input (REFIN)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Reference feedthrough REFIN = 1 Vpp at 1 kHz + 2.048 Vdc (see Note 11) –80 dB Reference input
bandwidth (f–3dB)
NOTE 11: Reference feedthrough is measured at the DAC output with an input code = 000 hex and a V
REFIN = 0.2 Vpp + 2.048 Vdc REFIN = 0.2 Vpp + 2.048 Vdc 30 kHz
input = 2.048 Vdc + 1 Vpp at 1 kHz.
ref
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
5
TLC5615C, TLC5615I
ÎÎÎ
ÎÎÎ
10-BIT DIGITAL-TO-ANALOG CONVERTERS
SLAS142C – OCTOBER 1996 – REVISED MARCH 2000
PARAMETER MEASUREMENT INFORMATION
CS
t
h(CSH0)
SCLK
See Note A See Note A
t
su(DS)
DIN
t
pd(DOUT)
DOUT
See Note B
NOTES: A. The input clock, applied at the SCLK terminal, should be inhibited low when CS is high to minimize clock feedthrough.
B. Data input from preceeding conversion cycle. C. Sixteenth SCLK falling edge
Previous LSB
t
su(CSS)
t
w(CH)
t
h(DH)
t
w(CS)
t
w(CL)
MSB LSB
t
h(CSH1)
t
See Note C
su(CS1)
Figure 1. Timing Diagram
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