Texas Instruments TLC320AD81CDBT Datasheet

TLC320AD81C

Stereo Audio Digital Equalizer DAC

Data Manual

1999 Mixed Signal Linear Products

Printed in U.S.A.
03/99

SLAS203

TLC320AD81C

Stereo Audio Digital Equalizer DAC

SLAS203

March 1999

Printed on Recycled Paper

IMPORTANT NOTICE

T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO
BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
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party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

Copyright  1999, Texas Instruments Incorporated

Contents

Section Title Page

1 Introduction 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.1 Features 1–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2 Functional Block Diagram 1–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3 Terminal Assignments 1–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4 Ordering Information 1–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.5 Terminal Functions 1–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 Description 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 Serial Audio Interface 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2 Audio Processing 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3 Power Supply 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4 DAC 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5 Serial Audio Interface 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5.1 I

2.5.2 Protocol 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5.3 Implementation 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5.4 Timing 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6 Left-Justified Serial Format 2–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6.1 Protocol 2–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6.2 Implementation 2–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6.3 Timing 2–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.7 Right-Justified Serial Format 2–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.7.1 Protocol 2–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.7.2 Implementation 2–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.7.3 Timing 2–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.8 Serial Control Interface 2–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.8.1 I

2.8.2 Operation 2–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.9 Filter Processor 2–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.9.1 Biquad Block 2–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.9.2 Filter Coefficients 2–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.10 Volume Control Functions 2–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.10.1 Soft Volume Update 2–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.10.2 Software Soft Mute 2–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.10.3 Hardware Soft Mute 2–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.10.4 Mixer Control 2–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.10.5 Treble Control 2–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.10.6 Bass Control 2–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.10.7 De-Emphasis (DM) 2–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 1 Device Initialization 2–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 1.1 Reset 2–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2

S Serial Format 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2

C Protocol 2–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

iii

2.11.2 Device Power On Plus Reset 2–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.3 Fast Load 2–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3 Specifications 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1 Absolute Maximum Ratings Over Operating Free-air Temperature Range 3–1. . . . .

3.2 Recommended Operating Conditions 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3 Static Digital Specifications, T

= 0°C to 70°C, all VDD = 3.3 V + 0.3 V 3–1. . . . . . . .

A

3.4 DAC Performance Characteristics, TA = 25°C, AVDD_DAC = 5 V,

All Other VDD = 3.3 V, fs = 44.1 kHz 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5 Audio Serial Port Timing Requirements 3–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2

3.6 I

C Serial Port Timing Requirements 3–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4 Parameter Measurement Information 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5 T ypical Characteristics 5–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6 Application Information 6–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.1 Audio Data 6–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Appendix A Software Interface A–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Appendix B Mechanical Data B–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

iv

List of Illustrations

Figure Title Page

2–1 I2S Compatible Serial Format 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–2 Left-Justified Serial Format 2–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–3 Right-Justified Serial Format 2–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–4 Typical I2C Data Transfer Sequence 2–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–5 Biquad Cascade Configuration 2–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–6 Main Control Register 2–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2

4–1 I

S Timing 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–2 I2C Timing 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–1 Example USB Audio System 6–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–2 Example SPDIF Audio System 6–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

List of Tables

Table Title Page

2–1 I2C Address Byte 2–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

v

vi

1 Introduction

The TLC320AD81C performs standard audio signal processing for bass, treble, and volume, as well as
parametric equalization on a digital audio stream resulting in superior quality audio normally not available
in a low-cost solution. The TLC320AD81C contains a digital audio processor , a slave I
a sigma-delta digital-to-analog converter (DAC). The audio control functions (volume, treble, and bass,) and

2

parametric EQ coefficients are downloaded through the I

C port to the TLC320AD81C.

The volume, treble, and bass controls may be dynamically adjusted by the user. They are updated within
the device without degradation of the output signal.

The parametric EQ consists of multiple cascaded independent biquad filters per channel. Each biquad has

2

five 24-bit coefficients that can be downloaded across the I

C port. The parametric EQ should not be
updated while digital audio data is being processed, because the update will possibly cause audible
artifacts.

The digital audio processor and on-chip logic use an internal system clock that is generated by the PLL from
the system clock provided to the device at the master clock input.

The TLC320AD81C supports three audio serial interface formats (I
data word lengths of 16, 18, and 20 bits (16-bit, 32 f
frequency may be set to 44.1 kHz or 48 kHz. An I

mode is only supported by left justified). The sampling

s

2

C slave port is used to download filter coefficients and

2

S, left justified, and right justified) with

control information to the TLC320AD81C.
Additionally, two address-select pins allow multiple TLC320AD81Cs to be cascaded on the I

support left, right, and sub (3-channel) systems or left, right, center, rear left, rear right, and sub (6-channel)
systems.

The sigma-delta DAC has 64x oversampling. Typically, the DAC also has a 98-dB signal-to-noise ratio
(SNR) and a 94-dB dynamic range at 5 V. Hardware control for de-emphasis is supported for CD
applications at 44.1 kHz. Hardware control for soft mute is also provided.

2

C interface port, and

2

C bus to

1–1

1.1 Features

• Stereo Sigma-Delta D/A Converter

• 98-dB Signal-to-Noise Ratio (SNR) Typical

• 94-dB Dynamic Range Typical

• Optional 5-V Analog Power Supply for DAC Output (1 Vrms)

• De-Emphasis Supported at 44.1 kHz for CD Applications

• Programmable Audio Serial Port

• Dual Input Data Channels (SDIN1 and SDIN2)

• Single Digital Output Data Channel (SDOUT)

• Programmable Digital Mixer

• Programmable Multi-Band Digital Parametric EQ

• Programmable Digital Bass and Treble Control (dynamically updateable)

• Programmable Digital Volume Control (dynamically updateable)

2

• Serial I

• Two I

• Supports 2 speaker, 3 speaker

• Soft Mute (hardware pin control and software control)

C Slave Port Allows Downloading of Control Data to the Device

2

C Address Pins Allow Cascading of Multiple Devices on the I2C Bus

†

, and 6 (5.1) speaker† systems

• Single 3.3-V Power Supply Operation

• 38-Pin TSSOP Package

• External Analog-to-Digital Converter Supported

†

Requires multiple TLC320AD81C devices

1.2 Functional Block Diagram

Multi Band EQTREBBASSVOL

TLC320AD81C

Σ

1–2

Audio Serial Interface

SCLK

SDIN1

LRCLK

SDIN2

SDOUT

PLL

MCLK

PLL-FLT

Digital
Filters

I2C Slave

SCL

SDA

SMUTEDM

∆Σ

Modulator

CS1

CS2

RESET

CAP V

DAC

REF

OUT_L
OUT_R

1.3 Terminal Assignments

SDOUT

LRCLK

AV

SS

AV

DD

PLL-FLT
RESERVED
RESERVED

RESET

CAP_V

OUT_R

AV

SS

DV

SS

NC – No internal connection

1.4 Ordering Information

1

MCLK

SCLK

_PLL
_PLL

_DAC
_DAC

2
3
4
5
6
7
8
9
10

NC

11

NC

12

NC

13
14

REF

NC

15
16

NC

17
18
19

PACKAGE

T

A

0°C to 70°C TLC320AD81CDBT

SMALL OUTLINE

(DBT)

38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20

SDIN2
SDIN1
SCL
SDA
DV

DD

DV

SS

CS2
CS1
RESERVED
DM
NC
NC
NC
SMUTE
NC
NC
OUT_L
AV

_DAC

DD

DV

_DAC

DD

1–3

1.5 Terminal Functions

I/O

DESCRIPTION

TERMINAL

NAME NO.

AVDD_DAC 21 I Analog power supply for the DAC
AVDD_PLL 6 I Analog power supply for the PLL
AVSS_DAC 18 I Analog ground for the DAC
AVSS_PLL 5 I Analog ground for the PLL
CAP_V

REF

CS1 31 I I2C address bit A0; low = 0, high = 1
CS2 32 I I2C address bit A1; low = 0, high = 1

DM 29 I
DV

DD

DVDD_DAC 20 I Digital power supply for the DAC
DV

SS

DVSS_DAC 19 I Digital ground for the DAC
LRCLK 3 I Serial audio left/right clock sampling frequency (fs)
MCLK 2 I Master clock

NC
OUT_L 22 O Analog output voltage left channel

OUT_R 16 O Analog output voltage right channel
PLL–FL T 7 O C1 = 1500 pF // R1 = 27.4 Ω + C2 = 0.068 µF (recommended values)
RESERVED 8, 9, 30 For internal use only, must be connected to GND
RESET 10 I Reset, low = current state, high = reinitialized the device
SCL 36 I/O Slave serial I2C clock
SCLK 4 I Shift clock (bit clock)
SDA 35 I/O Slave serial I2C data
SDIN1 37 I Serial audio data input one
SDIN2 38 I Serial audio data input two
SDOUT 1 O Serial audio data output

SMUTE 25 I

†

If only one capacitor is used, a 10-µF capacitor connected to AVSS_DAC should be used.

14 O 10 µF // 0.1 µF to AVSS_DAC (recommended values)

De-emphasis at 44.1 kHz; off when pin low , on when pin high (default = on
when pin not driven or biased)

34 I Digital power supply

33 I Digital ground

11–13 15, 17,

23, 24 26–28

No connection

Soft mute off when pin low; on when pin high (default = off when pin not
driven or biased)

†

1–4

2 Description

2.1 Serial Audio Interface

• Programmable audio serial port

2

S, left justified, and right justified

–I

• Dual input data channels (SDIN1 and SDIN2)
– 16-,18-, or 20-bit resolution (see section 6.1,

• Single output data channel (SDOUT)
– 16-,18-, or 20-bit resolution (see section 6.1,

• Accepts 32 f

• I2C slave port

2

• Two I

C programmable address pins (CS1 and CS2)

or 64 fs (SCLK)

s

†

Audio Data

Audio Data

2.2 Audio Processing

• Programmable multi band digital parametric EQ (updateable)

• Programmable volume control (dynamically updateable)

• Soft mute software controlled

• Digital mixing of SDIN1 and SDIN2 with independent gain control

• Programmable bass and treble tone control (dynamically updateable)

• De-emphasis supported for CD applications at 44.1 kHz

2.3 Power Supply

• Digital supply voltage – DVDD, DVSS of 3.3 V

• Digital supply voltage – DV

• Analog supply voltage – AV

• Analog supply voltage – AV

_DAC, DVSS_DAC of 3.3 V

DD

_PLL, A VSS_PLL of 3.3 V

DD

_DAC, AVSS_DAC of 5 V or 3.3 V

DD

)

)

2.4 DAC

• Stereo sigma-delta D/A converter

• 98-dB signal-to-noise ratio (SNR) typical

• 94-dB dynamic range typical

• Soft mute hardware control pin

• De-emphasis hardware control pin (44.1 kHz)

• 0.6 Vrms at AV

†

32 fs serial input mode is left justified 16 bit only

= 3.3 V or 1 Vrms at AVDD = 5 V analog output

DD

2–1

2.5 Serial Audio Interface

2.5.1 I

2

S Serial Format

SCLK

LRCLK = f

SDOUT

SDIN

s

MSB

X

MSBX

Left Channel Right Channel

LSB

LSB

MSBX

MSBX

Figure 2–1. I2S Compatible Serial Format

2.5.2 Protocol

1. LRCLK = Sampling frequency (fs)

2. Left channel is transmitted when LR is low

3. SCLK = 64 × LRCLK. SCLK is sometimes referred to as the bit clock.

4. Serial data is sampled with the rising edge of SCLK.

5. Serial data is transmitted on the falling edge of SCLK.

6. LRCLK must have a 50% duty cycle

2.5.3 Implementation

1. LRCLK and SCLK are both inputs

2.5.4 Timing

See Figure 4–1 for I2S timing.

LSB

LSB

2–2

2.6 Left-Justified Serial Format

SCLK

LRCLK = f

SDIN

SDOUT

s

MSB

MSB

LSB

LSB

Left Channel Right Channel

MSB

MSB

LSB

LSB

Figure 2–2. Left-Justified Serial Format

2.6.1 Protocol

1. LRCLK = Sampling frequency (fs)

2. Left channel is transmitted when LRCLK is high

3. The SDIN1 data is justified to the leading edge of the LRCLK

4. Serial data is sampled on the rising edge of SCLK

5. Serial data is transmitted on the falling edge of SCLK

6. SCLK = 32 LRCLK (32 f

SCLK is only supported for 16 bit data) or 64 LRCLK

s

7. In this mode, LRCLK does not have to be a 50% duty cycle clock. The number of bits used in the
interface sets the minimum duty cycle. There must be enough SCLK pulses to shift all of the data.

2.6.2 Implementation

1. LRCLK and SCLK are both inputs

2.6.3 Timing

See Figure 4–1 for I2S timing.

2–3