Texas Instruments TLC320AD77CDB Datasheet
TLC320AD77C
24ĆBit 96 kHz Stereo Audio Codec
Data Manual
1999 Mixed Signal Linear Products
Printed in U.S.A.
08/99
SLAS194
TLC320AD77C
24-Bit 96 kHz Stereo Audio Codec
Data Manual
SLAS194
August1999
Printed on Recycled Paper
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
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Copyright 1999, Texas Instruments Incorporated
Contents
Section Title Page
1 Introduction 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 Features 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Functional Block Diagram 1–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Terminal Assignments 1–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 Ordering Information 1–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 Terminal Functions 1–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Functional Description 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1 ADC Channel 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 DAC Channel 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3 Serial Interface 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4 Sampling Frequency 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5 Speed Mode Options 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6 Voltage Reference 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7 ADC Analog Input 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.8 DAC Analog Output 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.9 Sigma-Delta ADC 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.10 Decimation Filter 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.11 Sigma-Delta DAC 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.12 Interpolation Filter 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.13 De-emphasis 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.14 Serial Interface Formats 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.14.1 MSB First Right/Left Justified Format 2–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.14.2 IIS-Compatible Serial Format 2–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.14.3 MSB Left Justified Serial Interface Format 2–4. . . . . . . . . . . . . . . . . . . . . . . . .
2.14.4 DSP Compatible Serial Interface Format 2–5. . . . . . . . . . . . . . . . . . . . . . . . . . .
2.15 Sampling Frequency Ranges 2–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.16 Power Sequences 2–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.16.1 Initial Power Up 2–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.16.2 Power Down/Reset 2–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.16.3 Reinitialization Sequence 2–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.17 DAC De-Emphasis Filter 2–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.17.1 De-Emphasis Selection 2–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Specifications 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range 3–1. . . . .
3.2 Recommended Operating Conditions, T
AVDD = DVDD = 3.3 V ± 10%, fs = 44.1 kHz 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 Electrical Characteristics, TA = 25°C, AVDD = DVDD = 3.3 V ± 10%,
fs = 44.1 kHz 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.1 Static Digital Specifications, T
AVDD = DVDD = 3.3 V ± 10% 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
= 25°C,
A
= 25°C,
A
iii
3.3.2 ADC Digital Filter, TA = 25°C, AVDD = DVDD = 3.3 V ± 10%,
fs = 44.1 kHz 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.3 Analog-to-Digital Converter,
T
= 25°C, AVDD = DVDD = 3.3 V, fs = 44.1 kHz 3–2. . . . . . . . . . . . . . . . . . . .
3.3.4 DAC Interpolation Filter, TA = 25°C, AVDD = DVDD = 3.3 V + 10%,
3.3.5 Digital-to-Analog Converter, TA = 25°C, AVDD = 3.3 V, fs = 44.1 kHz,
3.3.6 Output Performance Data T
3.4 Serial Interface Switching Characteristics,
TA = 25°C, AVDD = DVDD = 3.3 V ± 10% 3–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5 DSP Serial Interface Switching Characteristics,
TA = 25°C, AVDD = DVDD = 3.3 V ± 10% 3–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 Parameter Measurement Information 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 Application Information 5–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1 Single-Ended to Differential External Analog
Front-End Circuit (f
5.1 External Analog Back-End Circuit (fs = 44.1 kHz) 5–2. . . . . . . . . . . . . . . . . . . . . . . . . .
Appendix A Mechanical Data A–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A
fs = 44.1 kHz 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input = 1 V
Sine Wave at 1 kHz 3–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
rms
= 44.1 kHz) 5–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
s
= 25°C, AVDD = DVDD = 3.3 V ± 10% 3–3. . . .
A
List of Illustrations
Figure Title Page
2–1 MSB First Right/Left Justified (for 16-, 20-, and 24-bits) 2–3. . . . . . . . . . . . . . . . . . . . . . . . .
2–2 IIS-Compatible Serial Format (for 16-, 20-, and 24-bits) 2–4. . . . . . . . . . . . . . . . . . . . . . . . .
2–3 MSB Left Justified Serial Interface Format (for 16-bits) 2–4. . . . . . . . . . . . . . . . . . . . . . . . . .
2–4 DSP Compatible Serial Interface Format (for 16-bits) 2–5. . . . . . . . . . . . . . . . . . . . . . . . . . .
2–5 De-Emphasis Characteristics 2–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–1 Master Clock Timing 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–2 Right/Left Justified, IIS, Left/Left Justified Serial Protocol Timing 4–1. . . . . . . . . . . . . . . . .
4–3 DSP Serial Port Timing 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–4 DAC Filter Overall Frequency Characteristics 4–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–5 DAC Digital Filter Passband Ripple Characteristics 4–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–6 ADC Digital Filter Characteristics 4–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–7 ADC Digital Filter Stopband Characteristics 4–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–8 ADC Digital Filter Passband Characteristics 4–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–9 ADC High Pass Filter Characteristics 4–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–1 Analog Front End (right channel) for 0.7 Vrms Input 5–1. . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–2 Analog Back End (right channel) for 0.7 Vrms Output 5–2. . . . . . . . . . . . . . . . . . . . . . . . . . .
5–3 Voltage Reference Connections 5–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Tables
Table Title Page
2–1 Example Master Clock Frequency Rates 2–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iv
1 Introduction
The TLC320AD77C is a cost competitive stereo analog-to-digital (A/D) and digital-to-analog (D/A) 24-bit
delta-sigma converter for consumer applications which demand excellent audio performance. It has a wide
variety of serial input options including left justified, right justified, IIS, or DSP data formats for 16-, 20-, or
24-bit input/output data. It has an extremely wide range of sampling rates starting at 16 kHz and increasing
upwards to 96 kHz. Its internal bandgap design provides a very clean voltage reference. The TLC320AD77C
is primarily designed for mini-disks, audio/video receivers, musical instruments, and other end-equipments
requiring high-performance digital audio conversion.
1.1 Features
• 24-Bit Delta Sigma Stereo ADC and DAC:
– 16-, 20-, or 24-Bit Input/Output Data
– Wide Range of Sampling Rates: 16 kHz to 96 kHz
– Master Clock: 256 f
– 3.3-V Power Supply Operation
– Internal Bandgap Voltage Reference
– Economical 28-Pin DB (SSOP) Package
• Stereo ADC:
– Differential Input
– 128× Oversampling (in normal speed mode)
– High Performance: 100-dB Signal-to-Noise Ratio (SNR) (EIAJ), 100-dB Dynamic Range
– Digital High-Pass Filter
• Stereo DAC:
– Single-Ended Output
– 128× Oversampling (in normal speed mode)
– High Performance: 100-dB Signal-to-Noise Ratio (SNR) (EIAJ), 100-dB Dynamic Range
• Digital De-Emphasis:
– 32-kHz, 44.1-kHz, and 48-kHz Selection
• Special Features:
– High Jitter Tolerance
– Good Phase Characteristics
– Excellent Power Supply Rejection Ratio
or 384 f
s
s
1–1
1.2 Functional Block Diagram
AV
SS(REF)
VCOM VREFM VREFP VRFILT
ADC/DAC
Voltage Reference
AINRP
AINRM
AINLP
AINLM
AOUTR
AOUTL
Modulator
Modulator
Analog
LPF
Analog
LPF
ADC
ADC
Decimation
Decimation
Digital
Modulator
Digital
Modulator
ADC
Filter
ADC
Filter
DAC
Interpolation
Filter
De-Emphasis
DAC
Interpolation
Filter
De-Emphasis
DEM0
ADC
HPF
ADC
HPF
DEM1
Serial
Port
I/O
Interface
Control
Clock
Generator
SDOUT
SDIN
SCLK
LRCLK
MOD0
MOD1
MOD2
PDN_RSTB
SPDMODE
TEST
MCLK
1–2
1.3 Terminal Assignments
DB PACKAGE
(TOP VIEW)
1.4 Ordering Information
AINLM
AINLP
VREFP
VREFM
VRFILT
AV
SS(REF)
AV
MOD2
MOD1
MOD0
DV
SDIN
SDOUT
SCLK
0°C to 70°C TLC320AD77C
T
SS
SS
A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
AINRM
28
AINRP
27
AOUTR
26
VCOM
25
AOUTL
24
AV
23
TEST
22
SPDMODE
21
PDN_RSTB
20
DEM1
19
DEM0
18
DV
17
16
LRCLK
15
MCLK
PACKAGE
SMALL OUTLINE
DD
DD
(DB)
1–3
1.5 Terminal Functions
I/O
DESCRIPTION
TERMINAL
NAME NO.
AINLM 1 I ADC analog differential negative input, left channel
AINLP 2 I ADC analog differential positive input, left channel
AINRM 28 I ADC analog differential negative input, right channel
AINRP 27 I ADC analog dif ferential positive input, right channel
AOUTL 24 O DAC analog output, left channel
AOUTR 26 O DAC analog output, right channel
AV
DD
AV
SS
AV
SS(REF)
DEM0 18 I De-emphasis selection
DEM1 19 I De-emphasis selection
DV
DD
DV
SS
LRCLK 16 I Left/right clock
MCLK 15 I Master clock
MOD0 10 I Serial interface selection
MOD1 9 I Serial interface selection
MOD2 8 I Serial interface selection
PDN_RSTB 20 I Power down/reset
SCLK 14 I Shift or bit clock
SDIN 12 I Serial data DAC input
SDOUT 13 O Serial data ADC output
SPDMODE 21 I Sampling frequency selection
TEST 22 Reserved, manufacturing test pin. Test should be connected to DVSS.
VCOM 25 O Common mode reference, provides a 1.5-V reference voltage (DAC only)
VREFM 4 O ADC/DAC negative reference voltage
VREFP 3 O ADC/DAC positive reference voltage
VRFILT 5 O Voltage reference low pass noise filter
23 Analog voltage supply
7 Analog voltage ground
6 I Analog ground voltage reference
17 Digital voltage supply
11 Digital ground
1–4
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