Texas Instruments TL16C754BPNR, TL16C754BPN, TL16C754BFN Datasheet

TL16C754B

QUAD UART WITH 64-BYTE FIFO

SLLS397 – NOVEMBER 1999

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

ST16C654 Pin Compatible With Additional
Enhancements

D

Supports Up To 24-MHz Crystal Input Clock
( 1.5 Mbps)

D

Supports Up To 48-MHz Oscillator Input
Clock ( 3 Mbps) for 5-V Operation

D

Supports Up To 32-MHz Oscillator Input
Clock ( 2 Mbps) for 3.3-V Operation

D

64-Byte Transmit FIFO

D

64-Byte Receive FIFO With Error Flags

D

Programmable and Selectable Transmit and
Receive FIFO Trigger Levels for DMA and
Interrupt Generation

D

Programmable Receive FIFO Trigger Levels
for Software/Hardware Flow Control

D

Software/Hardware Flow Control
– Programmable Xon/Xoff Characters
– Programmable Auto-RTS

and Auto-CTS

D

Optional Data Flow Resume by Xon Any
Character

D

DMA Signalling Capability for Both
Received and Transmitted Data

D

Supports 3.3-V or 5-V Supply

D

Characterized for Operation From –40°C to
85°C

D

Software Selectable Baud Rate Generator

D

Prescalable Provides Additional Divide by 4
Function

D

Fast Access 2 Clock Cycle IOR/IOW Pulse
Width

D

Programmable Sleep Mode

D

Programmable Serial Interface
Characteristics
– 5, 6, 7, or 8-Bit Characters
– Even, Odd, or No Parity Bit Generation

and Detection

– 1, 1.5, or 2 Stop Bit Generation

D

False Start Bit Detection

D

Complete Status Reporting Capabilities in
Both Normal and Sleep Mode

D

Line Break Generation and Detection

D

Internal Test and Loopback Capabilities

D

Fully Prioritized Interrupt System Controls

D

Modem Control Functions (CTS, RTS, DSR,
DTR

, RI, and CD)

22 23

NC
DSRD
CTSD
DTRD
GND
RTSD
INTD
CSD
TXD
IOR
TXC
CSC
INTC
RTSC
V

CC

DTRC
CTSC
DSRC
NC
NC

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41

24

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

NC
NC

DSRA

CTSA

DTRA

V

CC

RTSA

INTA

CSA

TXA
IOW
TXB

CSB

INTB

RTSB

GND

DTRB

CTSB

DSRB

NC

25 26 27 28

PN PACKAGE

(TOP VIEW)

D2

79 78 77 76 7580 74

RIA

RXA

GNDD7D6D5D4

XTAL1

RESET

CDB

RIB

RXB

CLKSEL

NC

A2

A1

72 71 7073

29

30 31 32 33

69 68

21

NC

D0

67 6665 64

34 35 36 37

RXRDY

TXRDY

GND

RXC

INTSEL

RXD

RID

NC

CDA

RIC

CDC

38 39 40

CDD

NC

63 62 61

V

CC

D1

NC

NC

XTAL2

NC

A0

D3

NC – No internal connection

TL16C754BPN

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Copyright  1999, Texas Instruments Incorporated

TL16C754B
QUAD UART WITH 64-BYTE FIFO

SLLS397 – NOVEMBER 1999

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

28 29

DSRD
CTSD
DTRD
GND
RTSD
INTD
CSD
TXD
IOR
TXC
CSC
INTC
RTSC
VCC
DTRC
CTSC
DSRC

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44

30

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

DSRA

CTSA

DTRA

VCC

RTSA

INTA

CSA

TXA
IOW
TXB

CSB

INTB

RTSB

GND

DTRB

CTSB

DSRB

31 32 33 34

D2

D1

87 6 5493

RXA

GNDD7D6D5D4

D3

XTAL2

RESET

RXRDY

TXRDY

RXB

CLKSEL

NC

A2A1A0

XTAL1

168672

35 36 37 38 39

66 65

27

CDB

RIB

D0

INTSEL

64 63 62 61

40 41 42 43

GND

RXC

RIC

CDC

VCC

RXD

RID

CDD

CDA

RIA

FN PACKAGE

(TOP VIEW)

TL16C754BFN

NC – No internal connection

description

The TL16C754B is a quad universal asynchronous receiver/transmitter (UART) with 64-byte FIFOs, automatic
hardware/software flow control, and data rates up to 3 Mbps. The TL16C754B offers enhanced features. It has
a transmission control register (TCR) that stores received FIFO threshold level to start/stop transmission during
hardware and software flow control. With the FIFO RDY register, the software gets the status of TXRDY/RXRDY
for all four ports in one access. On-chip status registers provide the user with error indications, operational
status, and modem interface control. System interrupts may be tailored to meet user requirements. An internal
loopback capability allows onboard diagnostics.

The UART transmits data sent to it from the peripheral 8-bit bus on the TX signal and receives characters on
the RX signal. Characters can be programmed to be 5, 6, 7, or 8 bits. The UART has a 64-byte receive FIFO
and transmit FIFO and can be programmed to interrupt at different trigger levels. The UART generates its own
desired baud rate based upon a programmable divisor and its input clock. It can transmit even, odd, or no parity
and 1, 1.5, or 2 stop bits. The receiver can detect break, idle or framing errors, FIFO overflow, and parity errors.
The transmitter can detect FIFO underflow. The UART also contains a software interface for modem control
operations, and software flow control and hardware flow control capabilities.

The TL16C754B is available in 80-pin TQFP and 68-pin PLCC packages.

TL16C754B

QUAD UART WITH 64-BYTE FIFO

SLLS397 – NOVEMBER 1999

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions

TERMINAL

NO.

I/O DESCRIPTION

NAME

PN FN

A0 30 34 I Address bit 0 select. Internal registers address selection. Refer to T able 7 for Register Address Map.
A1 29 33 I Address bit 1 select. Internal registers address selection. Refer to T able 7 for Register Address Map
A2 28 32 I Address bit 2 select. Internal registers address selection. Refer to T able 7 for Register Address Map
CDA, CDB

CDC, CDD

79, 23
39, 63

9, 27

43, 61

I

Carrier detect (active low). These inputs are associated with individual UART channels A through
D. A low on these pins indicates that a carrier has been detected by the modem for that channel.

CLKSEL 26 30 I

Clock select. CLKSEL selects the divide-by-1 or divide-by-4 prescalable clock. During the reset,
a logic 1 (VCC) on CLKSEL selects the divide-by-1 prescaler . A logic 0 (GND) on CLKSEL selects
the divide-by-4 prescaler. The value of CLKSEL is latched into MCR[7] at the trailing edge of RESET.
A logic 1 (VCC) on CLKSEL will latch a 0 into MCR[7]. A logic 0 (GND) on CLKSEL will latch a 1 into
MCR[7]. MCR[7] can be changed after RESET to alter the prescaler value.

CSA, CSB
CSC, CSD

9, 13,

49, 53

16, 20,

50, 54

I

Chip select A, B, C, and D (active low). These pins enable data transfers between the user CPU
and the TL16C754B for the channel(s) addressed. Individual UART sections (A, B, C, D) are
addressed by providing a low on the respective CSA

through CSD pin.

CTSA, CTSB
CTSC, CTSD

4, 18

44, 58

11, 25
45, 59

I

Clear to send (active low). These inputs are associated with individual UART channels A through
D. A low on the CTS pins indicates the modem or data set is ready to accept transmit data from the
754A. Status can be checked by reading MSR bit 4. These pins only affect the transmit and receive
operations when auto CTS function is enabled through the enhanced feature register (EFR) bit 7,
for hardware flow control operation.

D0–D2
D3–D7

68–70,

71–75

66–68,

1–5

I/O

Data bus (bidirectional). These pins are the eight bit, 3-state data bus for transferring information
to or from the controlling CPU. D0 is the least significant bit and the first data bit in a transmit or
receive serial data stream.

DSRA, DSRB
DSRC, DSRD

3, 19

43, 59

10, 26
44, 60

I

Data set ready (active low). These inputs are associated with individual UART channels A through
D. A low on these pins indicates the modem or data set is powered on and is ready for data exchange
with the UART.

DTRA, DTRB
DTRC, DTRD

5, 17

45, 57

12, 24
46, 58

O

Data terminal ready (active low). These outputs are associated with individual UART channels A
through D. A low on these pins indicates that the 754A is powered on and ready. These pins can
be controlled through the modem control register. Writing a 1 to MCR bit 0 sets the DTR

output to
low, enabling the modem. The output of these pins is high after writing a 0 to MCR bit 0, or after a
reset.

GND

16, 36,

56, 76

6, 23,

40, 57

Pwr Signal and power ground

INTA, INTB
INTC, INTD

8, 14,

48, 54

15, 21,

49, 55

O

Interrupt A, B, C, and D (active high). These pins provide individual channel interrupts, INTA-D.
INTA–D are enabled when MCR bit 3 is set to a 1, interrupts are enabled in the interrupt enable
register (IER) and when an interrupt condition exists. Interrupt conditions include: receiver errors,
available receiver buffer data, transmit buffer empty, or when a modem status flag is detected.
INTA–D are in the high-impedance state after reset.

INTSEL 67 65 I

Interrupt select (active high with internal pulldown). INTSEL can be used in conjunction with MCR
bit 3 to enable or disable the 3-state interrupts INTA-D or override MCR bit 3 and force continuous
interrupts. Interrupt outputs are enabled continuously by making this pin a 1. Driving this pin low
allows MCR bit 3 to control the 3-state interrupt output. In this mode, MCR bit 3 is set to a 1 to enable
the 3-state outputs.

IOR 51 52 I

Read input (active low strobe). A valid low level on IOR will load the contents of an internal register
defined by address bits A0–A2 onto the TL16C754B data bus (D0–D7) for access by an external
CPU.

IOW 11 18 I

Write input (active low strobe). A valid low level on IOW will transfer the contents of the data bus
(D0–D7) from the external CPU to an internal register that is defined by address bits A0–A2.

TL16C754B
QUAD UART WITH 64-BYTE FIFO

SLLS397 – NOVEMBER 1999

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Terminal Functions (Continued)

TERMINAL

NO.

I/O DESCRIPTION

NAME

PN FN

RESET 33 37 I

Reset. RESET will reset the internal registers and all the outputs. The UART transmitter output
and the receiver input will be disabled during reset time. See TL16C754B external reset
conditions for initialization details. RESET is an active high input.

RIA, RIB
RIC, RID

78, 24
38, 64

8, 28

42, 62

I

Ring indicator (active low). These inputs are associated with individual UART channels A through
D. A low on these pins indicates the modem has received a ringing signal from the telephone line.
A low to high transition on these input pins generates a modem status interrupt, if it is enabled.

RTSA, RTSB
RTSC, RTSD

7, 15

47, 55

14, 22
48, 56

O

Request to send (active low). These outputs are associated with individual UART channels A
through D. A low on the RTS

pins indicates the transmitter has data ready and waiting to send.
Writing a 1 in the modem control register (MCR bit 1) sets these pins to low, indicating data is
available. After a reset, these pins are set to 1. These pins only affects the transmit and receive
operation when auto RTS function is enabled through the enhanced feature register (EFR) bit 6,
for hardware flow control operation.

RXA, RXB
RXC, RXD

77, 25
37, 65

7, 29

41, 63

I

Receive data input. These inputs are associated with individual serial channel data to the 754A.
During the local loopback mode, these RX input pins are disabled and TX data is internally
connected to the UART RX input internally.

RXRDY 34 38 O

Receive ready (active low). RXRDY contains the wire-ORed status of all four receive channel
FIFOs, RXRDY A–D. It goes low when the trigger level has been reached or a timeout interrupt
occurs. It goes high when all RX FIFOs are empty and there is an error in RX FIFO.

TXA, TXB
TXC, TXD

10, 12
50, 52

17, 19
51, 53

O

Transmit data. These outputs are associated with individual serial transmit channel data from the
754A. During the local loopback mode, the TX input pin is disabled and TX data is internally
connected to the UART RX input.

TXRDY 35 39 O

Transmit ready (active low). TXRDY contains the wire-ORed status of all four transmit channel
FIFOs, TXRDY A–D. It goes low when there are a trigger level number of spares available. It goes
high when all four TX buffers are full.

V

CC

6, 46,6613, 47,

64

Pwr Power supply inputs

XTAL1 31 35 I

Crystal or external clock input. XTAL1 functions as a crystal input or as an external clock input.
A crystal can be connected between XTAL1 and XTAL2 to form an internal oscillator circuit (see
Figure 10). Alternatively, an external clock can be connected to XTAL1 to provide custom data
rates.

XTAL2 32 36 O

Output of the crystal oscillator or buffered clock. See also XTAL1. XTAL2 is used as a crystal
oscillator output or buffered clock output.

TL16C754B

QUAD UART WITH 64-BYTE FIFO

SLLS397 – NOVEMBER 1999

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional block diagram

Control Signals

Modem Control Signals

Divisor

Bus

Interface

Control

and

Status Block

Status Signals

Control Signals

Status Signals

Baud-Rate

Generator

UART_CLK

Receiver Block

Logic

Receiver FIFO

64-Byte

Vote

Logic

Transmitter Block

Logic

Transmitter FIFO

64-Byte

RX

RX

TX

TX

NOTE: The Vote logic determines whether the RX data is a logic 1 or 0. It takes three samples of the RX line and uses a majority vote to determine

the logic level received. The Vote logic operates on all bits received.

functional description

The TL16C754B UART is pin compatible with the TL16C554 and ST16C654 UART s. It provides more enhanced
features. All additional features are provided through a special enhanced feature register.

The UART will perform serial-to-parallel conversion on data characters received from peripheral devices or
modems and parallel-to-parallel conversion on data characters transmitted by the processor. The complete
status of each channel of the TL16C754B UART can be read at any time during functional operation by the
processor.

The TL16C754B UART can be placed in an alternate mode (FIFO mode) relieving the processor of excessive
software overhead by buffering received/transmitted characters. Both the receiver and transmitter FIFOs can
store up to 64 bytes (including three additional bits of error status per byte for the receiver FIFO) and have
selectable or programmable trigger levels. Primary outputs RXRDY

and TXRDY allow signalling of DMA

transfers.
The TL16C754B UART has selectable hardware flow control and software flow control. Both schemes

significantly reduce software overhead and increase system efficiency by automatically controlling serial data
flow. Hardware flow control uses the RTS output and CTS input signals. Software flow control uses
programmable Xon/Xoff characters.

The UART will include a programmable baud rate generator that can divide the timing reference clock input by
a divisor between 1 and (216–1). The CLKSEL pin can be used to divide the input clock by 4 or by 1 to generate
the reference clock during the reset. The divide-by-4 clock is selected when CLKSEL pin is a logic 0 or the
divide-by-1 is selected when CLKSEL is a logic 1.

TL16C754B
QUAD UART WITH 64-BYTE FIFO

SLLS397 – NOVEMBER 1999

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional description (continued)

trigger levels

The TL16C754B UART provides independent selectable and programmable trigger levels for both receiver and
transmitter DMA and interrupt generation. After reset, both transmitter and receiver FIFOs are disabled and so,
in effect, the trigger level is the default value of one byte. The selectable trigger levels are available via the FCR.
The programmable trigger levels are available via the TLR.

hardware flow control

Hardware flow control is composed of auto-CTS and auto-RTS. Auto-CTS and auto-RTS can be
enabled/disabled independently by programming EFR[7:6].

With auto-CTS, CTS must be active before the UART can transmit data.
Auto-RTS

only activates the RTS output when there is enough room in the FIFO to receive data and deactivates

the RTS

output when the RX FIFO is sufficiently full. The HALT and RESTORE trigger levels in the TCR

determine the levels at which RTS is activated/deactivated.
If both auto-CTS

and auto-RTS are enabled, when RTS is connected to CTS, data transmission does not occur
unless the receiver FIFO has empty space. Thus, overrun errors are eliminated during hardware flow control.
If not enabled, overrun errors occur if the transmit data rate exceeds the receive FIFO servicing latency.

auto-RTS

Auto-RTS data flow control originates in the receiver block (see functional block diagram). Figure 1 shows RTS
functional timing. The receiver FIFO trigger levels used in Auto-RTS are stored in the TCR. RTS is active if the
RX FIFO level is below the HAL T trigger level in TCR[3:0]. When the receiver FIFO HALT trigger level is reached,
RTS

is deasserted. The sending device (e.g., another UART) may send an additional byte after the trigger level
is reached (assuming the sending UART has another byte to send) because it may not recognize the
deassertion of RTS until it has begun sending the additional byte. RTS is automatically reasserted once the
receiver FIFO reaches the RESUME trigger level programmed via TCR[7:4]. This reassertion allows the
sending device to resume transmission.

RX

RTS

IOR

Start Byte N Stop Start Byte N+1 Stop Start

1 2 N N+1

NOTES: A. N = receiver FIFO trigger level

B. The two blocks in dashed lines cover the case where an additional byte is sent as described in Auto-RTS

.

Figure 1. RTS Functional Timing

TL16C754B

QUAD UART WITH 64-BYTE FIFO

SLLS397 – NOVEMBER 1999

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional description (continued)

auto-CTS

The transmitter circuitry checks CTS before sending the next data byte. When CTS is active, the transmitter
sends the next byte. To stop the transmitter from sending the following byte, CTS must be deasserted before
the middle of the last stop bit that is currently being sent. The auto-CTS function reduces interrupts to the host
system. When flow control is enabled, the CTS

state changes and need not trigger host interrupts because the
device automatically controls its own transmitter. Without auto-CTS, the transmitter sends any data present in
the transmit FIFO and a receiver overrun error can result. Figure 2 shows CTS functional timing, and Figure 3
shows an example of autoflow control.

Byte 0–7 StopStart Byte 0–7 StopStart

TX

CTS

NOTES: A. When CTS is low, the transmitter keeps sending serial data out.

B. When CTS

goes high before the middle of the last stop bit of the current byte, the transmitter finishes sending the current byte, but

it does not send the next byte.

C. When CTS

goes from high to low, the transmitter begins sending data again.

Figure 2. CTS Functional Timing

Serial to

Parallel

Flow

Control

Parallel to

Serial

Flow

Control

RX

FIFO

TX

FIFO

Parallel to

Serial

Flow

Control

Serial to

Parallel

Flow

Control

TX

FIFO

RX

FIFO

D7–D0 D7–D0

UART 1 UART 2

RX

RTS

TX

CTS

TX

CTS

RX

RTS

Figure 3. Autoflow Control (Auto-RTS and Auto-CTS) Example

software flow control

Software flow control is enabled through the enhanced feature register and the modem control register. Different
combinations of software flow control can be enabled by setting different combinations of EFR[3–0]. Table 1
shows software flow control options.

Two other enhanced features relate to S/W flow control:

– Xon Any Function [MCR(5): Operation will resume after receiving any character after recognizing the

Xoff character.

TL16C754B
QUAD UART WITH 64-BYTE FIFO

SLLS397 – NOVEMBER 1999

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional description (continued)

NOTE:

It is possible that an Xon1 character is recognized as an Xon Any character, which could
cause an Xon2 character to be written to the RX FIFO.

– Special Character [EFR(5)]: Incoming data is compared to Xoff2. Detection of the special character

sets the Xoff interrupt {IIR(4)] but does not halt transmission. The Xoff interrupt is cleared by a read of the
IIR. The special character is transferred to the RX FIFO.

Table 1. Software Flow Control Options EFR[3:0]

BIT 3 BIT 2 BIT 1 BIT 0 Tx, Rx SOFTWARE FLOW CONTROLS

0 0 X X No transmit flow control
1 0 X X Transmit Xon1, Xoff1
0 1 X X Transmit Xon2, Xoff2

1 1 X X Transmit Xon1, Xon2: Xoff1, Xoff2
X X 0 0 No receive flow control
X X 1 0 Receiver compares Xon1, Xoff1
X X 0 1 Receiver compares Xon2, Xoff2
1 0 1 1 Transmit Xon1, Xoff1

Receiver compares Xon1 or Xon2, Xoff1 or Xoff2

0 1 1 1 Transmit Xon2, Xoff2

Receiver compares Xon1 or Xon2, Xoff1 or Xoff2

1 1 1 1 Transmit Xon1, Xon2: Xoff1, Xoff2

Receiver compares Xon1 and Xon2: Xoff1 and Xoff2

0 0 1 1 No transmit flow control

Receiver compares Xon1 and Xon2: Xoff1 and Xoff2

When software flow control operation is enabled, the TL16C754B will compare incoming data with Xoff1/2
programmed characters (in certain cases Xoff1 and Xoff2 must be received sequentially1). When an Xoff
character is received, transmission is halted after completing transmission of the current character. Xoff
character detection also sets IIR[4] and causes INT to go high (if enabled via IER[5]).

To resume transmission an Xon1/2 character must be received (in certain cases Xon1 and Xon2 must be
received sequentially). When the correct Xon characters are received IIR[4] is cleared and the Xoff interrupt
disappears.

NOTE:

If a parity, framing or break error occurs while receiving a software flow control character, this
character will be treated as normal data and will be written to the RCV FIFO.

Xoff1/2 characters are transmitted when the RX FIFO has passed the programmed trigger level TCR[3:0].
Xon1/2 characters are transmitted when the RX FIFO reaches the trigger level programmed via TCR[7:4].
An important note here is that if, after an Xoff character has been sent, software flow control is disabled, the

UART will transmit Xon characters automatically to enable normal transmission to proceed. A feature of the
TL16C754B UART design is that if the software flow combination (EFR[3:0]) changes after an Xoff has been
sent, the originally programmed Xon is automatically sent. If the RX FIFO is still above the trigger level the newly
programmed Xoff1/2 will be transmitted.

1. When pairs of Xon/Xoff characters are programmed to occur sequentially, received Xon1/Xoff1 characters will be written to the Rx FIFO if
the subsequent character is not Xon2/Xoff2.

TL16C754B

QUAD UART WITH 64-BYTE FIFO

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functional description (continued)

The transmission of Xoff/Xon(s) follows the exact same protocol as transmission of an ordinary byte from the
FIFO. This means that even if the word length is set to be 5, 6, or 7 characters then the 5, 6, or 7 least significant
bits of Xoff1,2/Xon1,2 will be transmitted. The transmission of 5, 6, or 7 bits of a character is seldom done, but
this functionality is included to maintain compatibility with earlier designs.

It is assumed that software flow control and hardware flow control will never be enabled simultaneously . Figure 4
shows a software flow control example.

UART 1

Parallel to Serial

Serial to Parallel

Xon-1 Word

Xon-2 Word

Xoff-1 Word

Xoff-1 Word

Transmit

FIFO

Serial to Parallel

Parallel to Serial

Xon-1 Word

Xon-2 Word

Xoff-1 Word

Xoff-2 Word

Receive

FIFO

Data

Xoff – Xon – Xoff

Compare

Programmed

Xon–Xoff

Characters

UART 2

Figure 4. Software Flow Control Example

software flow control example

Assumptions: UART1 is transmitting a large text file to UART2. Both UARTs are using software flow control with
single character Xoff (0F) and Xon (0D) tokens. Both have Xoff threshold (TCR [3:0]=F) set to 60 and Xon
threshold (TCR[7:4]=8) set to 32. Both have the interrupt receive threshold (TLR[7:4]=D) set to 52.

UART1 begins transmission and sends 52 characters, at which point UART2 will generate an interrupt to its
processor to service the RCV FIFO, but assume the interrupt latency is fairly long. UART1 will continue sending
characters until a total of 60 characters have been sent. At this time UART2 will transmit a 0F to UART1,
informing UART1 to halt transmission. UART1 will likely send the 61

st

character while UART2 is sending the
Xoff character . Now UART2 is serviced and the processor reads enough data out of the RCV FIFO that the level
drops to 32. UART2 will now send a 0D to UART1, informing UART1 to resume transmission.

TL16C754B
QUAD UART WITH 64-BYTE FIFO

SLLS397 – NOVEMBER 1999

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional description (continued)

reset

Table 2 summarizes the state of registers after reset.

Table 2. Register Reset Functions

REGISTER

RESET

CONTROL

RESET STATE

Interrupt enable register RESET All bits cleared
Interrupt identification register RESET Bit 0 is set. All other bits cleared.
FIFO control register RESET All bits cleared
Line control register RESET Reset to 00011101 (1D hex).

Modem control register RESET

Bit 6–0 cleared. Bit 7 reflects the inverse of

the CLKSEL pin value.
Line status register RESET Bits 5 and 6 set. All other bits cleared.
Modem status register RESET Bits 0–3 cleared. Bits 4–7 input signals.

Enhanced feature register RESET

Bit 6 – 0 is cleared. Bit 7 reflects the inverse

of the CLKSEL pin value.
Receiver holding register RESET Pointer logic cleared
Transmitter holding register RESET Pointer logic cleared
Transmission control register RESET All bits cleared
Trigger level register RESET All bits cleared

NOTE: Registers DLL, DLH, SPR, Xon1, Xon2, Xoff1, Xoff2 are not reset by the top-level reset signal

RESET, i.e., they hold their initialization values during reset.

Table 3 summarizes the state of some signals after reset.

Table 3. Signal Reset Functions

SIGNAL

RESET

CONTROL

RESET STATE

TX RESET High
RTS RESET High
DTR RESET High
RXRDY RESET High
TXRDY RESET Low

interrupts

The TL16C754B UART has interrupt generation and prioritization (6 prioritized levels of interrupts) capability.
The interrupt enable register (IER) enables each of the 6 types of interrupts and the INT signal in response to
an interrupt generation. The IER can also disable the interrupt system by clearing bits 0–3, 5–7. When an
interrupt is generated, the interrupt identification register(IIR) indicates that an interrupt is pending and provides
the type of interrupt through IIR[5–0]. Table 4 summarizes the interrupt control functions.

TL16C754B

QUAD UART WITH 64-BYTE FIFO

SLLS397 – NOVEMBER 1999

11

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional description (continued)

Table 4. Interrupt Control Functions

IIR[5–0]

PRIORITY

LEVEL

INTERRUPT

TYPE

INTERRUPT SOURCE INTERRUPT RESET METHOD

000001 None None None None
000110 1 Receiver line

status

OE, FE, PE, or BI errors occur in characters in the
RX FIFO

FE< PE< BI: All erroneous characters are

read from the RX FIFO. OE: Read LSR
001100 2 RX timeout Stale data in RX FIFO Read RHR
000100 2 RHR interrupt DRDY (data ready)

(FIFO disable)
RX FIFO above trigger level (FIFO enable)

Read RHR

000010 3 THR interrupt TFE (THR empty)

(FIFO disable)
TX FIFO passes above trigger level (FIFO enable)

Read IIR OR a write to the THR

000000 4 Modem status MSR[3:0]= 0 Read MSR
010000 5 Xoff interrupt Receive Xoff character(s)/special character Receive Xon character(s)/Read of IIR
100000 6 CTS, RTS RTS pin or CTS pin change state from active (low)

to inactive (high)

Read IIR

It is important to note that for the framing error, parity error , and break conditions, LSR[7] generates the interrupt.
LSR[7] is set when there is an error anywhere in the RX FIFO and is cleared only when there are no more errors
remaining in the FIFO. LSR[4–2] always represent the error status for the received character at the top of the
Rx FIFO. Reading the Rx FIFO updates LSR[4–2] to the appropriate status for the new character at the top of
the FIFO. If the Rx FIFO is empty, then LSR[4–2] is all zeros.

For the Xoff interrupt, if an Xoff flow character detection caused the interrupt, the interrupt is cleared by an Xon
flow character detection. If a special character detection caused the interrupt, the interrupt is cleared by a read
of the ISR.

interrupt mode operation

In interrupt mode (if any bit of IER[3:0] is1), the processor is informed of the status of the receiver and transmitter
by an interrupt signal, INT. Therefore, it is not necessary to continuously poll the line status register (LSR) to
see if any interrupt needs to be serviced. Figure 5 shows interrupt mode operation.

1111

IER

IIR

THR RHR

IOW/IOR

INTProcessor

Figure 5. Interrupt Mode Operation

polled mode operation

In polled mode (IER[3:0] = 0000), the status of the receiver and transmitter can then be checked by polling the
line status register (LSR). This mode is an alternative to the interrupt mode of operation where the status of the
receiver and transmitter is automatically known by means of interrupts sent to the CPU. Figure 6 shows polled
mode operation.

TL16C754B
QUAD UART WITH 64-BYTE FIFO

SLLS397 – NOVEMBER 1999

12

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional description (continued)

0000

LSR

IER

THR RHR

IOW/IOR

Processor

Figure 6. FIFO Polled Mode Operation

DMA signalling

There are two modes of DMA operation, DMA mode 0 or 1, selected by FCR[3].
In DMA mode 0 or FIFO disable (FCR[0]=0) DMA occurs in single character transfers. In DMA mode 1

multicharacter (or block) DMA transfers are managed to relieve the processor for longer periods of time.

single DMA transfers (DMA mode0/FIFO disable)

Transmitter: When empty, the TXRDY signal becomes active. TXRDY will go inactive after one character has
been loaded into it.

Receiver: RXRDY is active when there is at least one character in the FIFO. It becomes inactive when the
receiver is empty.

Figure 7 shows TXRDY and RXRDY in DMA mode 0/FIFO disable.

FIFO Empty

TXRDY

wrptr

TXRDY

wrptr

At Least One
Location Filled

TX

FIFO Empty

RXRDY

rdptr

RXRDY

rdptr

At Least One
Location Filled

RX

Figure 7. TXRDY and RXRDY in DMA Mode 0/FIFO Disable

block DMA transfers (DMA mode 1)

Transmitter: TXRDY is active when a trigger level number of spaces are available. It becomes inactive when
the FIFO is full.