Texas Instruments TL16C752PT Datasheet

TL16C752

3.3-V DUAL UART WITH 64-BYTE FIFO

SLLS305 – MA Y 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Pin Compatible With ST16C2550 With Additional Enhancements

Supports Up to 3.125 Mbps Baud Rate – Up to 2.1875 Mbps Baud Rate When

Using Crystal (35 MHz Input Clock)

– Up to 3.125 Mbps Baud Rate When Using

Oscillator or Clock Source (50 MHz Input Clock)

64-Byte Transmit FIFO

64-Byte Receive FIFO With Error Flags

Programmable and Selectable Transmit and Receive FIFO Trigger Levels for DMA and Interrupt Generation

Programmable Receive FIFO Trigger Levels for Software/Hardware Flow Control

Software/Hardware Flow Control – Programmable Xon/Xoff Characters – Programmable Auto-RTS

and Auto-CTS

Software Flow Control Turned Off Optionally by Any Xon Rx Character

DMA Signalling Capability for Both Received and Transmitted Data

Supports 3.3-V Operation

Software Selectable Baud Rate Generator Prescaleable Clock Rates of 1X and 4X

Fast Access Time 2 Clock Cycle IOR/IOW Pulse Width

Programmable Sleep Mode

Programmable Serial Interface Characteristics – 5, 6, 7, or 8Bit Characters – Even, Odd, or No Parity Bit Generation

and Detection

– 1, 1.5, or 2 Stop Bit Generation

False Start Bit Detection

Complete Status Reporting Capabilities in Both Normal and Sleep Mode

Line Break Generation and Detection

Internal Test and Loopback Capabilities

Fully Prioritized Interrupt System Controls

Modem Control Functions (CTS, RTS, DSR, DTR

, RI, and CD)

14 15

RESET DTRB DTRA RTSA OPA RXRDYA INTA INTB A0 A1 A2 NC

36 35 34 33 32 31 30 29 28 27 26 25

1 2 3 4 5 6 7 8 9 10 11 12

D5 D6

D7 RXB RXA

TXRDYB

TXA

TXB OPB CSA CSB

17 18 19 20

RIA

CDA

DSRA

CTSA

47 46 45 44 4348 42

D4D3D2D1D0

RTSB

CTSB

IOW

GND

RXRDYB

IOR

DSRB

RIB

40 39 3841

22 23 24

TXRDYA

XTAL2

XTAL1

CDB

PACKAGE

(TOP VIEW)

NC – No internal connection

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

TL16C752

3.3-V DUAL UART WITH 64-BYTE FIFO

SLLS305 – MA Y 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description

The TL16C752 is a dual universal asynchronous receiver/transmitter (UART) with 64-byte FIFOs, automatic hardware/software flow control, and data rates up to 3.125 Mbps. The ’752 offers enhanced features. It has a transmission control register (TCR) that stores received FIFO threshold level to start/stop transmission during hardware and sofware flow control. With the FIFO RDY register, the software gets the status of TXRDY/RXRDY for all four ports in one access. Onboard status registers provide the user with error indications and operational status, modem interface control. System interrupts may be tailored to meet user requirements. An internal loopback capability allows onboard diagnostics.

The UART transmits data sent to it from the peripheral 8-bit bus on the TX signal and receives characters on the RX signal. Characters can be programmed to be 5, 6, 7, or 8 bits. The UART has a 64-byte receive FIFO and transmit FIFO and can be programmed to interrupt at different trigger levels. The UART generates its own desired baud rate based upon a programmable divisor and its input clock. It can transmit even, odd, or no parity and 1, 1.5, or 2 stop bits. The receiver can detect break, idle, or framing errors, FIFO overflow, and parity errors. The transmitter can detect FIFO underflow. The UART also contains a software interface for modem control operations, and has software flow control and hardware flow control capabilities.

The TL16C752 is available in a 48-pin PT (LQFP) package. The 48-pin version offers three state interrupt control and provides constant active interrupt outputs.

Terminal Functions

TERMINAL

NAME NO.

I/O

DESCRIPTION

A0 28 I Address 0 select bit. Internal registers address selection. A1 27 I Address 1 select bit. Internal registers address selection. A2 26 I Address 2 select bit. Internal registers address selection.

CDA, CDB 40, 16 I

Carrier detect (active low). These inputs are associated with individual UART channels A through D. A 0 on these pins indicates that a carrier has been detected by the modem for that channel.

CSA, CSB 10, 11 I

Chip select A and B (active low). These pins enable data transfers between the user CPU and the TL16C752 for the channel(s) addressed. Individual UART sections (A, B) are addressed by providing a 0 on the respective CS A

and CS B pins.

CTSA, CTSB 38, 23 I

Clear to send (active low). These inputs are associated with individual UART channels A and B. A logic 0 on the CTS pins indicates the modem or data set is ready to accept transmit data from the 752. Status can be tested by reading MSR bit 4. These pins only affect the transmit and receive operations when auto CTS function is enabled through the enhanced feature register (EFR) bit 7, for hardware flow control operation.

D0–D4 D5–D7

44–48,

1–3

I/O

Data bus (bidirectional). These pins are the eight bit, three state-data bus for transferring information to or from the controlling CPU. D0 is the least significant bit and the first data bit in a transmit or receive serial data stream.

DSRA, DSRB 39, 20 I

Data set ready (active low). These inputs are associated with individual UART channels A and B. A logic 0 on these pins indicates the modem or data set is powered on and is ready for data exchange with the UART . These pins have no effect on the UART transmit or receive operation.

DTRA, DTRB 34, 35 O

Data terminal ready (active low). These outputs are associated with individual UART channels A and B. A logic 0 on these pins indicates that the 752 is powered on and ready. These pins can be controlled through the modem control register . W riting a 1 to MCR bit 0 sets the DTR

output to 0, enabling the modem. These pins are a logic 1 after writing a 0 to MCR bit 0, or after a reset. These pins have no effect on the UART transmit or receive operation.

GND 17 Pwr Signal and power ground

INTA, INTB 30, 29 O

Interrupt A and B (active high). These pins provide individual channel interrupts, INT A and B. INT A and B are enabled when MCR bit 3 is set to a logic 1, interrupts are enabled in the interrupt enable register (IER), and when an interrupt condition exists. Interrupt conditions include: receiver errors, available receiver buffer data, transmit buffer empty, or when a modem status flag is detected.

IOR 19 I

Read input (active low strobe). A high to low transition on IOR will load the contents of an internal register defined by address bits A0–A2 onto the TL16C752 data bus (D0–D7) for access by an external CPU.

TL16C752

3.3-V DUAL UART WITH 64-BYTE FIFO

SLLS305 – MA Y 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions (Continued)

TERMINAL

NAME NO.

I/O

DESCRIPTION

IOW 15 I

Write input (active low strobe). A high to low transition on IOW will transfer the contents of the data bus (D0–D7) from the external CPU to an internal register that is defined by address bits A0–A2 and CSA

and CSB

OPA, OPB 32, 9 0

User defined outputs. This function is associated with individual channels A and B. The state at these pins is defined by the user and through the software settings of the MCR register, bit 3. INT A–B are set to active mode and OP to a logic 0 when the MCR–3 is set to a logic 1. INTA–B are set to the thru state mode and OP is set to a logic 0. See bit 3, Modem Control Register (MCR bit 3).

RESET 36 I

Reset. RESET will reset the internal registers and all the outputs. The UART transmitter output and the receiver input will be disabled during reset time. See TL16C752 external reset conditions for initialization details.

RIA, RIB 41, 21 I

Ring indicator (active low). These inputs are associated with individual UART channels A and B. A logic 0 on these pins indicates the modem has received a ringing signal from the telephone line. A logic 1 transition on these input pins generates an interrupt.

RTSA, RTSB 33, 22 O

Request to send (active low). These outputs are associated with individual UART channels A and B. A logic 0 on the RTS

pins indicates the transmitter has data ready and waiting to send. Writing a 1 in the modem control register (MCR bit 1) sets these pins to 0, indicating data is available. After a reset, these pins are set to 1. These pins only affects the transmit and receive operation when auto RTS function is enabled through the enhanced feature register (EFR) bit 6, for hardware flow control operation.

RXA, RXB 5, 4 I

Receive data input. These inputs are associated with individual serial channel data to the 752. During the local loopback mode, these RX input pins are disabled and TX data is internally connected to the UART RX input internally .

RXRDYA, RXRDYB

31, 18 O

Receive ready (active low). RXRDY A and B goes low when the trigger level has been reached or a timeout interrupt occurs. They goes high when the RX FIFO is empty and there is an error in RX FIFO.

TXA, TXB 7, 8 O

Transmit data. These outputs are associated with individual serial transmit channel data from the 752. During the local loopback mode, the TX input pin is disabled and TX data is internally connected to the UART RX input.

TXRDYA, TXRDYB

43, 6 O

Transmit ready (active low). TXRDY A and B go low when there trigger level numbers of spares available. They go high when the TX buffer is full.

42 I Power supply inputs.

XTAL1 13 I

Crystal or external clock input. XTAL1 functions as a crystal input or as an external clock input. A crystal can be connected between XTAL1 and XTAL2 to form an internal oscillator circuit (see Figures 9 and 10). Alternatively , an external clock can be connected to XTAL1 to provide custom data rates.

XTAL2 14 O

Output of the crystal oscillator or buffered clock. See also XT AL1. XT AL2 is used as a crystal oscillator output or buffered a clock output.

TL16C752

3.3-V DUAL UART WITH 64-BYTE FIFO

SLLS305 – MA Y 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional block diagram

Control Signals

Modem Control Signals

Divisor

Bus

Interface

Control

and

Status Block

Status Signals

Control Signals

Status Signals

Baud-Rate

Generator

UART_CLK

Receiver Block

Logic

Receiver FIFO

64-Byte

Vote

Logic

Transmitter Block

Logic

Transmitter FIFO

64-Byte

NOTE: The Vote logic determines whether the RX data is a logic 1 or 0. It takes three samples of the RX line, and uses a majority vote to determine

the logic level received. The Vote logic operates on all bits received.

functional description

The TL16C752 UART is pin compatible with the ST16C2550 UART. It provides more enhanced features. All additional features are provided through a special enhanced feature register.

The UART will perform serial-to-parallel conversion on data characters received from peripheral devices or modems and parallel-to-parallel conversion on data characters transmitted by the processor. The complete status of each channel of the TL16C752 UART can be read at any time during functional operation by the processor.

The TL16C752 can be placed in an alternate mode (FIFO mode) relieving the processor of excessive software overhead by buffering received/transmitted characters. Both the receiver and transmitter FIFOs can store up to 64 bytes (including three additional bits of error status per byte for the receiver FIFO) and have selectable or programmable trigger levels. Primary outputs RXRDY

and TXRDY allow signalling of DMA transfers.

The TL16C752 will have selectable hardware flow control and software flow control. Hardware flow control significantly reduces software overhead and increases system efficiency by automatically controlling serial data flow using the RTS

output and CTS input signals. Software flow control automatically controls data flow by using

programmable Xon/Xoff characters. The UART will include a programmable baud rate generator that can divide the timing reference clock input by

a divisor between 1 and (2

–1).

TL16C752

3.3-V DUAL UART WITH 64-BYTE FIFO

SLLS305 – MA Y 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional description (continued)

trigger levels

The TL16C752 provides independent selectable and programmable trigger levels for both receiver and transmitter DMA and interrupt generation. After reset, both transmitter and receiver FIFOs are disabled and so, in effect, the trigger level is the default value of one byte. The selectable trigger levels are available via the FCR. The programmable trigger levels are available via the TLR.

hardware flow control

Hardware flow control is composed on auto-CTS

and auto-RTS. Auto-CTS and auto-RTS can be enabled/

disabled independently by programming EFR[7:6]. With auto-CTS

, CTS must be active before the UART can transmit data.

Auto-RTS

only activates the RTS output when there is enough room in the FIFO to receive data and deactivates the RTS output when the RX FIFO is sufficiently full. The HALT and RESTORE trigger levels in the TCR determine the levels at which RTS is activated/deactivated.

If both auto-CTS

and auto-RTS are enabled, when RTS is connected to CTS, data transmission does not occur unless the receiver FIFO has empty space. Thus, overrun errors are eliminated during hardware flow control. If not enabled, overrun errors occur if the transmit data rate exceeds the receive FIFO latency.

auto-RTS

Auto-RTS data flow control originates in the receiver block (see functional block diagram). Figure 1 shows RTS functional timing. The receiver FIFO trigger levels used in Auto-RTS are stored in the TCR. RTS is active if the RX FIFO level is below the HAL T trigger level in TCR[3:0]. When the receiver FIFO HALT trigger level is reached, RTS

is deasserted. The sending device (e.g., another UART) may send an additional byte after the trigger level is reached (assuming the sending UART has another byte to send) because it may not recognize the deassertion of RTS

until it has begun sending the additional byte. RTS is automatically reasserted once the receiver FIFO reaches the RESUME trigger level programmed via TCR[7:4]. This reassertion allows the sending device to resume transmission.

RTS

IOR

Start Byte N Stop Start Byte N+1 Stop Start

1 2 N N+1

NOTES: 1. N = receiver FIFO trigger level

2. The two blocks in dashed lines cover the case where an additional byte is sent as described in Auto-RTS

Figure 1. RTS Functional Timing

TL16C752

3.3-V DUAL UART WITH 64-BYTE FIFO

SLLS305 – MA Y 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional description (continued)

auto-CTS

The transmitter circuitry checks CTS before sending the next data byte. When CTS is active, the transmitter sends the next byte. To stop the transmitter from sending the following byte. CTS

must be deasserted before

the middle of the last stop bit that is currently being sent. The auto-CTS

function reduces interrupts to the host

system. When flow control is enabled, the CTS

state changes and need not trigger host interrupts because the

device automatically controls its own transmitter. Without auto-CTS

, the transmitter sends any data present in

the transmit FIFO and a receiver overrun error can result. Figure 2 shows CTS

functional timing, and Figure 3

shows an example of autoflow control.

Byte 0–7 StopStart Byte 0–7 StopStart

CTS

NOTES: A. When CTS is low, the transmitter keeps sending serial data out

B. When CTS

goes high before the middle of the last stop bit of the current byte, the transmitter finishes sending the current byte but

it does not send the next byte.

C. When CTS

goes from high to low, the transmitter begins sending data again.

Figure 2. CTS Functional Timing

Serial to

Parallel

Flow

Control

Parallel to

Serial

Flow

Control

FIFO

Parallel to

Serial

Flow

Control

Serial to

Parallel

Flow

Control

FIFO

D7–D0 D7–D0

UART 1 UART 2

RTS

CTS

RTS

Figure 3. Autoflow Control (Auto-RTS and Auto-CTS) Example

TL16C752

3.3-V DUAL UART WITH 64-BYTE FIFO

SLLS305 – MA Y 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional description (continued)

software flow control

Software flow control is enabled through the enhanced feature register and the modem control register. Different combinations of software flow control can be enabled by setting different combinations of EFR[3–0]. Table 1 shows software flow control options.

There are two other enhanced features relating to S/W flow control:

– Xon Any Function [MCR950: Operation will resume after receiving any character after recognizing the

Xoff character.

NOTE:

It is possible that an Xon1 character is recognized as an Xon Any character which could cause an Xon2 character to be written to the RX FIFO.

– Special Character [EFR(5)]: Incoming data is compared to Xoff2. Detection of the special character

sets the Xoff interrupt {IIR(4)] but does not halt transmission. The Xoff interrupt is cleared by a read of the IIR. The special character is transferred to the R FIFO.

Table 1. Software Flow Control Options EFR[0:3]

BIT 3 BIT 2 BIT 1 BIT 0 Tx, Rx SOFTWARE FLOW CONTROLS

0 0 X X No transmit flow control 1 0 X X Transmit Xon1, Xoff1 0 1 X X Transmit Xon2, Xoff2 1 1 X X Transmit Xon1, Xon2: Xoff1, Xoff2 X X 0 0 No receive flow control X X 1 0 Receiver compares Xon1, Xoff1 X X 0 1 Receiver compares Xon2, Xoff2 1 0 1 1 Transmit Xon1, Xoff1

Receiver compares Xon1 and Xon2, Xoff1 and Xoff2

0 1 1 1 Transmit Xon2, Xoff2

Receiver compares Xon1 and Xon2, Xoff1 and Xoff2

1 1 1 1 Transmit Xon1, Xon2: Xoff1, Xoff2Xoff1

Receiver compares Xon1 and Xon2: Xoff1 and Xoff2

0 0 1 1 No transmit flow control

Receiver compares Xon1 and Xon2: Xoff1 and Xoff2

When software flow control operation is enabled, the TL16C752 will compare incoming data with Xoff1/2 programmed characters (in certain cases Xoff1 and Xoff2 must be received sequentially

). When the correct Xoff characters are received, transmission is halted after completing transmission of the current character . Xoff detection also sets IIR[4] (if enabled via IER[5]) and causes INT to go high.

To resume transmission an Xon1/2 character must be received (in certain cases Xon1 and Xon2 must be received sequentially). When the correct Xon characters are received IIR[4] is cleared and the Xoff interrupt disappears.

NOTE:

If a Parity, Framing or Break error occurs while receiving a software flow control character, this character will be treated as normal data and will be written to the RCV FIFO.

1. When pairs of Xon/Xoff characters are programmed to occur sequentially, received Xon1/Xoff1 characters must be written to the Rx FIFO if the subsequent character is not Xon2/Xoff2.

TL16C752

3.3-V DUAL UART WITH 64-BYTE FIFO

SLLS305 – MA Y 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional description (continued)

Xoff1/2 characters are transmitted when the RX FIFO has passed the programmed trigger level TCR[3:0]. Xon1/2 characters are transmitted when the RX FIFO reaches the trigger level programmed via TCR[7:4]. An important note here is that if, after an xoff character has been sent, software flow control is disabled the UART

will transmit Xon characters automatically to enable normal transmission to proceed. A feature of the TL16C752 UART design is that if the software flow combination (EFR[3:0]) changes after an Xoff has been sent, the originally programmed Xon is automatically sent. If the RX FIFO is still above the trigger level, the newly programmed Xoff1/2 will be transmitted.

The transmission of Xoff/Xon(s) follows the exact same protocol as transmission of an ordinary byte from the FIFO. This means that even if the word length is set to be 5, 6, or 7 characters then the 5, 6, or 7 least significant bits of Xoff1,2/Xon1,2 will be transmitted. (Note that the transmission of 5, 6, or 7 bits of a character is seldom done, but this functionality is included to maintain compatibility with earlier designs.)

It is assumed that software flow control and hardware flow control will never be enabled simultaneously . Figure 4 shows an example of software flow control.

UART 1

Parallel to Serial

Serial to Parallel

Xon-1 Word

Xon-2 Word

Xoff-1 Word

Transmit

FIFO

Serial to Parallel

Parallel to Serial

Xon-1 Word

Xoff-1 Word

Xoff-2 Word

Receive

FIFO

Data

Xoff – Xon – Xoff

Compare

Programmed

Xon–Xoff

Characters

UART 2

Xon-2 Word

Figure 4. Software Flow Control Example

TL16C752

3.3-V DUAL UART WITH 64-BYTE FIFO

SLLS305 – MA Y 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional description (continued)

reset

Table 2 summarizes the state of registers after reset.

Table 2. Register Reset Functions

RESET

CONTROL

RESET STATE

Interrupt enable register RESET All bits cleared Interrupt identification register RESET Bit 0 is set. All other bits cleared. FIFO control register RESET All bits cleared Line control register RESET Reset to 00011101 (1D hex). Modem control register RESET All bits cleared Line status register RESET Bits 5 and 6 set. All other bits cleared. Modem status register RESET Bits 0–3 cleared. Bits 4–7 input signals. Enhanced feature register RESET All bits cleared Receiver holding register RESET Pointer logic cleared Transmitter holding register RESET Pointer logic cleared Transmission control register RESET All bits cleared Trigger level register RESET All bits cleared

NOTE: Registers DLL, DLH, SPR, Xon1, Xon2, Xoff1, Xoff2 are not reset by the top-level reset signal

RESEST, i.e., they hold their initialization values during reset.

Table 3 summarizes the state of registers after reset.

Table 3. Signal Reset Functions

SIGNAL

RESET

CONTROL

RESET STATE

TX RESET High RTS RESET High DTR RESET High RXRDY RESET High TXRDY RESET Low

interrupts

The TL16C752 has interrupt generation and prioritization (6 prioritized levels of interrupts) capability. The Interrupt enable register (IER) enables each of the 6 types of interrupts and the INT signal in response to an interrupt generation. The IER can also disable the interrupt system by clearing bits 0–3, 5–7. When an interrupt is generated, the IIR indicates that an interrupt is pending and provides the type of interrupt through IIR[5–0]. Table 4 summarizes the interrupt control functions.

TL16C752

3.3-V DUAL UART WITH 64-BYTE FIFO

SLLS305 – MA Y 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional description (continued)

Table 4. Interrupt Control Functions

IIR[5–0]

PRIORITY

LEVEL

INTERRUPT

TYPE

INTERRUPT SOURCE INTERRUPT RESET METHOD

000001 None None None None 000110 1 Receiver line

status

OE, FE, PE, or BI errors occur in characters in the RX FIFO

FE< PE< BI: All erroneous characters are read from the RX FIFO.

OE: Read LSR 001100 2 RX timeout Stale data in RX FIFO Read RHR 000100 2 RHR interrupt DRDY (data ready)

(FIFO disable) RX FIFO above trigger level (FIFO enable)

Read RHR

000010 3 THR interrupt TFE (THR empty)

(FIFO disable) TX FIFO passes below trigger level (FIFO enable)

Read IIR OR a write to the THR

000000 4 Modem status MSR[3:0]/= 0 Read MSR 010000 5 Xoff interrupt Receive Xoff character(s)/special character Receive Xon character(s)/Read of IIR 100000 6 CTS, RTS RTS pin or CTS pin change state from active

(low) to inactive (high)

Read IIR

It is important to note that for the receiver line status interrupt, it is LSR[7] which generates the interrupt. LSR[4–2] are set when an erroneous character is read from the RX FIFO and they are cleared on a read of the LSR. LSR[7] is set when there is an error anywhere in the RX FIFO and is cleared only when there are no more errors remaining in the FIFO.

For the Xoff interrupt, if an Xoff flow character detection caused the interrupt, the interrupt is cleared by an Xon flow character detection. If a special character detection caused the interrupt, the interrupt is cleared by a read of the ISR.

interrupt mode operation

In FIFO interrupt mode (FCR=1, IER[3:0] = 1) the processor is informed of the status of the receiver and transmitter by an interrupt signal, INT. Therefore, it is not necessary to continuously poll the line stats register (LSR) to see if any interrupts need to be serviced. Figure 5 shows FIFO interrupt mode operation.

1111

IER

IIR

THR RHR

IOW/IOR

INTProcessor

Figure 5. FIFO Interrupt Mode Operation

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