THS4271EVM−UG
Unity Gain
User’s G uide
DEVICE
THS4271
THS4271
THS4275
EVM TITLE USER’S GUIDE DESCRIPTION SHUTDOWN
THS4271EVM-UG
THS4271EVM
THS4275EVM
THS4271 Unity Gain EVM
THS4271/75EVM
THS4271/75EVM
Noninverting unity gain configuration only
Configurable for gains ≥ +2/-1
Configurable for gains ≥ +2/-1
No
No
Yes
October 2002 High Performance Linear Products
SLOU147
IMPORTANT NOTICE
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enhancements, improvements, and other changes to its products and services at any time and to discontinue
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
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parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
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Mailing Address:
Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright 2002, Texas Instruments Incorporated
EVM IMPORTANT NOTICE
Texas Instruments (TI) provides the enclosed product(s) under the following conditions:
This evaluation kit being sold by TI is intended for use for ENGINEERING DEVELOPMENT OR EV ALUATION
PURPOSES ONLY and is not considered by TI to be fit for commercial use. As such, the goods being provided
may not be complete in terms of required design-, marketing-, and/or manufacturing-related protective
considerations, including product safety measures typically found in the end product incorporating the goods.
As a prototype, this product does not fall within the scope of the European Union directive on electromagnetic
compatibility and therefore may not meet the technical requirements of the directive.
Should this evaluation kit not meet the specifications indicated in the EVM User’s Guide, the kit may be returned
within 30 days from the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE
WARRANTY MADE BY SELLER TO BUYER AND IS IN LIEU OF ALL OTHER W ARRANTIES, EXPRESSED,
IMPLIED, OR S TATUTOR Y, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY
PARTICULAR PURPOSE.
The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user
indemnifies TI from all claims arising from the handling or use of the goods. Please be aware that the products
received may not be regulatory compliant or agency certified (FCC, UL, CE, etc.). Due to the open construction
of the product, it is the user’s responsibility to take any and all appropriate precautions with regard to electrostatic
discharge.
EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER PARTY SHALL BE LIABLE
TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.
TI currently deals with a variety of customers for products, and therefore our arrangement with the user is not
exclusive.
TI assumes no liability for applications assistance, customer product design, software performance, or
infringement of patents or services described herein.
Please read the EVM User’s Guide and, specifically, the EVM Warnings and Restrictions notice in the EVM
User’s Guide prior to handling the product. This notice contains important safety information about temperatures
and voltages. For further safety concerns, please contact the TI application engineer.
Persons handling the product must have electronics training and observe good laboratory practice standards.
No license is granted under any patent right or other intellectual property right of TI covering or relating to any
machine, process, or combination in which such TI products or services might be or are used.
Mailing Address:
Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright 2002, Texas Instruments Incorporated
EVM WARNINGS AND RESTRICTIONS
It is important to operate this EVM within the specified input and output ranges described in
the EVM User’s Guide. The input supply voltage (±V
dual supply (V
input signal (V
should be no greater than 15 V for single supply operation). The differential
S
) should be no greater than ± 3 V . The output current (IO) should be no greater
ID
) should be no greater than ±7.5 V for
S
than 100 mA.
Exceeding the specified input range may cause unexpected operation and/or irreversible
damage to the EVM. If there are questions concerning the input range, please contact a TI
field representative prior to connecting the input power.
Applying loads outside of the specified output range may result in unintended operation and/or
possible permanent damage to the EVM. Please consult the EVM User ’s Guide prior to
connecting any load to the EVM output. If there is uncertainty as to the load specification,
please contact a TI field representative.
During normal operation, some circuit components may have case temperatures greater than
60°C. The EVM is designed to operate properly with certain components above 60°C as long
as the input and output ranges are maintained. These components include but are not limited
to linear regulators, switching transistors, pass transistors, and current sense resistors. These
types of devices can be identified using the EVM schematic located in the EVM User’s Guide.
When placing measurement probes near these devices during operation, please be aware
that these devices may be very warm to the touch.
Mailing Address:
Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright 2002, Texas Instruments Incorporated
Information About Cautions and Warnings
This book may contain cautions and warnings.
Information About Cautions and Warnings
Preface
Read This First
FCC Warning
This is an example of a caution statement.
A caution statement describes a situation that could potentially
damage your software or equipment.
This is an example of a warning statement.
A warning statement describes a situation that could potentially
cause harm to you.
The information in a caution or a warning is provided for your protection.
Please read each caution and warning carefully.
This equipment is intended for use in a laboratory test environment only. It ge nerates, uses, and can radiate radio frequency energy and has not been tested
for compliance with the limits of computing devices pursuant to subpart J of
part 15 of FCC rules, which are designed to provide reasonable protection
against radio frequency interference. Operation of this equipment in other environments may cause interference with radio communications, in which case
the user at his own expense will be required to take whatever measures may
be required to correct this interference.
iii
Trademarks
This EVM contains components that can potentially be damaged by
electrostatic discharge. Always transport and store the EVM in its
supplied ESD bag when not in use. Handle using an antistatic
wristband. Operate on an antistatic work surface. For more
information on proper handling, refer to SSYA008.
Related Documentation From Texas Instruments
The URL’s below are correct as of the date of publication of this manual. Texas
Instruments applications apologizes if they change over time.
- THS4271/THS4275 data sheet (SLOS397)
- Application report (SLMA002), PowerPAD Thermally Enhanced Package,
http://www-s.ti.com/sc/psheets/slma004/slma002.pdf
Trademarks
- Application report (SLMA004), PowerPAD Made Easy,
http://www-s.ti.com/sc/psheets/slma004/slma004.pdf
- Application report (SSYA008), Electrostatic Discharge (ESD),
http://www-s.ti.com/sc/psheets/ssya008/ssya008.pdf
- Application report (SLOA102), High Speed PCB Layout Tips,
http://www-s.ti.com/sc/psheets/sloa102/sloa102.pdf
PowerPAD is a trademark of Texas Instruments.
iv
Contents
Contents
1 Introduction and Description 1-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 Evaluation Schematic 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Using the EVM 2-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 EVM Applications 3-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 Default Configuration 3-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 EVM Hardware Description 4-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figures
1-1 Schematic of the THS4271EVM-UG Unity Gain 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-1 Test Equipment Connections 2-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-1 Default Configuration 3-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-2 Noninverting Gain Stage 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4-1 Board Layout Views 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tables
4-1 THS4271EVM-UG Unity Gain Bill of Materials 4-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
v
Chapter 1
Introduction and Description
This EVM provides a platform for testing the THS4271 in 8-pin LLP (DRB)
package in a noninverting, unity gain mode. It contains the high-speed op amp,
a number of passive components, and various features and footprints that
enable the user to experiment, test, and verify various operational amplifier
circuit implementations.
The THS4271 unity gain EVM was developed to reduce peaking caused by
lead inductance in the feedback path, which proved to be excessive in a more
general layout. This EVM is designed to minimize peaking in the unity gain
configuration. Each pad and trace on a PCB has an inductance associated
with it, when in conjunction with the inductance associated with the package
may cause peaking in the frequency response, hence, cause the device to become unstable.
Minimizing the inductance in the feedback path is critical for reducing the peaking of the frequency response in unity gain. The recommended maximum inductance allowed in the feedback path is 4 nH. This can be calculated by using
the following equation:
L(nH) + Kȏƪln
Where:
W = Width of trace
ȏ+Length of the trace
T = Thickness of the trace
K = 5.08 nH/inch
K = 0.2 nH/mm for Getek 4.2 epoxy polyphenylene oxide resin.
Dimensions are in inches unless otherwise specified.
2ȏ
W ) T
) 0.223
W ) T
ȏ
) 0.5
ƫ
Introduction and Description
1-1
Evaluation Schematic
1.1 Evaluation Schematic
As delivered, the EVM has a fully functional example circuit—just add power
supplies, a signal source, and monitoring instrument. See Figure 1–1 for a
complete schematic diagram. EVM features include:
- Wide operating supply voltage range: single supply 4.5 V to dual supply
±7.5 V operation (see the device data sheet). Single supply operation is
obtained by connecting both J6 (GND) and J7 (VS-) to ground.
- Nominal 50-Ω input impedance (R4). Termination can be configured
according to the application requirement.
- 50-Ω impedance traces on Vin+, and the Vin- to Vout connection (see
Figure 4-1—the vias provide the impedance)
- Convenient GND test point (TP1).
- 453-Ω series matching resistor (R6)—produces a 500-Ω load in
combination with resistor R7. 500 Ω is the standard data sheet load
impedance.
- Power supply ripple rejection capacitors (C1 and C2).
- Decoupling capacitors (C3, C4, C5, C6).
- Power PADt heatsinking capability.
- A good example of high-speed amplifier PCB design and layout.
Figure 1-1.Schematic of the THS4271EVM-UG Unity Gain
Vs+
7
U1
2
FB1
J2
Vin+
Vs-
J7
100 pF
R4
49.9 W
C6C5
0.1 mF
3
Vs-
+
4
Vs-
+
-
C1
22 mF
6
THS4271
J6
GND
R6
453 W
TP1
Vs+
+
C2
22 mF
R7
49.9 W
C3
0.1 mF
J4
Vout
FB2
J5
Vs+
C4
100 pF
1-2
Figure 2-1 shows how to connect power supplies, signal source and monitoring instrument. It is recommended that the user connect the EVM as shown
to avoid damage to the EVM or the op amp installed on the board.
Figure 2-1.Test Equipment Connections
Chapter 2
Using the EVM
Using the EVM
2-1
Example applications are presented in this chapter. These applications
demonstrate the most popular circuits, but many other circuits can be
constructed. The purpose of the EVM board is for the user to experiment with
different circuits, exploring new and creative design techniques, which is the
function of an evaluation board.
3.1 Default Configuration
Figure 3-1. Default Configuration
J2
Vin+
R4 R7
49.9 W
Chapter 3
EVM Applications
Vs+
U1
7
2
-
3
+
4
6
R6
453 W
J4
Vout
49.9 W
Vs-
Note: This schematic reflects the default THS4271EVM-UG unity gain configuration.
Power supply decoupling not shown.
The EVM output provides a 500-Ω load to the output of the EVM to provide
optimum performance (per the data sheet). The load is implemented as a
453-Ω resistor (R6) in series with the output to J4 (V
), and a 49.9-Ω output
out
load resistor (R7) from J4 to ground.
The gain measured from J2 to the ouput of the amplifier (pin 6) is 1. However,
the interaction between R6 and R7 causes the output at J4 to be attenuated
by 10:1.
When the EVM is monitored with a high input impedance instrument, R7 can
remain on the board—however, when the EVM is monitored with an
instrument that has an input impedance of 50 Ω, it is recommended that R7
be removed.
If the user provides an external load, R7 may be removed, and R6 replaced
with a 0-Ω jumper as shown in Figure 3-2. The EVM then provides a voltage
gain of 1 (0 dB) at the output connector J4.
EVM Applications
3-1
Default Configuration
Changing R6 to 49.9 Ω allows the EVM to connect to a 50-Ω load. This
amplifier is designed to attain optimum performance driving 500-Ω loads, but
100-Ω loads can be driven. See the data sheet for device characteristics.
Figure 3-2. Noninverting Gain Stage
J2
Vin+
Note: Power supply decoupling not shown.
R4
49.9 W
Vs+
U1
7
2
-
3
+
4
Vs-
6
R6
0
J4
Vout
3-2
EVM Hardware Description
This chapter describes the EVM hardware. It includes the EVM parts list, and
printed-circuit board layout.
Table 4-1.THS4271EVM-UG Unity Gain Bill of Materials
Chapter 4
Item Description SMD
Bead, ferrite, 3A, 80 Ω 1206 FB1, FB2
1
Capacitor, 22 µF, tantalum,
2
25 V, 10%
Capacitor, 100 pF, ceramic,
3
5%, 150 V
Capacitor, 0.1 µF, ceramic,
4
X7R, 50 V
Resistor, 49.9 Ω, 1/8 W, 1% 0805 R7
5
Resistor, 453 Ω, 1/8 W, 1% 0805 R6
6
Resistor, 49.9 Ω, 1/4 W, 1% 1206 R4
7
Test point, black TP1
8
Jack, banana receptacle, 0.25”
9
diameter hole
Connector, edge, SMA PCB
10
jack
Standoff, 4-40 hex, 0.625”
11
length
Screw, Phillips, 4-40, .250”
12
IC, THS4271 U1
13
Board, printed-circuit
14
Size
D C1, C2
AQ12 C4, C5
0805 C3, C6
J5, J6, J7
J2, J4
Reference
Designator
PCB
Manufacturer’s
QTY
Part Number
(Steward)
2
HI1206N800R-00
(AVX) TAJD226K025R (Garrett)
2
(AVX)
2
AQ12EM101JAJME
(AVX)
2
08055C104KAT2A
(PHYCOMP)
1
9C08052A49R9FKHFT
(PHYCOMP)
1
9C08052A4530FKHFT
(PHYCOMP)
1
9C12063A49R9FKRFT
(Keystone) 5001 (Allied) 839-3601
1
(HH Smith) 101 (Newark) 35F865
3
(Johnson)
2
142-0701-801
(Keystone) 1808 (Newark) 89F1934
4
SHR-0440-016-SN
4
(TI) THS4271DRB
1
(TI) Edge #6443547
1
Rev.A
Distributor’s
Part Number
(Digi-Key)
240-1010-1-ND
TAJD226K025R
(TTI)
AQ12EM101JAJME
(Garrett)
08055C104KAT2A
(Garrett)
9C08052A49R9FKHFT
(Garrett)
9C08052A4530FKHFT
(Garrett)
9C12063A49R9FKRFT
(Allied) 528-0238
EVM Hardware Description
4-1
Figure 4-1. Board Layout Views
Top
Layer 3 - Power
Layer 2 - Ground
Bottom
4-2
Mouser Electronics
Authorized Distributor
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THS4271EVM-UG
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