Texas Instruments THS4022IDR, THS4022IDGN, THS4022IDGNR, THS4022ID, THS4022EVM Datasheet
...
THS4021, THS4022
350-MHz LOW-NOISE HIGH-SPEED AMPLIFIERS
SLOS265B – SEPTEMBER 1999 – REVISED FEBRUARY 2000
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Ultra-Low 1.5 nV/√Hz Voltage Noise
D
High Speed
– 350 MHz Bandwidth (G = 10, –3 dB)
– 470 V/µs Slew Rate
– 40 ns Settling Time (0.1%)
D
Stable at a Gain of 10 (–9) or Greater
D
High Output Drive, IO = 100 mA (typ)
D
Excellent Video Performance
– 17 MHz Bandwidth (0.1 dB, G = 10)
– 0.02% Differential Gain
– 0.08° Differential Phase
D
Very Low Distortion
– THD = –68 dBc (f = 1 MHz, RL = 150 Ω)
D
Wide Range of Power Supplies
– VCC = ±5 V to ±15 V
D
Available in Standard SOIC or MSOP
PowerPAD Package
D
Evaluation Module Available
description
The THS4021 and THS4022 are ultra-low voltage
noise, high-speed voltage feedback amplifiers
that are ideal for applications requiring low voltage
noise, including communication and imaging. The
signal-amplifier THS4021 and the dual-amplifier
THS4022 offer very good ac performance with
350-MHz bandwidth, 470-V/µs slew rate, and
40-ns settling time (0.1%). The THS4021 and
THS4022 are stable at gains of 10 (–9) or greater.
These amplifiers have a high drive capability of
100 mA and draw only 7.8-mA supply current per
channel. With total harmonic distortion (THD) of
–68 dBc at f = 1 MHz, the THS4021 and THS4022
are ideally suited for applications requiring low
distortion.
RELATED DEVICES
DEVICE DESCRIPTION
THS4011/2
THS4031/2
THS4061/2
290-MHz Low Distortion High-Speed Amplifiers
100-MHz Low Noise High-Speed Amplifiers
180-MHz High-Speed Amplifiers
PowerPAD is a trademark of Texas Instruments Incorporated.
Copyright 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
THS4022
D AND DGN PACKAGE
(TOP VIEW)
1
2
3
4
8
7
6
5
1OUT
1IN–
1IN+
–V
CC
V
CC+
2OUT
2IN–
2IN+
1
2
3
4
8
7
6
5
NULL
IN–
IN+
V
CC–
NULL
V
CC+
OUT
NC
THS4021
D AND DGN PACKAGE
(TOP VIEW)
NC – No internal connection
Cross Section View Showing
PowerPAD Option (DGN)
Figure 1
f – Frequency – Hz
VOLTAGE & CURRENT NOISE
vs
FREQUENCY
VCC = ± 15 V and ± 5 V
TA = 25°C
100
1
10
nV/
Hz
– Voltage Noise –V
n
pA/
Hz
– Current Noise –I
n
10010 1 k 10 k 100 k
V
n
I
n
CAUTION: The THS4021 and THS4022 provide ESD protection circuitry. However , permanent damage can still occur if this device
is subjected to high-energy electrostatic discharges. Proper ESD precautions are recommended to avoid any performance
degradation or loss of functionality.
THS4021, THS4022
350-MHz LOW-NOISE HIGH-SPEED AMPLIFIERS
SLOS265B – SEPTEMBER 1999 – REVISED FEBRUARY 2000
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
AVAILABLE OPTIONS
PACKAGED DEVICES
T
A
NUMBER OF
CHANNELS
PLASTIC
SMALL OUTLINE
†
(D)
PLASTIC
MSOP
†
(DGN)
MSOP
SYMBOL
EVALUATION
MODULE
°
°
1 THS4021CD THS4021CDGN ACK THS4021EVM
0°C to 70°C
2 THS4022CD THS4022CDGN ACL THS4022EVM
°
°
1 THS4021ID THS4021IDGN ACA —
–
40°C to 85°C
2 THS4022ID THS4022IDGN ACB —
†
The D and DGN packages are available taped and reeled. Add an R suffix to the device type (i.e., THS4021CDGN).
functional block diagram
OUT
8
6
1
IN–
IN+
2
3
Null
Figure 2. THS4021 – Single Channel
1OUT
1IN–
1IN+
V
CC
2OUT
2IN–
2IN+
–V
CC
Figure 3. THS4022 – Dual Channel
THS4021, THS4022
350-MHz LOW-NOISE HIGH-SPEED AMPLIFIERS
SLOS265B – SEPTEMBER 1999 – REVISED FEBRUARY 2000
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
†
Supply voltage, VCC ±16.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, VI ±V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output current, IO 150 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential input voltage, V
IO
±4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum junction temperature, TJ 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature, TA: C-suffix 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I-suffix –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 300°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATING TABLE
θ
θ
T
= 25°C
PACKAGE
JA
(°C/W)
JC
(°C/W)
A
POWER RATING
D 167
‡
38.3 740 mW
DGN
§
58.4 4.7 2.14 W
‡
This data was taken using the JEDEC standard Low-K test PCB. For the JEDEC Proposed
High-K test PCB, the θJA is 95°C/W with a power rating at TA = 25°C of 1.32 W.
§
This data was taken using 2 oz. trace and copper pad that is soldered directly to a 3 in. × 3 in.
PC. For further information, refer to
Application Information
section of this data sheet.
recommended operating conditions
MIN NOM MAX UNIT
pp
Dual supply ±4.5 ±16
Suppl
y v
oltage, V
CC+
and V
CC–
Single supply 9 32
V
p
p
C-suffix 0 70
°
Operating free-air temperature, T
A
I-suffix –40 85
°C
THS4021, THS4022
350-MHz LOW-NOISE HIGH-SPEED AMPLIFIERS
SLOS265B – SEPTEMBER 1999 – REVISED FEBRUARY 2000
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at TA = 25°C, VCC = ±15 V, RL = 150 Ω (unless otherwise noted)
dynamic performance
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VCC = ±15 V
350
VCC = ±5 V
Gain
=
10
280
MH
z
Small-signal bandwidth (–3 dB)
VCC = ±15 V
80
VCC = ±5 V
Gain
=
20
70
MHzBW
VCC = ±15 V
17
Bandwidth for 0.1 dB flatness
VCC = ±5 V
Gain
=
10
17
MH
z
p
V
O(pp)
= 20 V, VCC = ±15 V 3.7
Full power bandwidth
†
V
O(pp)
= 5 V, VCC = ±5 V 11.8
MHz
VCC = ±15 V , 10-V step,
470
SR
Slew rate
‡
VCC = ±5 V, 5-V step
Gain
=
10
370
V/µs
VCC = ±15 V , 5-V step
40
Settling time to 0.1%
VCC = ±5 V, 2-V step
Gain
= –
10
50
ns
t
s
VCC = ±15 V , 5-V step
145
Settling time to 0.01%
VCC = ±5 V, 2-V step
Gain
= –
10
150
ns
†
Slew rate is measured from an output level range of 25% to 75%.
‡
Full power bandwidth = slew rate / 2π V
O(Peak)
.
noise/distortion performance
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RL = 150 Ω –68
V
pp
= 2 V,
V
CC
=
±15 V
RL = 1 kΩ –77
THD
Total harmonic distortion
O( )
,
f = 1 MHz, Gain = 2
RL = 150 Ω –69
dBc
V
CC
= ±5
V
RL = 1 kΩ –78
V
n
Input voltage noise VCC = ±5 V or ±15 V, f = 10 kHz 1.5 nV/√Hz
I
n
Input current noise VCC = ±5 V or ±15 V, f = 10 kHz 2 pA/√Hz
Gain = 2, NTSC,
VCC = ±15 V
Differential gain error
,
40 IRE modulation,,±100 IRE ramp
VCC = ±5 V
0.02%
p
Gain = 2, NTSC,
VCC = ±15 V 0.08°
Differential phase error
,
40 IRE modulation,,±100 IRE ramp
VCC = ±5 V
0.06°
X
T
Channel-to-channel crosstalk
(THS4022 only)
VCC = ±5 V or ±15 V, f = 1 MHz –60 dB
THS4021, THS4022
350-MHz LOW-NOISE HIGH-SPEED AMPLIFIERS
SLOS265B – SEPTEMBER 1999 – REVISED FEBRUARY 2000
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at TA = 25°C, VCC = ±15 V , RL = 150 Ω (unless otherwise noted) (continued)
dc performance
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
= ±15 V , V
= ±10 V ,
TA = 25°C 40 60
p
p
CC
,
RL = 1 kΩ
O
,
TA = full range 35
V/mV
Open loop gain
V
= ±5 V, V
= ±2.5 V ,
TA = 25°C 20 35
CC
,
RL = 250 Ω
O
,
TA = full range 15
V/mV
p
TA = 25°C 0.5 2
VOSInput offset voltage
TA = full range 3
mV
Offset voltage drift TA = full range 15 µV/°C
p
VCC = ±5 V or ±15 V
TA = 25°C 3 6
IIBInput bias current
TA = full range 6
µ
A
p
TA = 25°C 30 250
IOSInput offset current
TA = full range 400
nA
Offset current drift TA = full range 0.3 nA/°C
input characteristics
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
p
VCC = ±15 V ±13.8 ±14.3
V
ICR
Common-mode input voltage range
VCC = ±5 V ±3.8 ±4.3
V
CMRR Common mode rejection ratio VCC = ±15 V , V
ICR
= ±12 V , TA = full range 74 95 dB
r
i
Input resistance 1 MΩ
C
i
Input capacitance 1.5 pF
output characteristics
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VCC = ±15 V RL = 250 Ω ±12 ±12.5
p
VCC = ±5 V RL = 150 Ω ±3 ±3.3
V
VOOutput voltage swing
VCC = ±15 V
±13 ±13.5
VCC = ±5 V
R
L
= 1
kΩ
±3.4 ±3.8
V
VCC = ±15 V
80 100
I
O
Output
curren
t
VCC = ±5 V
R
L
= 20
Ω
50 75
mA
I
SC
Short-circuit current
†
VCC = ±15 V 150 mA
R
O
Output resistance
†
Open loop 13 Ω
†
Observe power dissipation ratings to keep the junction temperature below the absolute maximum rating when the output is heavily loaded or
shorted. See the absolute maximum ratings section of this data sheet for more information.
power supply
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
pp
p
Dual supply ±4.5 ±16.5
VCCSuppl
y v
oltage operating range
Single supply 9 33
V
TA = 25°C 7.8 10
pp
p
p
V
CC
=
±15 V
TA = full range 11
ICCSupply current (per amplifier)
TA = 25°C 6.7 9
mA
V
CC
=
±5 V
TA = full range 10.5
PSRR Power supply rejection ratio VCC = ±5 V or ±15 V TA = full range 80 95 dB
THS4021, THS4022
350-MHz LOW-NOISE HIGH-SPEED AMPLIFIERS
SLOS265B – SEPTEMBER 1999 – REVISED FEBRUARY 2000
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 4
10
0
–10
–20
–30
–40
–50
–60
–70
–80
1 M 10 M 100 M 1 G
f – Frequency – Hz
CROSSTALK
vs
FREQUENCY
Crosstalk – dB
VCC = ± 15 V
Gain = 10
RF = 220 Ω
RL = 150 Ω
Figure 5
OPEN LOOP GAIN AND
PHASE RESPONSE
vs
FREQUENCY
f – Frequency – Hz
100 M10 M100 k 1 M
–60
–90
0
30
–180
–120
Open Loop Gain – dB
Phase
10 k1 k 1 G
–150
–30
VCC = ± 5 V & ±15 V
Gain
Phase
–20
0
20
40
60
80
100
120
Figure 6
–40
–50
–60
–70
–80
–90
–100
VCC = ± 15 V
Gain = 10
V
O(PP)
= 2 V
100 k 1 M 10 M
TOTAL HARMONIC DISTORTION
vs
FREQUENCY
f – Frequency – Hz
THD – Total Harmonic Distortion – dBc
RL = 150 Ω
RL = 1 kΩ
Figure 7
–10
0
–30
–50
–70
–90
–110
5 101520
DISTORTION
vs
OUTPUT VOLTAGE
VO – Output Voltage – V
Distortion – dBc
VCC = ± 15 V
RL = 1 kΩ
G = 10
f = 1 MHz
2nd Harmonic
3rd Harmonic
Figure 8
–10
–30
–50
–70
–90
–110
0 5 10 15 20
DISTORTION
vs
OUTPUT VOLTAGE
Distortion – dBc
VO – Output Voltage – V
VCC = ± 15 V
RL = 150 Ω
G = 10
f = 1 MHz
2nd Harmonic
3rd Harmonic
Figure 9
–50
–60
–70
–80
–90
–100
100 k 1 M 10 M
DISTORTION
vs
FREQUENCY
f – Frequency – Hz
Distortion – dBc
2nd Harmonic
3rd Harmonic
VCC = ± 15 V
RL = 1 kΩ
G = 10
V
O(PP)
= 2 V
Figure 10
–50
–60
–70
–80
–90
–100
100 k 1 M 10 M
VCC = ± 5 V
RL = 1 kΩ
G = 10
V
O(PP)
= 2 V
2nd Harmonic
3rd Harmonic
DISTORTION
vs
FREQUENCY
f – Frequency – Hz
Distortion – dBc
Figure 11
VCC = ± 15 V
RL = 150 Ω
G = 10
V
O(PP)
= 2 V
2nd Harmonic
3rd Harmonic
–50
–60
–70
–80
–90
–100
100 k 1 M 10 M
DISTORTION
vs
FREQUENCY
f – Frequency – Hz
Distortion – dBc
THS4021, THS4022
350-MHz LOW-NOISE HIGH-SPEED AMPLIFIERS
SLOS265B – SEPTEMBER 1999 – REVISED FEBRUARY 2000
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 12
100 k 1 M 10 M
DISTORTION
vs
FREQUENCY
f – Frequency – Hz
Distortion – dBc
VCC = ± 5 V
RL = 150 Ω
G = 10
V
O(PP)
= 2 V
2nd Harmonic
3rd Harmonic
–40
–50
–60
–70
–80
–90
–100
Figure 13
25
20
15
10
10 k 100 k 1 M 10 M
100 M
1 G
VCC = ± 15 V
Gain = 10
RL = 150 Ω
V
O(PP)
= 400 mV
RF = 150 Ω
RF = 220 Ω
OUTPUT AMPLITUDE
vs
FREQUENCY
f – Frequency – Hz
Output Amplitude – dB
Figure 14
25
20
15
10
10 k 100 k 1 M 10 M
100 M
1 G
OUTPUT AMPLITUDE
vs
FREQUENCY
f – Frequency – Hz
Output Amplitude – dB
VCC = ± 5 V
Gain = 10
RL = 150 Ω
V
O(PP)
= 400 mV
RF = 220 Ω
RF = 150 Ω
Figure 15
OUTPUT AMPLITUDE
vs
FREQUENCY
Output Amplitude – dB
RF = 6.2 kΩ
RF = 220 Ω
f – Frequency – Hz
10
15
20
25
30
1 10 100 1000 10000
1 G10 M100 k 1 M 100 M
VCC = ±15 V
Gain = 20
RL = 150 Ω
V
O(PP)
= 400 mV
RF = 1 kΩ
OUTPUT AMPLITUDE
vs
FREQUENCY
f – Frequency – Hz
Output Amplitude – dB
Figure 16
10
15
20
25
30
1 10 100 1000 10000
1 G10 M100 k 1 M 100 M
RF = 6.2 kΩ
RF = 220 Ω
VCC = ±5 V
Gain = 20
RL = 150 Ω
V
O(PP)
= 400 mV
RF = 1 kΩ
Figure 17
–0.60
–0.40
–0.20
–0.00
0.20
0.40
0.60
0.80
0 50 100 150 200 250 300 350 400
1-V STEP RESPONSE
t – Time – ns
– Output Voltage – V
V
O
VCC = ± 5 V
Gain = 10
RF = 220 Ω
RL = 150 Ω
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
Figure 18
–3
–2
–1
0
1
2
3
0 50 100 150 200 250 300 350 400
5-V STEP RESPONSE
t – Time – ns
– Output Voltage – V
V
O
VCC = ± 5 V
Gain = –10
RF = 220 Ω
RL = 150 Ω
Figure 19
–0.6
–0.40
–0.20
–0.00
0.20
0.40
0.60
0.80
0 50 100 150 200 250 300 350 400
1-V STEP RESPONSE
t – Time – ns
– Output Voltage – V
V
O
VCC = ± 15 V
Gain = 10
RF = 220 Ω
RL = 150 Ω
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
Figure 20
–6
–4
–2
0
2
4
6
0 100 200 300 400 500
10-V STEP RESPONSE
t – Time – ns
– Output Voltage – V
V
O
VCC = ± 15 V
Gain = 10
RF = 220 Ω
RL = 150
THS4021, THS4022
350-MHz LOW-NOISE HIGH-SPEED AMPLIFIERS
SLOS265B – SEPTEMBER 1999 – REVISED FEBRUARY 2000
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 21
INPUT OFFSET VOLTAGE
vs
FREE-AIR TEMPERATURE
TA – Free-Air Temperature – °C
V
IO
– Input Offset Voltage – mV
–0.05
–0.10
–0.15
–0.20
–0.25
–0.30
–40 –20 0 20 40 60 80 100
VCC = ± 15 V
VCC = ± 5 V
Figure 22
3.30
3.25
3.20
3.15
3.10
3.05
3
–40 –20 0 20 40 60 80 100
INPUT BIAS CURRENT
vs
FREE-AIR TEMPERATURE
TA - Free-Air Temperature - °C
VCC = ± 5 V & ±15 V
Input Bias Current –
I
IB
µA
–
Figure 23
2
4
6
8
10
12
14
5 7 9 11 13 15
OUTPUT VOLTAGE
vs
SUPPLY VOLTAGE
±VCC – Supply Voltage – V
TA = 25°C
O
– Output Voltage –V
V
RL = 150 Ω
RL = 1 kΩ
Figure 24
3
5
7
9
11
13
15
5 7 9 11 13 15
TA = 25°C
COMMON-MODE INPUT VOLTAGE
vs
SUPPLY VOLTAGE
±VCC – Supply Voltage – V
– Common-Mode Input Voltage –
V
ICR
± V
0
2
4
6
8
10
12
14
–40 –20.00 0.00 20.00 40.00 60.00 80.00100.00
Figure 25
OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
TA – Free-Air Temperature – _C
VCC = ± 5 V
RL = 150 Ω
VCC = ± 5 V
RL = 1 kΩ
VCC = ± 15 V
RL = 250 Ω
VCC = ± 15 V
RL = 1 kΩ
–40 –20 0 20 40 60 80 100
O
– Output Voltage –V
V
Figure 26
11
10
9
8
7
6
5
579111315
TA=85°C
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
± VCC – Supply Voltage – V
I
CC
– Supply Current – mA
TA=–40°C
TA=25°C
Figure 27
f – Frequency – Hz
VOLTAGE & CURRENT NOISE
vs
FREQUENCY
VCC = ± 15 V and ± 5 V
TA = 25°C
100
1
10
nV/
Hz
– Voltage Noise –V
n
pA/
Hz
– Current Noise –I
n
10010 1 k 10 k 100 k
V
n
I
n
Figure 28
0
–10
–20
–30
–40
–50
–60
–70
–80
100 k 1 M 10 M 100 M 1 G
POWER SUPPLY REJECTION RATIO
vs
FREQUENCY
f – Frequency – Hz
PSRR – Power Supply Rejection Ratio – dB
VCC = ±15 V & ±5 V
–V
CC
+V
CC
Figure 29
0
–10
–20
–30
–40
–50
–60
100 k 1 M 10 M 100 M 1 G
CMRR
vs
FREQUENCY
CMRR – Common-Mode Rejection Ratio – dB
f – Frequency – Hz
VCC = ±15 V or ±5 V
RF = 20 kΩ
V
I(PP)
= 2 V
THS4021, THS4022
350-MHz LOW-NOISE HIGH-SPEED AMPLIFIERS
SLOS265B – SEPTEMBER 1999 – REVISED FEBRUARY 2000
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
theory of operation
The THS402x is a high-speed, operational amplifier configured in a voltage feedback architecture. It is built
using a 30-V , dielectrically isolated, complementary bipolar process with NPN and PNP transistors possessing
fTs of several GHz. This results in an exceptionally high performance amplifier that has a wide bandwidth, high
slew rate, fast settling time, and low distortion. A simplified schematic is shown in Figure 30.
IN– (2)
IN+ (3)
NULL (1) NULL (8)
(6) OUT
(4) VCC–
(7) VCC+
Figure 30. THS4021 Simplified Schematic
noise calculations and noise figure
Noise can cause errors on very small signals. This is especially true when amplifying small signals, where
signal-to-noise ratio (SNR) is very important. The noise model for the THS402x is shown in Figure 31. This
model includes all of the noise sources as follows:
• e
n
= Amplifier internal voltage noise (nV/√Hz)
• IN+ = Noninverting current noise (pA/√Hz)
• IN– = Inverting current noise (pA/√Hz)
• e
Rx
= Thermal voltage noise associated with each resistor (eRx = 4 kTRx)
THS4021, THS4022
350-MHz LOW-NOISE HIGH-SPEED AMPLIFIERS
SLOS265B – SEPTEMBER 1999 – REVISED FEBRUARY 2000
10
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APPLICATION INFORMATION
noise calculations and noise figure (continued)
_
+
R
F
R
S
R
G
e
Rg
e
Rf
e
Rs
e
n
IN+
Noiseless
IN–
e
ni
e
no
Figure 31. Noise Model
The total equivalent input noise density (eni) is calculated by using the following equation:
eni+ǒe
n
Ǔ
2
)
ǒ
IN
)
R
S
Ǔ
2
)ǒIN–
ǒRFø
R
G
Ǔ
Ǔ
2
)
4kTRs)
4kTǒRFø
R
G
Ǔ
Ǹ
Where:
k = Boltzmann’s constant = 1.380658 × 10
–23
T = Temperature in degrees Kelvin (273 +°C)
RF || RG = Parallel resistance of RF and R
G
To get the equivalent output noise of the amplifier, just multiply the equivalent input noise density (eni) by the
overall amplifier gain (AV).
eno+
eniAV+
e
ni
ǒ
1
)
R
F
R
G
Ǔ
(noninverting case)
As the previous equations show, to keep noise at a minimum, small value resistors should be used. As the
closed-loop gain is increased (by reducing RG), the input noise is reduced considerably because of the parallel
resistance term. This leads to the general conclusion that the most dominant noise sources are the source
resistor (RS) and the internal amplifier noise voltage (en). Because noise is summed in a root-mean-squares
method, noise sources smaller than 25% of the largest noise source can be effectively ignored. This can greatly
simplify the formula and make noise calculations much easier to calculate.
For more information on noise analysis, please refer to the
Noise Analysis
section in
Operational Amplifier
Circuits Applications Report
(literature number SLVA043).
THS4021, THS4022
350-MHz LOW-NOISE HIGH-SPEED AMPLIFIERS
SLOS265B – SEPTEMBER 1999 – REVISED FEBRUARY 2000
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APPLICATION INFORMATION
noise calculations and noise figure (continued)
This brings up another noise measurement usually preferred in RF applications, the noise figure (NF). Noise
figure is a measure of noise degradation caused by the amplifier. The value of the source resistance must be
defined and is typically 50 Ω in RF applications.
NF+10log
ȧ
ȧ
ȱ
Ȳ
e
2
ni
ǒ
e
Rs
Ǔ
2
ȧ
ȧ
ȳ
ȴ
Because the dominant noise components are generally the source resistance and the internal amplifier noise
voltage, we can approximate noise figure as:
NF+10log
ȧ
ȧ
ȧ
ȧ
ȧ
ȱ
Ȳ
1
)
ȧ
ȡ
Ȣ
ǒ
e
n
Ǔ
2
)ǒIN
)
R
S
Ǔ
2
ȧ
ȣ
Ȥ
4kTR
S
ȧ
ȧ
ȧ
ȧ
ȧ
ȳ
ȴ
Figure 32 shows the noise figure graph for the THS402x.
Source Resistance – Ω
Noise Figure – dB
NOISE FIGURE
vs
SOURCE RESISTANCE
0
2
4
6
8
10
12
14
16
10 100 1000 10000
1010
f = 10 kHz
TA = 25°C
100 1 k 10 k
Figure 32. Noise Figure vs Source Resistance
THS4021, THS4022
350-MHz LOW-NOISE HIGH-SPEED AMPLIFIERS
SLOS265B – SEPTEMBER 1999 – REVISED FEBRUARY 2000
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APPLICATION INFORMATION
driving a capacitive load
Driving capacitive loads with high performance amplifiers is not a problem as long as certain precautions are
taken. The first is to realize that the THS402x has been internally compensated to maximize its bandwidth and
slew rate performance. When the amplifier is compensated in this manner, capacitive loading directly on the
output will decrease the device’s phase margin leading to high frequency ringing or oscillations. Therefore, for
capacitive loads of greater than 10 pF, it is recommended that a resistor be placed in series with the output of
the amplifier, as shown in Figure 33. A minimum value of 20 Ω should work well for most applications. For
example, in 75-Ω transmission systems, setting the series resistor value to 75 Ω both isolates any capacitance
loading and provides the proper line impedance matching at the source end.
+
_
THS402x
C
LOAD
1 kΩ
Input
Output
50 Ω
20 Ω
Figure 33. Driving a Capacitive Load
offset nulling
The THS402x has very low input offset voltage for a high-speed amplifier . However, if additional correction is
required, an offset nulling function has been provided on the THS4021. The input offset can be adjusted by
placing a potentiometer between terminals 1 and 8 of the device and tying the wiper to the negative supply . This
is shown in Figure 34.
_
+
THS402x
VCC–
VCC+
0.1 µF
0.1 µF
10 kΩ
Figure 34. Offset Nulling Schematic
THS4021, THS4022
350-MHz LOW-NOISE HIGH-SPEED AMPLIFIERS
SLOS265B – SEPTEMBER 1999 – REVISED FEBRUARY 2000
13
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APPLICATION INFORMATION
offset voltage
The output offset voltage, (VOO) is the sum of the input offset voltage (VIO) and both input bias currents (IIB) times
the corresponding gains. The following schematic and formula can be used to calculate the output offset
voltage:
VOO+
V
IO
ǒ
1
) ǒ
R
F
R
G
Ǔ
Ǔ
"
I
IB
)
R
S
ǒ
1
) ǒ
R
F
R
G
Ǔ
Ǔ
"
I
IB–RF
+
–
V
I
+
R
G
R
S
R
F
I
IB–
V
O
I
IB+
Figure 35. Output Offset Voltage Model
general configurations
When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often
required. The simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifier
(see Figure 36).
V
I
V
O
C1
+
–
R
G
R
F
R1
f
–3dB
+
1
2pR1C1
V
O
V
I
+ ǒ
1
)
R
F
R
G
Ǔ
ǒ
1
1)sR1C1
Ǔ
Figure 36. Single-Pole Low-Pass Filter
THS4021, THS4022
350-MHz LOW-NOISE HIGH-SPEED AMPLIFIERS
SLOS265B – SEPTEMBER 1999 – REVISED FEBRUARY 2000
14
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APPLICATION INFORMATION
circuit layout considerations
To achieve the levels of high frequency performance of the THS402x, follow proper printed-circuit board high
frequency design techniques. A general set of guidelines is given below. In addition, a THS402x evaluation
board is available to use as a guide for layout or for evaluating the device performance.
D
Ground planes – It is highly recommended that a ground plane be used on the board to provide all
components with a low inductive ground connection. However, in the areas of the amplifier inputs and
output, the ground plane can be removed to minimize the stray capacitance.
D
Proper power supply decoupling – Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic
capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers
depending on the application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal
of every amplifier. In addition, the 0.1-µF capacitor should be placed as close as possible to the supply
terminal. As this distance increases, the inductance in the connecting trace makes the capacitor less
effective. The designer should strive for distances of less than 0.1 inches between the device power
terminals and the ceramic capacitors.
D
Sockets – Sockets are not recommended for high-speed operational amplifiers. The additional lead
inductance in the socket pins will often lead to stability problems. Surface-mount packages soldered directly
to the printed-circuit board is the best implementation.
D
Short trace runs/compact part placements – Optimum high frequency performance is achieved when stray
series inductance has been minimized. To realize this, the circuit layout should be made as compact as
possible, thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting
input of the amplifier. Its length should be kept as short as possible. This will help to minimize stray
capacitance at the input of the amplifier.
D
Surface-mount passive components – Using surface-mount passive components is recommended for high
frequency amplifier circuits for several reasons. First, because of the extremely low lead inductance of
surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small
size of surface-mount components naturally leads to a more compact layout, thereby minimizing both stray
inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be
kept as short as possible.
general PowerPAD design considerations
The THS402x is available packaged in a thermally-enhanced DGN package, which is a member of the
PowerP AD family of packages. This package is constructed using a downset leadframe upon which the die is
mounted [see Figure 37(a) and Figure 37(b)]. This arrangement results in the lead frame being exposed as a
thermal pad on the underside of the package [see Figure 37(c)]. Because this thermal pad has direct thermal
contact with the die, excellent thermal performance can be achieved by providing a good thermal path away
from the thermal pad.
The PowerP AD package allows for both assembly and thermal management in one manufacturing operation.
During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be
soldered to a copper area underneath the package. Through the use of thermal paths within this copper area,
heat can be conducted away from the package into either a ground plane or other heat dissipating device.
The PowerP AD package represents a breakthrough in combining the small area and ease of assembly of the
surface mount with the, heretofore, awkward mechanical methods of heatsinking.
THS4021, THS4022
350-MHz LOW-NOISE HIGH-SPEED AMPLIFIERS
SLOS265B – SEPTEMBER 1999 – REVISED FEBRUARY 2000
15
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APPLICATION INFORMATION
general PowerPAD design considerations (continued)
DIE
Side View (a)
End View (b) Bottom View (c)
DIE
Thermal
Pad
NOTE A: The thermal pad is electrically isolated from all terminals in the package.
Figure 37. Views of Thermally Enhanced DGN Package
Although there are many ways to properly heatsink this device, the following steps illustrate the recommended
approach.
Thermal pad area (68 mils x 70 mils) with 5 vias
(Via diameter = 13 mils)
Figure 38. PowerPAD PCB Etch and Via Pattern
1. Prepare the PCB with a top side etch pattern as shown in Figure 38. There should be etch for the leads as
well as etch for the thermal pad.
2. Place five holes in the area of the thermal pad. These holes should be 13 mils in diameter . Keep them small
so that solder wicking through the holes is not a problem during reflow.
3. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. This helps
dissipate the heat generated by the THS402xDGN IC. These additional vias may be larger than the 13-mil
diameter vias directly under the thermal pad. They can be larger because they are not in the thermal pad
area to be soldered, so wicking is not a problem.
4. Connect all holes to the internal ground plane.
5. When connecting these holes to the ground plane, do not use the typical web or spoke via connection
methodology . Web connections have a high thermal resistance connection that is useful for slowing the heat
transfer during soldering operations. This makes the soldering of vias that have plane connections easier.
In this application, however , low thermal resistance is desired for the most efficient heat transfer. Therefore,
the holes under the THS402xDGN package should make their connection to the internal ground plane with
a complete connection around the entire circumference of the plated-through hole.
6. The top-side solder mask should leave the terminals of the package and the thermal pad area with its five
holes exposed. The bottom-side solder mask should cover the five holes of the thermal pad area. This
prevents solder from being pulled away from the thermal pad area during the reflow process.
7. Apply solder paste to the exposed thermal pad area and all of the IC terminals.
8. With these preparatory steps in place, the THS402xDGN IC is simply placed in position and run through
the solder reflow operation as any standard surface-mount component. This results in a part that is properly
installed.
THS4021, THS4022
350-MHz LOW-NOISE HIGH-SPEED AMPLIFIERS
SLOS265B – SEPTEMBER 1999 – REVISED FEBRUARY 2000
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
general PowerPAD design considerations (continued)
The actual thermal performance achieved with the THS402xDGN in its PowerPAD package depends on the
application. In the example above, if the size of the internal ground plane is approximately 3 inches × 3 inches,
then the expected thermal coefficient, θJA, is about 58.4_C/W. For comparison, the non-PowerPAD version of
the THS402x IC (SOIC) is shown. For a given θJA, the maximum power dissipation is shown in Figure 39 and
is calculated by the following formula:
PD+
ǒ
T
MAX–TA
q
JA
Ǔ
Where:
PD= Maximum power dissipation of THS402x IC (watts)
T
MAX
= Absolute maximum junction temperature (150°C)
TA= Free-ambient air temperature (°C)
θ
JA
= θ
JC
+ θ
CA
θJC= Thermal coefficient from junction to case
θCA= Thermal coefficient from case to ambient air (°C/W)
DGN Package
θJA = 58.4°C/W
2 oz. Trace And Copper Pad
With Solder
DGN Package
θJA = 158°C/W
2 oz. Trace And
Copper Pad
Without Solder
SOIC Package
High-K Test PCB
θJA = 98°C/W
TJ = 150°C
SOIC Package
Low-K Test PCB
θJA = 167°C/W
2
1.5
1
0
–40 –20 0 20 40
Maximum Power Dissipation – W
2.5
3
MAXIMUM POWER DISSIPATION
vs
FREE-AIR TEMPERATURE
3.5
60 80 100
0.5
TA – Free-Air Temperature – °C
NOTE A: Results are with no air flow and PCB size = 3”× 3”
Figure 39. Maximum Power Dissipation vs Free-Air Temperature
More complete details of the PowerP AD installation process and thermal management techniques can be found
in the Texas Instruments Technical Brief,
PowerPAD Thermally Enhanced Package.
This document can be
found at the TI web site (www.ti.com) by searching on the key word PowerPAD. The document can also be
ordered through your local TI sales office. Refer to literature number SLMA002 when ordering.
THS4021, THS4022
350-MHz LOW-NOISE HIGH-SPEED AMPLIFIERS
SLOS265B – SEPTEMBER 1999 – REVISED FEBRUARY 2000
17
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APPLICATION INFORMATION
general PowerPAD design considerations (continued)
The next consideration is the package constraints. The two sources of heat within an amplifier are quiescent
power and output power. The designer should never forget about the quiescent heat generated within the
device, especially multiamplifier devices. Because these devices have linear output stages (Class A-B), most
of the heat dissipation is at low output voltages with high output currents. Figure 40 to Figure 43 show this effect,
along with the quiescent heat, with an ambient air temperature of 50°C. Obviously , as the ambient temperature
increases, the limit lines shown will drop accordingly. The area under each respective limit line is considered
the safe operating area. Any condition above this line will exceed the amplifier’s limits and failure may result.
When using V
CC
= ±5 V, there is generally not a heat problem, even with SOIC packages. But, when using
VCC = ±15 V , the SOIC package is severely limited in the amount of heat it can dissipate. The other key factor
when looking at these graphs is how the devices are mounted on the PCB. The PowerPAD devices are
extremely useful for heat dissipation. But, the device should always be soldered to a copper plane to fully use
the heat dissipation properties of the PowerPAD. The SOIC package, on the other hand, is highly dependent
on how it is mounted on the PCB. As more trace and copper area is placed around the device, θ
JA
decreases
and the heat dissipation capability increases. The currents and voltages shown in these graphs are for the total
package. For the dual amplifier package (THS4022), the sum of the RMS output currents and voltages should
be used to choose the proper package. The graphs shown assume that both amplifier’s outputs are identical.
Figure 40
Package With
θJA < = 120°C/W
SO-8 Package
θJA = 167°C/W
Low-K Test PCB
VCC = ± 5 V
Tj = 150°C
TA = 50°C
100
80
40
0
012 3
– Maximum RMS Output Current – mA
140
180
200
45
160
120
60
20
| VO | – RMS Output Voltage – V
I
O
||
Maximum Output
Current Limit Line
THS4021
MAXIMUM RMS OUTPUT CURRENT
vs
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
Safe Operating
Area
Figure 41
100
10
0369
1000
12 15
Maximum Output
Current Limit Line
SO-8 Package
θJA = 167°C/W
Low-K Test PCB
SO-8 Package
θJA = 98°C/W
High-K Test PCB
TJ = 150°C
TA = 50°C
| VO | – RMS Output Voltage – V
– Maximum RMS Output Current – mA
I
O
||
VCC = ± 15 V
DGN Package
θJA = 58.4°C/W
THS4021
MAXIMUM RMS OUTPUT CURRENT
vs
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
Safe Operating
Area
THS4021, THS4022
350-MHz LOW-NOISE HIGH-SPEED AMPLIFIERS
SLOS265B – SEPTEMBER 1999 – REVISED FEBRUARY 2000
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
general PowerPAD design considerations (continued)
Figure 42
Package With
θJA ≤ 60°C/W
SO-8 Package
θJA = 98°C/W
High-K Test PCB
VCC = ± 5 V
TJ = 150°C
TA = 50°C
Both Channels
100
80
40
0
012 3
– Maximum RMS Output Current – mA
140
180
200
45
160
120
60
20
| VO | – RMS Output Voltage – V
I
O
||
Maximum Output
Current Limit Line
THS4022
MAXIMUM RMS OUTPUT CURRENT
vs
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
SO-8 Package
θJA = 167°C/W
Low-K Test PCB
Safe Operating Area
Figure 43
100
10
0369
1000
12 15
Maximum Output
Current Limit Line
| VO | – RMS Output Voltage – V
– Maximum RMS Output Current – mA
I
O
||
VCC = ± 15 V
TJ = 150°C
TA = 50°C
Both Channels
THS4022
MAXIMUM RMS OUTPUT CURRENT
vs
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
1
SO-8 Package
θJA = 167°C/W
Low-K Test PCB
DGN Package
θJA = 58.4°C/W
Safe Operating Area
SO-8 Package
θJA = 98°C/W
High-K Test PCB
THS4021, THS4022
350-MHz LOW-NOISE HIGH-SPEED AMPLIFIERS
SLOS265B – SEPTEMBER 1999 – REVISED FEBRUARY 2000
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
evaluation board
An evaluation board is available for the THS4021 (literature number SLOP129) and THS4022 (literature number
SLOP231). This board has been configured for very low parasitic capacitance in order to realize the full
performance of the amplifier. A schematic of the evaluation board is shown in Figure 44. The circuitry has been
designed so that the amplifier may be used in either an inverting or noninverting configuration. For more
information, please refer to the
THS4021 EVM User’s Guide
or the
THS4022 EVM User’s Guide
. To order the
evaluation board, contact your local TI sales office or distributor.
_
+
THS4021
VCC–
VCC+
C1
6.8 µF
C4
0.1 µF
C2
6.8 µF
C3
0.1 µF
R4
1 kΩ
R2
49.9 Ω
R3
49.9 Ω
R5
49.9 Ω
IN–
IN+
NULL
OUT
NULL
+
+
Figure 44. THS4021 Evaluation Board
THS4021, THS4022
350-MHz LOW-NOISE HIGH-SPEED AMPLIFIERS
SLOS265B – SEPTEMBER 1999 – REVISED FEBRUARY 2000
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL INFORMATION
D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
4040047/D 10/96
0.228 (5,80)
0.244 (6,20)
0.069 (1,75) MAX
0.010 (0,25)
0.004 (0,10)
1
14
0.014 (0,35)
0.020 (0,51)
A
0.157 (4,00)
0.150 (3,81)
7
8
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.010 (0,25)
PINS **
0.008 (0,20) NOM
A MIN
A MAX
DIM
Gage Plane
0.189
(4,80)
(5,00)
0.197
8
(8,55)
(8,75)
0.337
14
0.344
(9,80)
16
0.394
(10,00)
0.386
0.004 (0,10)
M
0.010 (0,25)
0.050 (1,27)
0°–8°
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
THS4021, THS4022
350-MHz LOW-NOISE HIGH-SPEED AMPLIFIERS
SLOS265B – SEPTEMBER 1999 – REVISED FEBRUARY 2000
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL INFORMATION
DGN (S-PDSO-G8) PowerPAD PLASTIC SMALL-OUTLINE PACKAGE
0,69
0,41
0,25
Thermal Pad
(See Note D)
0,15 NOM
Gage Plane
4073271/A 01/98
4,98
0,25
5
3,05
4,78
2,95
8
4
3,05
2,95
1
0,38
0,15
0,05
1,07 MAX
Seating Plane
0,10
0,65
M
0,25
0°–6°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions include mold flash or protrusions.
D. The package thermal performance may be enhanced by attaching an external heat sink to the thermal pad. This pad is electrically
and thermally connected to the backside of the die and possibly selected leads.
E. Falls within JEDEC MO-187
PowerPAD is a trademark of Texas Instruments Incorporated.
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
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pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
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CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
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In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
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