TEXAS INSTRUMENTS THS1031 Technical data

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THS1031

2.7 V – 5.5 V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS242A – NOVEMBER 1999 – REVISED JANUARY 2000

D

10-Bit Resolution 30 MSPS
Analog-to-Digital Converter:

D

Configurable Input Functions:
– Single-Ended
– Single-Ended With Analog Clamp
– Single-Ended With Programmable Digital

Clamp

– Differential

D

Built-in Programmable Gain Amplifier
(PGA)

D

Differential Nonlinearity: ±0.3 LSB

D

Signal-to-Noise: 56 dB

D

Spurious Free Dynamic Range: 60 dB

D

Adjustable Internal Voltage Reference

D

Straight Binary/2s Complement Output

D

Out-of-Range Indicator

D

Power-Down Mode

28-PIN TSSOP/SOIC PACKAGE

AGND

DV

DGND

DD

I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9

OVR

(TOP VIEW)

1

28

2

27

3

26

4

25

5

24

6

23

7

22

8

21

9

20

10

19

11

18

12

17

13

16

14

15

AV

DD

AIN
V

REF

REFBS
REFBF
MODE
REFTF
REFTS
CLAMPIN
CLAMP
REFSENSE
WR
OE
CLK

description

The THS1031 is a CMOS, low power, 10-bit, 30 MSPS analog-to-digital converter (ADC) that can operate with
a supply range from 2.7 V to 3.3 V . The THS1031 has been designed to give circuit developers more flexibility.
The analog input to the THS1031 can be either single-ended or differential. This device has a built-in clamp
amplifier whose clamp input level can be selected from an external dc source or from an internal high-precision
10-bit digital clamp level programmable via an internal CLAMP register. A 3-bit PGA is included to maintain SNR
for small signal. The THS1031 provides a wide selection of voltage reference to match the user’s design
requirements. For more design flexibility , the internal reference can be bypassed to use an external reference
to suit the dc accuracy and temperature drift requirements of the application. The out-of-range output is used
to monitor any out-of-range condition in THS1031’s input range. The format of digital output can be coded in
either straight binary or 2s complement.

The speed, resolution, and single-supply operation of the THS1031 are suited for applications in set-top-box
(STB), video, multimedia, imaging, high-speed acquisition, and communications. The built-in clamp function
allows dc restoration of video signal and is suitable for video application. The speed and resolution ideally suit
charge-couple device (CCD) input systems such as color scanners, digital copiers, digital cameras, and
camcorders. A wide input voltage range between REFBS and REFTS allows the THS1031 to be applied in both
imaging and communications systems

The THS1031I is characterized for operation from –40°C to 85°C.

AVAILABLE OPTIONS

PACKAGED DEVICES

Copyright  2000, Texas Instruments Incorporated

0°C to 70°C THS1031CPW THS1031CDW

–40°C to 85°C THS1031IPW THS1031IDW

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

A

28-TSSOP (PW) 28-SOIC (DW)

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1

THS1031

2.7 V – 5.5 V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS242A – NOVEMBER 1999 – REVISED JANUARY 2000

functional block diagram

CLAMPIN

CLAMP

SW2

CLAMP

DAC

Power

Down

10

WR

CTL

REG

AIN

REFTS

REFBS

MODE

REFTF

REFBF

SW1

SHA

SW3

VBG

SW4

REFSENSE V

REF

DC

REF

3

PGA

DAC REF

A/D

Output

Buffers

Timing
Circuit

BIN/2’S

I/O0 –
I/O9

OVR

OE

CLK

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

I/O

DESCRIPTION

2.7 V – 5.5 V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS242A – NOVEMBER 1999 – REVISED JANUARY 2000

Terminal Functions

TERMINAL

NAME NO.

AGND 1 I Analog ground
AIN 27 I Analog input
AV

DD

CLAMP 19 I HI to enable CLAMP mode, LO to disable CLAMP mode
CLAMPIN 20 I Connect to an external analog clamp reference input.
CLK 15 I Clock input
DGND 14 I Digital ground
DV

DD

I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9

MODE 23 I Mode input
OE 16 I HI to the 3-state data bus, LO to enable the data bus
OVR 13 O Out-of-range indicator
REFBS 25 I Reference bottom sense
REFBF 24 I Reference bottom decoupling
REFSENSE 18 I Reference sense
REFTF 22 I Reference top decoupling
REFTS 21 I Reference top sense
V

REF

WR 17 I Write strobe goes HI to write data value D0:D9 to the internal registers.

28 I Analog supply

2 I Digital driver supply
3

4
5
6
7
8

9
10
11
12

26 I/O Internal and external reference for ADC

Digital I/O bit 0 (LSB)
Digital I/O bit 1
Digital I/O bit 2
Digital I/O bit 3
Digital I/O bit 4

I/O

Digital I/O bit 5
Digital I/O bit 6
Digital I/O bit 7
Digital I/O bit 8
Digital I/O bit 9 (MSB)

THS1031

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3

THS1031

Suppl

oltage

Maximum sampling rate

MSPS

V

2.7 V – 5.5 V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS242A – NOVEMBER 1999 – REVISED JANUARY 2000

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

†

Supply voltage: AVDD to AGND, DVDD to DGND –0.3 to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

AGND to DGND –0.3 to 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

AV

to DVDD –6.5 to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DD

Mode input MODE to AGND –0.3 to A VDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reference voltage input range REFTF, REFTB, REFTS, REFBS to AGND –0.3 to A VDD + 0.3 V. . . . . . . . .

Analog input voltage range AIN to AGND –0.3 to A VDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reference input V
Reference output V

to AGND –0.3 to A VDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

REF

to AGND –0.3 to A VDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

REF

Clock input CLK to AGND –0.3 to A VDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Digital input to DGND –0.3 to DVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Digital output to DGND –0.3 to DVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating junction temperature range, T
Storage temperature range, T

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

STG

0°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

J

Lead temperature 1,6 mm (1/16 in) from case for 10 seconds 300°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

digital inputs

MIN NOM MAX UNIT

High-level input voltage, V
Low-level input voltage, V

IH

IL

analog inputs

Analog input voltage, V
Reference input voltage, V
Reference input voltage, V
Reference input voltage, V
Clamp input voltage, V

I(AIN)

I(VREF)
I(REFTS)
I(REFBS)

I(CLAMPIN)

power supply

AV

pp

y v

p

= 30

DV

DD

DD

REFTS, REFBS reference voltages (MODE = AVDD)

PARAMETER MIN TYP MAX UNIT

REFTS Reference input voltage (top) 1 AV
REFBS Reference input voltage (bottom) 0 AVDD–1 V

Differential input (REFTS – REFBS) 1 2 V
Switched input capacitance on REFTS 0.6 pF
Switched input capacitance on REFBS 0.6 pF

2.4 V

0.2 x DV

MIN NOM MAX UNIT

REFBS REFTS V

1 2 V
1 AV
0 AVDD–1 V

REFBS REFTS V

MIN NOM MAX UNIT

2.7 3 5.5

2.7 3 5.5

DD

DD

DD

V

V

V

sampling rate and resolution

Fs 5 30 MHz
Resolution 10 Bits

4

PARAMETER MIN NOM MAX UNIT

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Input common mode (REFTF

REFBF)/2

V

V

V

V

REFTF (MODE

AVDD)

V

2 V

V

V

V

V

REFBF (MODE

AVDD)

V

V

V

THS1031

2.7 V – 5.5 V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS242A – NOVEMBER 1999 – REVISED JANUARY 2000

electrical characteristics, A VDD = 3 V , DVDD = 3 V , Fs = 30 MSPS/50% duty cycle, MODE = A VDD, 2 V
input span from 0.5 V to 2.5 V , external reference, PGA = 1X, T
noted)

analog inputs

PARAMETER MIN TYP MAX UNIT

V

I(AIN)

C

I

FPBW Full power BW (–3 dB) 150 MHz

REFTF, REFBF reference voltages

Differential input (REFTF – REFBF) 1 2 V

p

Input resistance between REFTF and REFBF 600 Ω

Analog input voltage REFBS REFTS V
Switched input capacitance 1.2 pF

DC leakage current (input = ±FS) 100 µA

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

+

= 1

REF

=

=

REF

= 1

REF

=

= 2

REF

= –40°C to 85°C (unless otherwise

A

AVDD = 3 V 1.3 1.5 1.7
AVDD = 5 V 2 2.5 3
AVDD = 3 V 2
AVDD = 5 V 3
AVDD = 3 V 2.5
AVDD = 5 V 3.5
AVDD = 3 V 1
AVDD = 5 V 0.5
AVDD = 3 V 2
AVDD = 5 V 1.5

V

reference voltages

REF

PARAMETER MIN TYP MAX UNIT

Internal 1 V reference (REFSENSE = V
Internal 2 V reference (REFSENSE = AVSS) 1.90 2 2.10 V
External reference (REFSENSE = AVDD) 1 2 V
Reference input resistance 18 kΩ

) 0.95 1 1.05 V

REF

dc accuracy

PARAMETER MIN TYP MAX UNIT

INL Integral nonlinearity ±1 ±2 LSB
DNL Differential nonlinearity ±0.3 ±1 LSB

Offset error 0.4 1.4 %FSR
Gain error 1.4 3.5 %FSR
Missing code No missing code assured

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5

THS1031

ENOB

Effective number of bits

Bits

SFDR

Spurious free dynamic range

dB

THD

Total harmonic distortion

dB

SNR

Signal-to-noise

dB

SINAD

Signal-to-noise and distortion

dB

2.7 V – 5.5 V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS242A – NOVEMBER 1999 – REVISED JANUARY 2000

electrical characteristics, A VDD = 3 V , DVDD = 3 V , Fs = 30 MSPS/50% duty cycle, MODE = A VDD, 2 V
input span from 0.5 V to 2.5 V , external reference, PGA = 1X, T
noted) (continued)

dynamic performance (ADC and PGA)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

f = 3.5 MHz 8.2 9
f = 3.5 MHz, AVDD = 5 V 8.8
f = 15 MHz 7.7
f = 15 MHz, AVDD = 5 V 7.64
f = 3.5 MHz 55 60

p

f = 3.5 MHz, AVDD = 5 V 63
f = 15 MHz 48
f = 15 MHz, AVDD = 5 V 52.4
f = 3.5 MHz –58.2 –54.7
f = 3.5 MHz, AVDD = 5 V –68.7
f = 15 MHz –47
f = 15 MHz, AVDD = 5 V –51.9
f = 3.5 MHz 51.2 56
f = 3.5 MHz, AVDD = 5 V 55
f = 15 MHz 53
f = 15 MHz, AVDD = 5 V 49.3
f = 3.5 MHz 51.1 56
f = 3.5 MHz, AVDD = 5 V 55
f = 15 MHz 48.1
f = 15 MHz, AVDD = 5 V 47.7

= –40°C to 85°C (unless otherwise

A

PGA

PARAMETER MIN TYP MAX UNIT

Gain range (linear scale) 0.5 4 V/V
Gain step size (linear scale) 0.5
Gain error from nominal 3%
Number of control bits 3 Bits

clamp DAC

PARAMETER MIN TYP MAX UNIT

Resolution 10 Bits
DAC output range REFBF REFTF
Clamping analog output voltage range 0.1 AVDD–0.1 V
Clamping analog output voltage error – 40 + 40 mV

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PDPower dissipation

mW

THS1031

2.7 V – 5.5 V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS242A – NOVEMBER 1999 – REVISED JANUARY 2000

electrical characteristics, A VDD = 3 V , DVDD = 3 V , Fs = 30 MSPS/50% duty cycle, MODE = A VDD, 2 V
input span from 0.5 V to 2.5 V , external reference, PGA = 1X, T
noted) (continued)

clock

PARAMETER MIN TYP MAX UNIT

t

CK

t

CKH

t

CKL

t

d

t

(ap)

timing

t

(PZ)

t

(DEN)

t

(OEW)

t

(WOE)

t

(WP)

t

(DS)

t

(DH)

power supply

I

CC

PD(STBY) Standby power AVDD = DVDD = 3 V, MODE = AGND 3 5 mW

Clock period 33 ns
Pulse duration, clock high 15 16.5 ns
Pulse duration, clock high 15 16.5 ns
Clock to data valid 25 ns
Pipeline latency 3 Cycles
Aperture delay 4 ns
Aperture uncertainty (jitter) 2 ps

PARAMETER MIN TYP MAX UNIT

Output disable to high-Z output 0 20 ns
Output enable to output valid 0 20 ns
Output disable to write enable 12 ns
Output disable to write enable 12 ns
Write pulse 15 ns
Input data setup time 5 ns
Input data hold time 5 ns

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Operating supply current AVDD = 3 V, MODE = AGND 30.6 45 mA

p

AVDD = DVDD = 3 V 94 135
AVDD = DVDD = 5 V 160

= –40°C to 85°C (unless otherwise

A

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

7

THS1031

2.7 V – 5.5 V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS242A – NOVEMBER 1999 – REVISED JANUARY 2000

PARAMETER MEASUREMENT INFORMATION

OE

WE

I/O

NOTE A: All timing measurements are based on 50% of edge transition.

Analog Input

t

(DZ)

Sample 1

(See Note A)

t

(OEW)

Sample 2

t(C

K)

t

(WP)

t

(DH)

t

(DS)

hi–Z hi–Z

Input OutputOutput

Figure 1. Write Timing Diagram

Sample 3

Sample 4

t

(WOE)

t

(DEN)

Sample 5

t

t

(CKH)

Input Clock

Digital Output

NOTE A: All timing measurements are based on 50% of edge transition.

(See

Note A)

(CKL)

Pipeline Latency

Figure 2. Digital Output Timing Diagram

t

d

Sample 1 Sample 2

8

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