The THS1031 is a CMOS, low power, 10-bit, 30 MSPS analog-to-digital converter (ADC) that can operate with
a supply range from 2.7 V to 3.3 V . The THS1031 has been designed to give circuit developers more flexibility.
The analog input to the THS1031 can be either single-ended or differential. This device has a built-in clamp
amplifier whose clamp input level can be selected from an external dc source or from an internal high-precision
10-bit digital clamp level programmable via an internal CLAMP register. A 3-bit PGA is included to maintain SNR
for small signal. The THS1031 provides a wide selection of voltage reference to match the user’s design
requirements. For more design flexibility , the internal reference can be bypassed to use an external reference
to suit the dc accuracy and temperature drift requirements of the application. The out-of-range output is used
to monitor any out-of-range condition in THS1031’s input range. The format of digital output can be coded in
either straight binary or 2s complement.
The speed, resolution, and single-supply operation of the THS1031 are suited for applications in set-top-box
(STB), video, multimedia, imaging, high-speed acquisition, and communications. The built-in clamp function
allows dc restoration of video signal and is suitable for video application. The speed and resolution ideally suit
charge-couple device (CCD) input systems such as color scanners, digital copiers, digital cameras, and
camcorders. A wide input voltage range between REFBS and REFTS allows the THS1031 to be applied in both
imaging and communications systems
The THS1031I is characterized for operation from –40°C to 85°C.
AVAILABLE OPTIONS
PACKAGED DEVICES
Copyright 2000, Texas Instruments Incorporated
0°C to 70°CTHS1031CPWTHS1031CDW
–40°C to 85°CTHS1031IPWTHS1031IDW
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
CLAMP19IHI to enable CLAMP mode, LO to disable CLAMP mode
CLAMPIN20IConnect to an external analog clamp reference input.
CLK15IClock input
DGND14IDigital ground
DV
DD
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
MODE23IMode input
OE16IHI to the 3-state data bus, LO to enable the data bus
OVR13OOut-of-range indicator
REFBS25IReference bottom sense
REFBF24IReference bottom decoupling
REFSENSE18IReference sense
REFTF22IReference top decoupling
REFTS21IReference top sense
V
REF
WR17IWrite strobe goes HI to write data value D0:D9 to the internal registers.
28IAnalog supply
2IDigital driver supply
3
4
5
6
7
8
9
10
11
12
26I/OInternal and external reference for ADC
Digital I/O bit 0 (LSB)
Digital I/O bit 1
Digital I/O bit 2
Digital I/O bit 3
Digital I/O bit 4
I/O
Digital I/O bit 5
Digital I/O bit 6
Digital I/O bit 7
Digital I/O bit 8
Digital I/O bit 9 (MSB)
Lead temperature 1,6 mm (1/16 in) from case for 10 seconds 300°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
digital inputs
MINNOMMAXUNIT
High-level input voltage, V
Low-level input voltage, V
IH
IL
analog inputs
Analog input voltage, V
Reference input voltage, V
Reference input voltage, V
Reference input voltage, V
Clamp input voltage, V
I(AIN)
I(VREF)
I(REFTS)
I(REFBS)
I(CLAMPIN)
power supply
AV
pp
y v
p
= 30
DV
DD
DD
REFTS, REFBS reference voltages (MODE = AVDD)
PARAMETERMINTYPMAXUNIT
REFTSReference input voltage (top)1AV
REFBSReference input voltage (bottom)0AVDD–1V
Differential input (REFTS – REFBS)12V
Switched input capacitance on REFTS0.6pF
Switched input capacitance on REFBS0.6pF
2.4V
0.2 x DV
MINNOMMAXUNIT
REFBSREFTSV
12V
1AV
0AVDD–1V
REFBSREFTSV
MINNOMMAXUNIT
2.735.5
2.735.5
DD
DD
DD
V
V
V
sampling rate and resolution
Fs530MHz
Resolution10Bits
4
PARAMETERMINNOMMAXUNIT
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Input common mode (REFTF
REFBF)/2
V
V
V
V
REFTF (MODE
AVDD)
V
2 V
V
V
V
V
REFBF (MODE
AVDD)
V
V
V
THS1031
2.7 V – 5.5 V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242A – NOVEMBER 1999 – REVISED JANUARY 2000
electrical characteristics, A VDD = 3 V , DVDD = 3 V , Fs = 30 MSPS/50% duty cycle, MODE = A VDD, 2 V
input span from 0.5 V to 2.5 V , external reference, PGA = 1X, T
noted)
analog inputs
PARAMETERMINTYPMAXUNIT
V
I(AIN)
C
I
FPBWFull power BW (–3 dB)150MHz
REFTF, REFBF reference voltages
Differential input (REFTF – REFBF)12V
p
Input resistance between REFTF and REFBF600Ω
Analog input voltageREFBSREFTSV
Switched input capacitance1.2pF
electrical characteristics, A VDD = 3 V , DVDD = 3 V , Fs = 30 MSPS/50% duty cycle, MODE = A VDD, 2 V
input span from 0.5 V to 2.5 V , external reference, PGA = 1X, T
noted) (continued)
dynamic performance (ADC and PGA)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
f = 3.5 MHz8.29
f = 3.5 MHz, AVDD = 5 V8.8
f = 15 MHz7.7
f = 15 MHz, AVDD = 5 V7.64
f = 3.5 MHz5560
p
f = 3.5 MHz, AVDD = 5 V63
f = 15 MHz48
f = 15 MHz, AVDD = 5 V52.4
f = 3.5 MHz–58.2 –54.7
f = 3.5 MHz, AVDD = 5 V–68.7
f = 15 MHz–47
f = 15 MHz, AVDD = 5 V–51.9
f = 3.5 MHz51.256
f = 3.5 MHz, AVDD = 5 V55
f = 15 MHz53
f = 15 MHz, AVDD = 5 V49.3
f = 3.5 MHz51.156
f = 3.5 MHz, AVDD = 5 V55
f = 15 MHz48.1
f = 15 MHz, AVDD = 5 V47.7
= –40°C to 85°C (unless otherwise
A
PGA
PARAMETERMINTYPMAXUNIT
Gain range (linear scale)0.54V/V
Gain step size (linear scale)0.5
Gain error from nominal3%
Number of control bits3Bits
clamp DAC
PARAMETERMINTYPMAXUNIT
Resolution10Bits
DAC output rangeREFBFREFTF
Clamping analog output voltage range0.1AVDD–0.1V
Clamping analog output voltage error– 40+ 40mV
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PDPower dissipation
mW
THS1031
2.7 V – 5.5 V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242A – NOVEMBER 1999 – REVISED JANUARY 2000
electrical characteristics, A VDD = 3 V , DVDD = 3 V , Fs = 30 MSPS/50% duty cycle, MODE = A VDD, 2 V
input span from 0.5 V to 2.5 V , external reference, PGA = 1X, T
noted) (continued)
Output disable to high-Z output020ns
Output enable to output valid020ns
Output disable to write enable12ns
Output disable to write enable12ns
Write pulse15ns
Input data setup time5ns
Input data hold time5ns
The MODE pin is used to select the reference source for the ADC.
D
Internal ADC Reference: Connect the MODE pin to A VDD to use the reference source for ADC generated
on the V
(REFTF+REFBF)/2 is set to a voltage for optimum operation of the ADC (near AVDD/2).
D
External ADC Reference: To supply an external reference source to the ADC, connect the MODE pin to
AGND. An external reference source should be connected to REFTF/REFTS and REFBF/REFBS.
MODE = AGND closes internal switches to allow a Kelvin connection through REFTS/REFBS, and disables
the on-chip amplifiers which drive on to the ADC references. Differential input is not supported
analog input mode
single-ended input
The single-ended input can be configured to work with either an external ADC reference or internal ADC
reference.
pin. (See V
REF
REFERENCE described in Table 2) such that (REFTF–REFBF) = V
REF
REF
and
D
External ADC Reference Mode: A single-ended analog input is accepted at the AIN pin where the input
signal is bounded by the voltages on the REFTS and REFBS pins. Figure 15 shows an example of applying
external reference to REFTS and REFBS pins in which REFTS is connected to the low-impedance 2-V
source and REFBS is connected to the low-impedance 2-V source. REFTS and REFBS may be driven to
any voltage within the supply as long as the difference (REFTS – REFBS) is between 1 V and 2 V as
specified in Table 2. Figure 16 shows an example of external-reference using a Kelvin connection to
eliminate line voltage drop errors.
2 V
1 V
2 V
1 V
0.1 µF
AIN
REFTS
REFBS
MODE
SW3
REFTF
10 µF0.1 µF
THS1031
SHA
PGA
A/D
16
REFBF
0.1 µF
Figure 15. External ADC Reference Mode
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
analog input mode(continued)
THS1031
2.7 V – 5.5 V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242A – NOVEMBER 1999 – REVISED JANUARY 2000
PRINCIPLES OF OPERATION
REFT
REFB
0.1
µF
0.1 µF
REFTF
REFBF
0.1 µF
0.1 µF
0.1 µF
AIN
REFTS
REFBS
MODE
SW3
REFTF
10 µF
REFBF
THS1031
SHAA/DPGA
Figure 16. Kelvin Connection With External ADC Reference Mode
D
Internal ADC Reference Mode With External Input Common Mode: The input common mode is supplied
to pins REFTS and REFBS while connected together. The input signal should be centered around this
common mode with peak-to-peak input equal to the voltage on the V
pin. Input can be either dc-coupled
REF
or ac-coupled to the same common mode voltage (Figure 17) or any other voltage within the input voltage
range.
Internal ADC Reference Mode With Common Mode Input V
V
/2 by connecting REFTS to V
REF
and AVSS.
and REFBS to AVSS. The input signal at AIN will swing between V
REF
/2: The input common mode is set to
REF
REF
1.5 V
2 V
0 V
2 V
1 V
AV
AIN
REFTS
REFBS
DD
MODE
V
REF
REFSENSE
Figure 18. Common Mode Input V
AIN
REFTS
THS1031
SHAA/DPGA
A/D
REFTF
0.1 µF
REFBF
0.1 µF
10 µF
0.1 µF
ADC
REF
+
_
+–
1 V
/2 With 1-V Internal Reference
REF
THS1031
SHA
PGA
18
AV
DD
REFBS
MODE
V
REF
REFSENSE
+
_
Figure 19. Common Mode Input V
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ADC
REF
+–
1 V
/2 With 2-V Internal Reference
REF
REFTF
0.1 µF
REFBF
0.1 µF
10 µF
0.1 µF
2.7 V – 5.5 V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242A – NOVEMBER 1999 – REVISED JANUARY 2000
PRINCIPLES OF OPERATION
analog input mode(continued)
differential input
In this mode, the first differential input is applied to the AIN pin and the second differential input is applied to the
common point where REFTS and REFBS are tied together. The common mode of the input should be set to
AVDD/2 as shown in Figure 20. The maximum magnitude of the differential input signal should be equal to V
V
REF
THS1031
AIN
AVDD/2
REFTS
REFBS
SHA
PGA
A/D
THS1031
REF
.
DD
MODE
V
REF
V
is either internal or external
REF
ADC
REF
REFTF
0.1 µF
REFBF
0.1 µF
10 µF
0.1 µF
AV
Figure 20. Differential Input
digital input mode
The THS1031 contains 4 registers: two CLAMP registers, a CONTROL register, and a TEST register . The TEST
register is reserved for test purposes. Binary data can be written into the CLAMP and CONTROL registers via
I/O0–I/O9 by inserting an active-low write strobe to the WR input pin and an active-low signal to the OE input
pin. This will disable the ADC’s output bus. The two MSBs of each register are address bits. For example, set
bit 9 and bit 8 to 00 to select the clamp register 1. Set bit 9 and bit 8 to 01 to select the clamp register 2.
clamp registers
The internal digital clamp circuit uses a 10-bit DAC to convert the 10-bit digital value into the analog clamp level
in which the clamp register 1 contains 8 LSBs of DAC(7:0). The clamp register 2 contains two MSBs of the
DAC(9:8). DAC(9:8)
into 4 quarters which can be selected by bit 0 (DAC8) and bit 1 (DAC9) in the clamp register 2. The user can
clamp to any of 256-dc levels within each quarter determined by the 8-bit content of the clamp register 1.
Figure 21 shows how the DACs 10-bit digital input map to the analog clamping range from 0 V to V
D
Clamp Register 1
9876543210
00DAC7DAC6DAC5DAC4DAC3DAC2DAC1DAC0
(Default = 00):
For clamping purpose, the entire range of voltage reference V
set bit 5 to1 to set the output data format to 2s complement.
D
INT/EXT Clamp: (
or set bit 4 to 1 to select the internal digital clamp whose clamp level is defined in the clamp register
described above.
D
Power Down: (
: (Default = 0)
Set bit 6 to 1 to disable the internal clamp amplifier for power savings.
(Default is straight binary
Default = 0)
Default = 0)
Set bit 4 of the CONTROL register to 0 to select the external analog clamp
Set bit 3 of the CONTROL register to 1 to power down the THS1031.
) Set bit 5 to 0 to set the output data format to straight binary or
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
digital input mode (continued)
D
PGA(2–0): (
table:
test register (reserved)
9876543210
11XXXXXXXX
Default = 001)
THS1031
2.7 V – 5.5 V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242A – NOVEMBER 1999 – REVISED JANUARY 2000
PRINCIPLES OF OPERATION
3-bit gain for programmable gain amplifier can be set as indicated in the following
PGA[2–0]GAIN
0000.5
001Unity gain
0101.5
0112.0
1002.5
1013.0
1103.5
1114.0
digital output mode
D
3-State Output: The digital outputs can be set to high-impedance state by applying a Hi logic to the OE
pin.
D
Output Format: Defined by bit 5 of the CONTROL register. The output format is straight binary if bit 5 set
to 0. The output format is 2s complement if bit 5 is set to 1.
The default format is straight binary
clamp operation
The THS1031 ADC features an internal clamp circuit for dc restoration of video or ac coupled signals. The clamp
input level can come from either an external source or an internal digital clamp circuit containing a 10-bit DAC
and clamp register.
D
External Clamp Input: To enable the external clamp input source, use the default state on power up or
write a 0 to bit 4 of the PGA/CONTROL register. This will connect the switch SW2 to the CLAMPIN pin. The
clamp amplifier will then servo the voltage at the AIN pin to be equal to the clamp voltage applied at the
CLAMPIN pin. After the desired clamp level is attained, the switch SW1 is opened by taking CLAMP back
to logic low. Ignoring the droop caused by the input bias current, the input capacitor CIN will hold the DC
voltage at AIN constant until the next clamp interval. The input resistor RIN has a minimum recommended
value of 10 W, to maintain the closed-loop stability of the clamp amplifier.
D
Internal Programmable Digital Clamp Input: The THS1031 ADC features a programmable digital clamp
circuit to set more precise clamping level to 1-LSB accuracy for dc restoration of video or ac coupled signals.
Figure 22 shows the internal clamp circuitry and the external control signals needed for the digital clamp
operation. To enable the digital clamp input source, write a 1 to bit 4 of the CONTROL register which will
connect the switch SW2 to the output of the 10-bit clamp DAC. In the CLAMP register, bit 0 to bit 7 are used
to set the clamp level input to the 10-bit DAC and bit 6–7 are used to select one of 4 equal clamping voltage
sub-ranges as described in the description of CLAMP REGISTER for digital input mode. The clamp
amplifier will then servo the voltage at the AIN pin to be equal to the clamp voltage applied at the CLAMPIN
pin. After the desired clamp level is attained, the switch SW1 is opened by taking CLAMP back to logic low.
Ignoring the droop caused by the input bias current, the input capacitor CIN will hold the dc voltage at AIN
constant until the next clamp interval. The input resistor RIN has a minimum recommended value of 10 W,
to maintain the closed-loop stability of the clamp amplifier.
Clamp Acquisition Time: Figure 22 shows the basic operation of the clamp circuit in which the ac input
signal is passed through an RC coupler.
The acquisition time when the switch is closed will equal a: T(acq) = Ci.Ri ln(Vc/Ve)(Eq.1)
In case of composite video, typical input Ri = 20 Ω. In a video clamping application, the droop is a critical
parameter and thus the input capacitor should be sized to allow sufficient acquisition time of clamp voltage at
AIN within the CLAMP interval, but also to minimize droop between clamping intervals. Typically, Ci = 1µF
By applying equation 1 above, the following examples apply to an NTSC composite video signal:
D
The acquisition time needed to clamp 1-V input level to black level (0.340 Vdc ) is about 130 µs.
D
The acquisition time needed to clamp 2-V input level to the white level (1 Vdc) is about 140 µs.
D
The acquisition time needed to clamp 3-V input level to the sync level (0.288 Vdc) is about 160 µs.
droop
The voltage droop is the voltage change across the input capacitor C
dV
+ǒI
ń
CiǓ(t)
bias
by the bias current as follows:
i
where t = elapsed time between clamping intervals
The bias current depends on the sampling rate. For a sampling rate of 30 MSPS and a typical input capacitance
of 1 pF, the input resistance is
Rs = 1/(Cs.Fs) = 1/(1 pFx30 MHz) = 33 kΩ
For 1-V input range and clamping period = 64 µs, the max bias current will equal I
= 0.5 V/33 kΩ = 15 µA:
bias
dV = (15 µA/1 µF)(64 µs) = 0.96 mV
For 1-V input range and clamping period = 64 µs, the max bias current will equal I
= 0.5 V/33 kΩ = 15 µA:
bias
dV = (15 µA/1 µF)(64 µs) = 0.96 mV
For 2-V input range and clamping period = 64 µs, the max bias current will equal I
= 1.0 V/33 kΩ = 30 µA
bias
dV = (30 µA/1 µF)(64 µs) = 1.9 mV
22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2.7 V – 5.5 V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242A – NOVEMBER 1999 – REVISED JANUARY 2000
PRINCIPLES OF OPERATION
clamp operation (continued)
requirements
For a single direct source of NTSC video,
D
The initial clamp acquisition time needs to be between 130 µs and 160 µs to set the input dc level within
1 mV accuracy.
D
The clamp pulse at CLAMP is recommended to be 2 µs (typ).
D
The droop voltage needs to be compensated within one clamping period of 64 µs for 1 V and 2 V. Input
ranges are 1 mV and 1.9 mV respectively which are less than 1 LSB.
power management
Upon power up, the THS1031 is put in the default mode. In the default mode, the PGA (PGA bypass) and the
clamp DAC are powered down which adds to the device’s flexibility. The users need not incur the penalty of
having to provide power for a certain section if it is not necessary to their design.
When bit 3 of PGA/control register is set to 1, the entire device is powered down. The ADC will wake-up in 400 ns
(typ) after the bit 3 is reset.
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
7,70
9,80
9,60
4040064/F 01/97
24
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS1031
2.7 V – 5.5 V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER
SLAS242A – NOVEMBER 1999 – REVISED JANUARY 2000
MECHANICAL DATA
DW (R-PDSO-G**) PLASTIC SMALL-OUTLINE
16 PINS SHOWN
0.050 (1,27)
16
1
0.020 (0,51)
0.014 (0,35)
9
0.299 (7,59)
0.293 (7,45)
8
A
0.010 (0,25)
0.419 (10,65)
0.400 (10,15)
M
0.010 (0,25) NOM
0°–8°
Gage Plane
0.010 (0,25)
0.050 (1,27)
0.016 (0,40)
0.104 (2,65) MAX
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-013
0.012 (0,30)
0.004 (0,10)
DIM
A MAX
A MIN
PINS **
16
0.410
(10,41)
0.400
(10,16)
Seating Plane
0.004 (0,10)
20
0.510
(12,95)
0.500
(12,70)
24
0.610
(15,49)
0.600
(15,24)
28
0.710
(18,03)
0.700
(17,78)
4040000/C 07/96
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
25
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 2000, Texas Instruments Incorporated
Loading...
+ hidden pages
You need points to download manuals.
1 point = 1 manual.
You can buy points or you can get point for every manual you upload.