Texas Instruments THS1030IPWR, THS1030IDWR, THS1030IPW, THS1030IDW, THS1030EVM Datasheet

THS1030

2.7 V – 5.5 V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS243A – NOVEMBER 1999 – REVISED JANUARY 2000

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

10-Bit Resolution 30 MSPS
Analog-to-Digital Converter:

D

Configurable Input: Single-Ended or
Differential

D

Differential Nonlinearity: ±0.3 LSB

D

Signal-to-Noise: 57 dB

D

Spurious Free Dynamic Range: 60 dB

D

Adjustable Internal Voltage Reference

D

Out-of-Range Indicator

D

Power-Down Mode

D

Pin Compatible with TLC876

description

The THS1030 is a CMOS, low power, 10-bit, 30
MSPS analog-to-digital converter (ADC) that can
operate with a supply range from 2.7 V to 3.3 V.
The THS1030 has been designed to give circuit
developers more flexibility . The analog input to the
THS1030 can be either single-ended or differential. The THS1030 provides a wide selection of voltage
references to match the user’s design requirements. For more design flexibility, the internal reference can be
bypassed to use an external reference to suit the dc accuracy and temperature drift requirements of the
application. The out-of-range output is used to monitor any out-of-range condition in THS1030s input range.

The speed, resolution, and single-supply operation of the THS1030 are suited for applications in STB, video,
multimedia, imaging, high-speed acquisition, and communications. The speed and resolution ideally suit
charge-couple device (CCD) input systems such as color scanners, digital copiers, digital cameras, and
camcorders. A wide input voltage range between REFBS and REFTS allows the THS1030 to be applied in both
imaging and communications systems.

The THS1030I is characterized for operation from –40°C to 85°C

AVAILABLE OPTIONS

PACKAGED DEVICES

T

A

28-TSSOP (PW) 28-SOIC (DW)

0°C to 70°C THS1030CPW THS1030CDW

–40°C to 85°C THS1030IPW THS1030IDW

Copyright  2000, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

TI is a trademark of Texas Instruments Incorporated.

1
2
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4
5
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8
9
10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17
16
15

AGND

DV

DD

I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9

OVR

DGND

AV

DD

AIN
V

REF

REFBS
REFBF
MODE
REFTF
REFTS
876M
AGND
REFSENSE
STBY
OE
CLK

28-PIN TSSOP/SOIC PACKAGE

(TOP VIEW)

THS1030

2.7 V – 5.5 V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS243A – NOVEMBER 1999 – REVISED JANUARY 2000

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional block diagram

SHA

Output

Buffers

Timing
Circuit

A/D

SW3

DC

REF

VBG

REFSENSE VREF CLK

REFBF

REFTF

MODE

REFBS

REFTS

AIN

I/O0 –
I/O9

OVR

OE

SW4

STBY

THS1030

2.7 V – 5.5 V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS243A – NOVEMBER 1999 – REVISED JANUARY 2000

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions

TERMINAL

NAME NO.

I/O

DESCRIPTION

AGND 1, 19 I Analog ground
AIN 27 I Analog input
AV

DD

28 I Analog supply
CLK 15 I Clock input
DGND 14 I Digital ground
DV

DD

2 I Digital driver supply

I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9

3
4
5
6
7
8

9
10
11
12

I/O

Digital I/O bit 0 (LSB)
Digital I/O bit 1
Digital I/O bit 2
Digital I/O bit 3
Digital I/O bit 4
Digital I/O bit 5
Digital I/O bit 6
Digital I/O bit 7
Digital I/O bit 8

Digital I/O bit 9 (MSB)
MODE 23 I Mode input
OE 16 I HI to the 3-state data bus, LO to enable the data bus
OVR 13 O Out-of-range indicator
REFBS 25 I Reference bottom sense
REFBF 24 I Reference bottom decoupling
REFSENSE 18 I Reference sense
REFTF 22 I Reference top decoupling
REFTS 21 I Reference top sense
STBY 17 I HI = power down mode, LO = normal operation mode
V

REF

26 I/O Internal and external reference for ADC

876M 20 I HI = THS1030 mode, LO = TLC876 mode (see section 4 for TLC876 mode)

THS1030

2.7 V – 5.5 V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS243A – NOVEMBER 1999 – REVISED JANUARY 2000

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

†

Supply voltage: AVDD to AGND, DVDD to DGND –0.3 to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

AGND to DGND –0.3 to 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

AV

DD

to DVDD –6.5 to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Mode input MODE to AGND –0.3 to AVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reference voltage input range REFTF, REFTB, REFTS, REFBS to AGND –0.3 to AVDD + 0.3 V. . . . . . . . .

Analog input voltage range AIN to AGND –0.3 to AVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reference input V

REF

to AGND –0.3 to AVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reference output V

REF

to AGND –0.3 to AVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Clock input CLK to AGND –0.3 to AVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Digital input to DGND –0.3 to DVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Digital output to DGND –0.3 to DVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating junction temperature range, T

J

0°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

STG

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 in) from case for 10 seconds 300°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

digital inputs

MIN NOM MAX UNIT

High-level input voltage, V

IH

2.4 V

Low-level input voltage, V

IL

0.2 x DV

DD

V

analog inputs

MIN NOM MAX UNIT

Analog input voltage, V

I(AIN)

REFBS REFTS V

Reference input voltage, V

I(VREF)

1 2 V

Reference input voltage, V

I(REFTS)

1 AV

DD

V

Reference input voltage, V

I(REFBS)

0 AVDD–1 V

power supply

MIN NOM MAX UNIT

pp

p

AV

DD

2.7 3 5.5

Suppl

y v

oltage

Maximum sampling rate

= 30

MSPS

DV

DD

2.7 3 5.5

V

REFTS, REFBS reference voltages (MODE = AVDD)

PARAMETER MIN NOM MAX UNIT

REFTS Reference input voltage (top) 1 AV

DD

V

REFBS Reference input voltage (bottom) 0 AVDD–1 V

Differential input (REFTS – REFBS) 1 2 V
Switched input capacitance on REFTS 0.5 pF

sampling rate and resolution

PARAMETER MIN NOM MAX UNIT

Fs 5 30 MSPS
Resolution 10 Bits

THS1030

2.7 V – 5.5 V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS243A – NOVEMBER 1999 – REVISED JANUARY 2000

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating conditions, A VDD = 3 V , DVDD = 3 V , Fs = 30
MSPS/50% duty cycle, MODE = AV

DD

, 2 V input span from 0.5 V to 2.5 V, external reference, TA =

–40°C to 85°C (unless otherwise noted)

analog inputs

PARAMETER MIN TYP MAX UNIT

V

I(AIN)

Analog input voltage REFBS REFTS V

C

I

Switched input capacitance 1.2 pF

FPBW Full power BW (–3 dB) 150 MHz

DC leakage current (input = ±FS) 60 µA

VREF reference voltages

PARAMETER MIN TYP MAX UNIT

Internal 1 V reference (REFSENSE = V

REF

) 0.95 1 1.05 V
Internal 2 V reference (REFSENSE = AVSS) 1.90 2 2.10 V
External reference (REFSENSE = AVDD) 1 2 V
Reference input resistance 18 kΩ

REFTF, REFBF reference voltages

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Differential input (REFTF – REFBF) 1 2 V

p

AVDD = 3 V 1.3 1.5 1.7

Input common mode (REFTF

+

REFBF)/2

AVDD = 5 V 2 2.5 3

V

AVDD = 3 V 2

V

REF

=

1 V

AVDD = 5 V 3

V

REFTF (MODE

=

AVDD)

AVDD = 3 V 2.5

V

REF

= 2

V

AVDD = 5 V 3.5

V

AVDD = 3 V 1

V

REF

= 1

V

AVDD = 5 V 0.5

V

REFBF (MODE

=

AVDD)

AVDD = 3 V 2

V

REF

=

2 V

AVDD = 5 V 1.5

V

Input resistance between REFTF and REFBF 600 Ω

dc accuracy

PARAMETER MIN TYP MAX UNIT

INL Integral nonlinearity ±1 ±2 LSB
DNL Differential nonlinearity ±0.3 ±1 LSB

Offset error 0.4 1.4 %FSR
Gain error 1.4 3.5 %FSR
Missing code No missing code assured

THS1030

2.7 V – 5.5 V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS243A – NOVEMBER 1999 – REVISED JANUARY 2000

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating conditions, A VDD = 3 V , DVDD = 3 V , Fs = 30
MSPS/50% duty cycle, MODE = AV

DD

, 2 V input span from 0.5 V to 2.5 V, external reference, TA =

–40°C to 85°C (unless otherwise noted) (continued)

dynamic performance

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

f = 3.5 MHz 8.4 9
f = 3.5 MHz, AVDD = 5 V 9

ENOB

Effective number of bits

f = 15 MHz, 3 V 7.8

Bits

f = 15 MHz, AVDD = 5 V 7.7
f = 3.5 MHz 56 60.6

p

f = 3.5 MHz, AVDD = 5 V 64.6

dB

SFDR

Spurious free dynamic range

f = 15 MHz 48.5
f = 15 MHz, AVDD = 5 V 53
f = 3.5 MHz –60 –56
f = 3.5 MHz, AVDD = 5 V –66.9

dB

THD

Total harmonic distortion

f = 15 MHz –47.5
f = 15 MHz, AVDD = 5 V –53.1
f = 3.5 MHz 53 57
f = 3.5 MHz, AVDD = 5 V 56

dB

SNR

Signal-to-noise

f = 15 MHz 53.1
f = 15 MHz, AVDD = 5 V 49.4
f = 3.5 MHz 52.5 56
f = 3.5 MHz, AVDD = 5 V 56

SINAD

Signal-to-noise and distortion

f = 15 MHz 48.6

dB

f = 15 MHz, AVDD = 5 V 48.1

clock

PARAMETER MIN TYP MAX UNIT

t

(CK)

Clock period 33 ns

t

(CKH)

Pulse duration, clock high 15 16.5 ns

t

(CKL)

Pulse duration, clock low 15 16.5 ns

t

d

Clock to data valid 20 ns
Pipeline latency 3 Cycles

t

(ap)

Aperture delay 4 ns
Aperture uncertainty (jitter) 2 ps

power supply

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

I

CC

Operating supply current AVDD =DVDD = 3 V, MODE = AGND 29 40 mA

p

AVDD = DVDD = 3 V 87 120

PDPower dissipation

AVDD = DVDD = 5 V 150

mW

PD(STBY) Standby power AVDD =DVDD = 3 V, MODE = AGND 3 5 mW

THS1030

2.7 V – 5.5 V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS243A – NOVEMBER 1999 – REVISED JANUARY 2000

7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

(See

Note A)

NOTE A: All timing measurements are based on 50% of edge transition.

Analog Input

Input Clock

Digital Output

Sample 1

Sample 2

Sample 3

Sample 4

Sample 5

t

(CK)

t

(CKH)

t

(CKL)

t

d

Pipeline Latency

Sample 1 Sample 2

Figure 1. Digital Output Timing Diagram