TEXAS INSTRUMENTS THS1030 Technical data

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THS1030

2.7 V – 5.5 V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS243A – NOVEMBER 1999 – REVISED JANUARY 2000

D

10-Bit Resolution 30 MSPS
Analog-to-Digital Converter:

D

Configurable Input: Single-Ended or
Differential

D

Differential Nonlinearity: ±0.3 LSB

D

Signal-to-Noise: 57 dB

D

Spurious Free Dynamic Range: 60 dB

D

Adjustable Internal Voltage Reference

D

Out-of-Range Indicator

D

Power-Down Mode

D

Pin Compatible with TLC876

description

The THS1030 is a CMOS, low power, 10-bit, 30
MSPS analog-to-digital converter (ADC) that can

28-PIN TSSOP/SOIC PACKAGE

AGND

DV

DGND

DD

I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9

OVR

(TOP VIEW)

1

28

2

27

3

26

4

25

5

24

6

23

7

22

8

21

9

20

10

19

11

18

12

17

13

16

14

15

AV

DD

AIN
V

REF

REFBS
REFBF
MODE
REFTF
REFTS
876M
AGND
REFSENSE
STBY
OE
CLK

operate with a supply range from 2.7 V to 3.3 V.
The THS1030 has been designed to give circuit
developers more flexibility . The analog input to the
THS1030 can be either single-ended or differential. The THS1030 provides a wide selection of voltage
references to match the user’s design requirements. For more design flexibility, the internal reference can be
bypassed to use an external reference to suit the dc accuracy and temperature drift requirements of the
application. The out-of-range output is used to monitor any out-of-range condition in THS1030s input range.

The speed, resolution, and single-supply operation of the THS1030 are suited for applications in STB, video,
multimedia, imaging, high-speed acquisition, and communications. The speed and resolution ideally suit
charge-couple device (CCD) input systems such as color scanners, digital copiers, digital cameras, and
camcorders. A wide input voltage range between REFBS and REFTS allows the THS1030 to be applied in both
imaging and communications systems.

The THS1030I is characterized for operation from –40°C to 85°C

AVAILABLE OPTIONS

A

0°C to 70°C THS1030CPW THS1030CDW

–40°C to 85°C THS1030IPW THS1030IDW

28-TSSOP (PW) 28-SOIC (DW)

PACKAGED DEVICES

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

TI is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  2000, Texas Instruments Incorporated

1

THS1030

2.7 V – 5.5 V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS243A – NOVEMBER 1999 – REVISED JANUARY 2000

functional block diagram

AIN

REFTS

REFBS

MODE

REFTF
REFBF

SHA

DC

REF

SW3

VBG

SW4

REFSENSE VREF CLK

A/D

STBY

Output

Buffers

Timing
Circuit

I/O0 –
I/O9

OVR

OE

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

I/O

DESCRIPTION

2.7 V – 5.5 V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS243A – NOVEMBER 1999 – REVISED JANUARY 2000

Terminal Functions

TERMINAL

NAME NO.

AGND 1, 19 I Analog ground
AIN 27 I Analog input
AV

DD

CLK 15 I Clock input
DGND 14 I Digital ground
DV

DD

I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9

MODE 23 I Mode input
OE 16 I HI to the 3-state data bus, LO to enable the data bus
OVR 13 O Out-of-range indicator
REFBS 25 I Reference bottom sense
REFBF 24 I Reference bottom decoupling
REFSENSE 18 I Reference sense
REFTF 22 I Reference top decoupling
REFTS 21 I Reference top sense
STBY 17 I HI = power down mode, LO = normal operation mode
V

REF

876M 20 I HI = THS1030 mode, LO = TLC876 mode (see section 4 for TLC876 mode)

28 I Analog supply

2 I Digital driver supply
3

4
5
6
7
8

9
10
11
12

26 I/O Internal and external reference for ADC

Digital I/O bit 0 (LSB)
Digital I/O bit 1
Digital I/O bit 2
Digital I/O bit 3
Digital I/O bit 4

I/O

Digital I/O bit 5
Digital I/O bit 6
Digital I/O bit 7
Digital I/O bit 8
Digital I/O bit 9 (MSB)

THS1030

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3

THS1030

Suppl

oltage

Maximum sampling rate

MSPS

V

2.7 V – 5.5 V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS243A – NOVEMBER 1999 – REVISED JANUARY 2000

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

†

Supply voltage: AVDD to AGND, DVDD to DGND –0.3 to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

AGND to DGND –0.3 to 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

AV

to DVDD –6.5 to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DD

Mode input MODE to AGND –0.3 to AVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reference voltage input range REFTF, REFTB, REFTS, REFBS to AGND –0.3 to AVDD + 0.3 V. . . . . . . . .

Analog input voltage range AIN to AGND –0.3 to AVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reference input V
Reference output V

to AGND –0.3 to AVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

REF

to AGND –0.3 to AVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

REF

Clock input CLK to AGND –0.3 to AVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Digital input to DGND –0.3 to DVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Digital output to DGND –0.3 to DVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating junction temperature range, T
Storage temperature range, T

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

STG

0°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

J

Lead temperature 1,6 mm (1/16 in) from case for 10 seconds 300°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

digital inputs

MIN NOM MAX UNIT

High-level input voltage, V
Low-level input voltage, V

IH

IL

analog inputs

Analog input voltage, V
Reference input voltage, V
Reference input voltage, V
Reference input voltage, V

I(AIN)

I(VREF)
I(REFTS)
I(REFBS)

power supply

AV

pp

y v

p

= 30

DV

DD

DD

REFTS, REFBS reference voltages (MODE = AVDD)

PARAMETER MIN NOM MAX UNIT

REFTS Reference input voltage (top) 1 AV
REFBS Reference input voltage (bottom) 0 AVDD–1 V

Differential input (REFTS – REFBS) 1 2 V
Switched input capacitance on REFTS 0.5 pF

2.4 V

0.2 x DV

MIN NOM MAX UNIT

REFBS REFTS V

1 2 V
1 AV
0 AVDD–1 V

MIN NOM MAX UNIT

2.7 3 5.5

2.7 3 5.5

DD

DD

DD

V

V

V

sampling rate and resolution

Fs 5 30 MSPS
Resolution 10 Bits

4

PARAMETER MIN NOM MAX UNIT

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Input common mode (REFTF

REFBF)/2

V

V

1 V

V

REFTF (MODE

AVDD)

V

V

V

V

V

V

REFBF (MODE

AVDD)

V

2 V

V

THS1030

2.7 V – 5.5 V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS243A – NOVEMBER 1999 – REVISED JANUARY 2000

electrical characteristics over recommended operating conditions, A VDD = 3 V , DVDD = 3 V , Fs = 30
MSPS/50% duty cycle, MODE = AV
–40°C to 85°C (unless otherwise noted)

analog inputs

PARAMETER MIN TYP MAX UNIT

V

I(AIN)

C

I

FPBW Full power BW (–3 dB) 150 MHz

VREF reference voltages

REFTF, REFBF reference voltages

Differential input (REFTF – REFBF) 1 2 V

p

Input resistance between REFTF and REFBF 600 Ω

Analog input voltage REFBS REFTS V
Switched input capacitance 1.2 pF

DC leakage current (input = ±FS) 60 µA

PARAMETER MIN TYP MAX UNIT

Internal 1 V reference (REFSENSE = V
Internal 2 V reference (REFSENSE = AVSS) 1.90 2 2.10 V
External reference (REFSENSE = AVDD) 1 2 V
Reference input resistance 18 kΩ

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

+

=

=

, 2 V input span from 0.5 V to 2.5 V, external reference, TA =

DD

) 0.95 1 1.05 V

REF

AVDD = 3 V 1.3 1.5 1.7
AVDD = 5 V 2 2.5 3

REF

REF

REF

REF

=

= 2

= 1

=

AVDD = 3 V 2
AVDD = 5 V 3
AVDD = 3 V 2.5
AVDD = 5 V 3.5
AVDD = 3 V 1
AVDD = 5 V 0.5
AVDD = 3 V 2
AVDD = 5 V 1.5

dc accuracy

INL Integral nonlinearity ±1 ±2 LSB
DNL Differential nonlinearity ±0.3 ±1 LSB

PARAMETER MIN TYP MAX UNIT

Offset error 0.4 1.4 %FSR
Gain error 1.4 3.5 %FSR
Missing code No missing code assured

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5

THS1030

ENOB

Effective number of bits

Bits

SFDR

Spurious free dynamic range

THD

Total harmonic distortion

dB

SNR

Signal-to-noise

SINAD

Signal-to-noise and distortion

dB

PDPower dissipation

mW

2.7 V – 5.5 V, 10-BIT, 30 MSPS
CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS243A – NOVEMBER 1999 – REVISED JANUARY 2000

electrical characteristics over recommended operating conditions, A VDD = 3 V , DVDD = 3 V , Fs = 30
MSPS/50% duty cycle, MODE = AV
–40°C to 85°C (unless otherwise noted) (continued)

dynamic performance

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

p

, 2 V input span from 0.5 V to 2.5 V, external reference, TA =

DD

f = 3.5 MHz 8.4 9
f = 3.5 MHz, AVDD = 5 V 9
f = 15 MHz, 3 V 7.8
f = 15 MHz, AVDD = 5 V 7.7
f = 3.5 MHz 56 60.6
f = 3.5 MHz, AVDD = 5 V 64.6
f = 15 MHz 48.5
f = 15 MHz, AVDD = 5 V 53
f = 3.5 MHz –60 –56
f = 3.5 MHz, AVDD = 5 V –66.9
f = 15 MHz –47.5
f = 15 MHz, AVDD = 5 V –53.1
f = 3.5 MHz 53 57
f = 3.5 MHz, AVDD = 5 V 56
f = 15 MHz 53.1
f = 15 MHz, AVDD = 5 V 49.4
f = 3.5 MHz 52.5 56
f = 3.5 MHz, AVDD = 5 V 56
f = 15 MHz 48.6
f = 15 MHz, AVDD = 5 V 48.1

dB

dB

clock

PARAMETER MIN TYP MAX UNIT

t

(CK)

t

(CKH)

t

(CKL)

t

d

t

(ap)

Clock period 33 ns
Pulse duration, clock high 15 16.5 ns
Pulse duration, clock low 15 16.5 ns
Clock to data valid 20 ns
Pipeline latency 3 Cycles
Aperture delay 4 ns
Aperture uncertainty (jitter) 2 ps

power supply

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

I

CC

PD(STBY) Standby power AVDD =DVDD = 3 V, MODE = AGND 3 5 mW

Operating supply current AVDD =DVDD = 3 V, MODE = AGND 29 40 mA

p

AVDD = DVDD = 3 V 87 120
AVDD = DVDD = 5 V 150

6

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THS1030

2.7 V – 5.5 V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS243A – NOVEMBER 1999 – REVISED JANUARY 2000

PARAMETER MEASUREMENT INFORMATION

Sample 2

Sample 1

Analog Input

t

(CK)

t

t

(CKH)

Input Clock

Digital Output

NOTE A: All timing measurements are based on 50% of edge transition.

(See

Note A)

(CKL)

Pipeline Latency

Sample 3

Figure 1. Digital Output Timing Diagram

Sample 4

Sample 5

t

d

Sample 1 Sample 2

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7