Texas Instruments TCA5013 User Manual

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SDA SCL

SHDN

INT

IOMC1

CLKIN1

IOMC2

CLKIN2

VDD

VUP

VDDI

PRES

VCCUC

GNDUC

IOUC CLKUC RSTUC

VCCS1

IOS1 CLKS1

RSTS1

VCCS3

IOS3

VCCS2

IOS2

CLKS2

RSTS2

CLKS3 RSTS3

GNDS

TCA5013

GNDS

GPIO1

GPIO2

GPIO3

GPIO4

TST3

TST2

TST1

DDI

User Card

Slot

SAM1

Card

Slot

SAM2

Card

Slot

GNDP

Microcontroller

10k

10k 10k

10k

100 nF

VUP

10 µF

10k

VDD

10 µH

VDD

= 100

µF

200nF

LDOCAP

1 µF

TST4

GND

SAM3

Card

Slot

200nF

VDD=V

DDI

= 3.3 V

VUP

Product Folder

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Technical Documents

Tools & Software

Support & Community

TCA5013

SCPS253C –JANUARY 2014–REVISED SEPTEMBER 2019

TCA5013 Feature Rich Smartcard Interface IC with 1 User Card and 3 SAM Card Support

1 Features

• Operating supply voltage range of 2.7 V to 5.5 V

• Supports EMV 4.3, ISO7816-3 and ISO7816-10 standards

• Supports 1 user card and 3 secure access module cards

• IEC61000-4-2 8-kV Contact discharge esd protection on all smartcard interface pins

• Low power mode for power saving when inactive (shutdown mode)

• Automatic card deactivation in the event of short circuit, card pull out, over temperature or power supply fault

• Integrated DC-DC boost to generate VCCfor 5 V and 3 V on all card interfaces

• Automatic card clock generation for synchronous card activation

• 4-byte FIFO for storing ATR from ISO7816-10 Type 1 cards

• Programmable rise/fall time control for IO and clock lines of all smartcards

• Input clock frequency up to 26 MHz

• Tamper proof package design

2 Applications

• High-end point of sale (POS) terminals

• Multi secure accesscard capable EPOS systems

3 Description

TCA5013 is a smartcard interface IC that is targeted for use in Point of Sale (POS) terminals. The device enables POS terminals to interface with EMV4.3, ISO7816-3 and ISO7816-10 compliant cards. It supports up to 3 Secure Access Module (SAM) cards in addition to 1 user card. It operates from a single supply and generates all the card voltages. The device is controlled by a standard I2C interface and is capable of card activation and deactivation per EMV4.3 and ISO7816-3 standards. In addition it also supports ISO7816-10 synchronous cards. It has a 4byte FIFO that stores the ATR (Answer to Reset) sequence in ISO7816-10 type 1 cards. Synchronous cards (ISO7816-10 type 1 and type 2) can be set up for automatic activation or manual activation. The device has multiple power saving modes and also supports power saving in the smartcard itself by “clock stop” or lowering clock frequency to lowest allowable levels per the ISO7816 - 3 standard. TCA5013 has IEC 61000-4-2 8kV contact discharge on all pins that interface with smartcards. This enables the system to be resistant to ESD in the field without the need for external ESD devices. It is available in an 5 mm x 5 mm BGA package. The pin out of the device is such that all the IO pins are securely surrounded by other pins. This prevents the secure pins from being probed during device operation.

Device Information

PART NUMBER PACKAGE BODY SIZE (NOM)

TCA5013 NFBGA (48) 5.00 mm × 5.00 mm (1) For all available packages, see the orderable addendum at

the end of the data sheet.

(1)

Simplified Schematic

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

TCA5013

SCPS253C –JANUARY 2014–REVISED SEPTEMBER 2019

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1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description ............................................................. 1

4 Revision History..................................................... 2

5 Pin Configuration and Functions......................... 3

6 Specifications......................................................... 5

6.1 Absolute Maximum Ratings ...................................... 5

6.2 Handling Ratings....................................................... 5

6.3 Recommended Operating Conditions....................... 5

6.4 Thermal Information.................................................. 5

6.5 Electrical Characteristics—Power Supply and ESD . 6

6.6 Electrical Characteristics—Card VCC........................ 6

6.7 Electrical Characteristics—Card RST....................... 6

6.8 Electrical Characteristics—Card CLK ....................... 7

6.9 Electrical Characteristics—Card Interface IO, C4 and

C8............................................................................... 7

6.10 Electrical Characteristics—PRES ........................... 8

6.11 Electrical Characteristics—IOMC1 and IOMC2 ...... 9

6.12 Electrical Characteristics—CLKIN1 and CLKIN2.... 9

6.13 Electrical Characteristics—A0 and SHDN .............. 9

6.14 Electrical Characteristics—INT ............................... 9

6.15 Electrical Characteristics—GPIO............................ 9

6.16 Electrical Characteristics—SDA and SCL............. 10

6.17 Electrical Characteristics—Fault Condition

Detection.................................................................. 10

6.18 I2C Interface Timing Requirements....................... 10

6.19 I2C Interface Timing Characteristics ..................... 10

6.20 Synchronous Type 1 Card Activation Timing

Characteristics ......................................................... 11

6.21 Synchronous Type 2 Card Activation Timing

Characteristics ......................................................... 11

6.22 Card Deactivation Timing Characteristics............. 11

6.23 Typical Characteristics.......................................... 11

7 Parameter Measurement Information ................ 12

8 Detailed Description ............................................ 13

8.1 Overview ................................................................. 13

8.2 Functional Block Diagram....................................... 14

8.3 Feature Description................................................. 15

8.4 Device Functional Modes........................................ 17

8.5 Programming........................................................... 38

8.6 Register Maps......................................................... 41

9 Application and Implementation ........................ 55

9.1 Application Information............................................ 55

9.2 Typical Application ................................................. 55

10 Power Supply Recommendations..................... 57

10.1 Power-On-Reset ................................................... 57

11 Layout................................................................... 57

11.1 Layout Guidelines ................................................. 57

11.2 Layout Example .................................................... 58

12 Device and Documentation Support ................. 59

12.1 Trademarks........................................................... 59

12.2 Electrostatic Discharge Caution............................ 59

12.3 Glossary................................................................ 59

13 Mechanical, Packaging, and Orderable

Information........................................................... 59

4 Revision History

Changes from Revision B (January 2016) to Revision C Page

• Changed the Pin Configuration view ..................................................................................................................................... 3

• Added: (Cold reset sequence) to Figure 6 ........................................................................................................................... 22

Changes from Revision A (July 2014) to Revision B Page

• Changed the datasheet title to "TCA5013 Feature Rich Smartcard Interface IC with 1 User Card and 3 SAM Card

Support".................................................................................................................................................................................. 1

• Added the Features: Tamper proof package design.............................................................................................................. 1

• Changed the Applications ...................................................................................................................................................... 1

• Full Version release of document........................................................................................................................................... 1

Changes from Original (July 2014) to Revision A Page

• Full version release of document. ......................................................................................................................................... 1

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1 2 3 4 5 6 7 8 9

Not to scale

PRES GPIO4 GPIO3 GPIO2 GPIO1 VUP LX

C8 A0 INT SHDN SCL SDA LDOCAP TS T4 GNDP

C4 VDD

CLKUC TST3 GND CLKIN1

GNDUC IOUC IOMC1 GN D

RSTUC VCCUC IOMC2 CL KIN2

TST2 VDDI

RSTS3 IOS3 GNDS TS T1 IOS2 GNDS GNDS IOS1 VC CS1

CLKS3 VCCS3 RSTS2 CL KS2 VCCS2 RSTS1 CL KS1

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5 Pin Configuration and Functions

TCA5013

SCPS253C –JANUARY 2014 –REVISED SEPTEMBER 2019

ZAH Package

NFBGA 48-Pins

Bottom View

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TCA5013

SCPS253C –JANUARY 2014–REVISED SEPTEMBER 2019

Pin Functions

NO. NAME

A1 PRES INPUT User card presence detection A2 GPIO4 I/O General purpose IO (5-V tolerant) A4 GPIO3 I/O General purpose IO (5-V tolerant) A5 GPIO2 I/O General purpose IO (5-V tolerant) A6 GPIO1 I/O General purpose IO (5-V tolerant) A8 VUP PWR Boost output terminal A9 LX PWR Boost inductor input terminal B1 C8 I/O User card auxiliary IO (Open Drain) B2 A0 INPUT B3 INT OUTPUT Interrupt output (open drain) B4 SHDN INPUT Shutdown and reset pin B5 SCL INPUT

B6 SDA I/O B7 LDOCAP PWR Internal LDO output. Connect to 1 µf decoupling capacitor. B8 TST4 NA Test pin. Grounded in application. B9 GNDP PWR Power ground C2 C4 I/O User card auxiliary IO (Open drain) C8 VDD PWR Device main power supply D1 CLKUC OUTPUT User card clock D2 TST3 NA Test pin. Grounded in application. D8 GND PWR Device ground D9 CLKIN1 INPUT User card external clock input pin E1 GNDUC PWR User card ground pin E2 IOUC I/O User card IO pin E8 IOMC1 I/O User card microcontroller data IO E9 GND PWR Device ground F1 RSTUC OUTPUT User card reset output pin F2 VCCUC PWR User card VCC pin F8 IOMC2 I/O SAM microcontroller data IO F9 CLKIN2 INPUT User card external clock input pin G2 TST2 NA Test pin. Grounded in application. G8 VDDI PWR Microcontroller interface supply voltage. H1 RSTS3 OUTPUT Reset output for SAM3 H2 IOS3 I/O IO pin for SAM3 H3 GNDS PWR Ground for all SAMs H4 TST1 NA Test pin. Grounded in application H5 IOS2 I/O IO pin for SAM2 H6 GNDS PWR Ground for all SAMs H7 GNDS PWR Ground for all SAMs H8 IOS1 I/O IO pin for SAM1 H9 VCCS1 PWR VCC for SAM1 J1 CLKS3 OUTPUT Clock output for SAM3 J2 VCCS3 PWR VCC for SAM3 J4 RSTS2 OUTPUT Reset output for SAM2 J5 CLKS2 OUTPUT Clock output for SAM2 J6 VCCS2 PWR VCC for SAM2 J8 RSTS1 OUTPUT Reset output for SAM1 J9 CLKS1 OUTPUT Clock output for SAM1

TYPE DESCRIPTION

I2C address selection pin. Connect to VDDI, GND.

I2C clock input I2C data

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6 Specifications

TCA5013

SCPS253C –JANUARY 2014 –REVISED SEPTEMBER 2019

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

(1)(2)

(3)

MIN MAX UNIT

DDI

Supply voltage range –0.3 6 V Interface voltage range –0.3 4 V

Input voltage range on digital I/O pins referenced to V

DDI

-0.3

DDI

0.3

VCC+

0.3

Load current on GPIO pins -15 mA Load current on INT and SDA pins -6 mA

(1) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. (2) The package thermal impedance is calculated in accordance with JESD 51-7. (3) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 Handling Ratings

MIN MAX UNIT

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

Storage temperature range –65 150 °C

stg

Electrostatic discharge

(ESD)

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all

(1)

pins Charged device model (CDM), per JEDEC specification

JESD22-C101, all pins

(2)

–4 4

-1.5 1.5

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN MAX UNIT

DDI

CC(TOT)

Supply voltage range – DC-DC enabled 2.7 5.5 V Supply voltage Range – DC-DC disabled 5.25 5.5 V Interface voltage range 1.65 3.6 V Sum of the currents that can be drawn on all Card VCC pins 180 mA Operating temperature range –40 85 °C

6.4 Thermal Information

TCA5013

THERMAL METRIC

θJA

θJC(top)

θJB

Junction-to-ambient thermal resistance 96.9 Junction-to-case (top) thermal resistance 59.0 Junction-to-board thermal resistance 49.4 Junction-to-top characterization parameter 1.9 Junction-to-board characterization parameter 58.6

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(1)

UNITZAH

48 PINS

°C/W

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TCA5013

SCPS253C –JANUARY 2014–REVISED SEPTEMBER 2019

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6.5 Electrical Characteristics—Power Supply and ESD

VDD= V

DDTH

DDSH

DDITH

DDSH

DDST

DDA

DDA1

DDISH

DDIA

WAKE

OSC

DC-DC

ESD-IEC

(1) Values highly dependent on external components like boost inductor and external rectifier. The specification is based on 75% boost

= 3.3 V; L

DDI

= 10 µH; C

VDD

= 10 µF; C

VDD

= 10 µF; TA= –40°C to 85°C unless otherwise noted

VUP

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VDD supervisor fault threshold VDDvoltage below which SUPL fault is asserted 2.45 2.7 V VDD shutdown threshold VDDvoltage below which device will shutdown 2.0 V VDDI shutdown threshold V VDD Shutdown current Shutdown Mode at T VDD Standby current Shutdown Mode at T

Supply current

(1)

voltage below which device will shutdown 1.4 1.6 V

DDI

= 25 C 22 28 µA

ambient

= 25°C 300 650 µA

ambient

IOMC1 = IOMC2 = V CLKIN1 = CLKIN2 = GND; T Current consumption per card interface activated

= V

CCUC

ambient

= f

= I

= 25°C

CCS1

CLKIN2

CCS1

= 55 mA; I

CLKIN1

CCUC

= V

= f

DDI

CCS2

CLKUC

;

= V

= f

CCS2

ambient

CCS3 CLKS1

= I

= 25°C

= 5 V;

= 5 MHz;

= 2 mA;

CCS3

235 280 mA

VDD Interface shutdown current Shutdown Mode at 25°C 3.5 5 µA VDD Interface supply current

All Card VCC= 5 V; CLKIN1 = CLKIN2 = 5 MHz; @ 25°C; IOMC1 = IOMC2 = V

DDI

290 300 µA

Time from

Device wakeup time

SHDN > VIHto INT < V

0.1 10 ms

Internal Oscillator Frequency Measured on CLKUC, CLKS1,CLKS2,CLKS3 1 1.2 1.4 MHz DC-DC switching frequency 2.4 MHz

DC-DC output voltage

IEC61000-4-2 level 4 ESD protection on pins defined in Table 1

If any card VCCis 5 V 5.5 If all card VCCis 3 V or 1.8 V 3.5

-8 8 kV

efficiency for max value and 85% efficiency for typical value

2 mA

6.6 Electrical Characteristics—Card V

VDD= V

= 3.3 V; L

DDI

= 10 µH; C

VDD

= 10 µF; C

VDD

VUP

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

∆VCC/∆I

RIPPLE

Card supply voltage

Load transient response

Current pulses I < 100 mA, t < 400 ns

Peak to peak ripple voltage Measured on VCC= 5 V, 3 V, 1.8 V 90 mV

Card supply Current

Card LDO dropout voltage ICC= 65 mA 250 mV

6.7 Electrical Characteristics—Card RST

VDD= V

OL - RST

OH - RST

R - RST

F - RST

= 3.3 V; L

DDI

= 10 µH; C

VDD

= 10 µF; C

VDD

VUP

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Output Low voltage IOL= -200 µA 0.1 V Output high voltage IOH= 150 µA 0.9 V Rise time CL= 30 pF ; 10% to 90% 0.1 µs Fall time CL= 30 pF ; 90% to 10% 0.1 µs

= 10 µF; TA= –40°C to 85°C unless otherwise noted

VCC= 5 V; ICC≤ 65 mA 4.75 5 5.25

VCC= 1.8 V; ICC≤ 45 mA 1.71 1.8 1.89 VCC= 5 V ; 40 nA.s current spike 4.65 5.35 V VCC= 3 V ; 17.5 nA.s current spike 2.76 3.24 V VCC= 1.8 V ; 11.1 nA.s current spike 1.62 1.98 V

VCC= 5 V 65

VCC= 1.8 V 45

= 10 µF; TA= –40°C to 85°C unless otherwise noted

VVCC= 3 V; ICC≤ 65 mA 2.85 3 3.15

mAVCC= 3 V 65

V V

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SCPS253C –JANUARY 2014 –REVISED SEPTEMBER 2019

6.8 Electrical Characteristics—Card CLK

VDD= V

OL - CLK

OH - CLK

R - CLK

CLK f

CLK

D Clock duty cycle Internal clock = 1.2 MHz; CL= 30 pF 45 55 %

DDI

/ t

F - CLK

PU-PD-SKEW

= 3.3 V; L

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

= 10 µH; C

VDD

Output Low voltage IOL= -100 µA 0.1 V Output high voltage IOH= 100 µA 0.9 V

Rise/Fall time

Clock pull-up / pull-down skew t Frequency on CLK pin CL= 30 pF 20 MHz

= 10 µF; C

VDD

VUP

CL= 30 pF ; 10% to 90%;

– t

R-CLK

F-CLK

= 10 µF; TA= –40°C to 85°C unless otherwise noted

CLK slew rate settings register = 0000b

CLK slew rate settings register = 0001b

CLK slew rate settings register = 0010b

CLK slew rate settings register = 0011b

CLK slew rate settings register = 0100b

CLK slew rate settings register = 0101b

CLK slew rate settings register = 0110b

CLK slew rate settings register = 0111b

CLK slew rate settings register = 1000b

CLK slew rate settings register = 1001b

CLK slew rate settings register = 1010b

CLK slew rate settings register = 1011b

CLK slew rate settings register = 1100b

CLK slew rate settings register = 1101b

CLK slew rate settings register = 1110b

CLK slew rate settings register = 1111b

/ t

; CL= 30 pF 10 %

F-CLK

13.5

V V

6.9 Electrical Characteristics—Card Interface IO, C4 and C8

VDD= V

OL - C4, C8

OH - C4, C8

IL - IO, C4, C8

IH - IO, C4, C8

OL - IO, 5 V

= 3.3 V; L

DDI

= 10 µH; C

VDD

= 10 µF; C

VDD

= 10 µF; TA= –40°C to 85°C unless otherwise noted

VUP

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Output Low Voltage VCC= 5 V IOL= -1 mA 0.5 V Output Low Voltage VCC= 5 V, 3 V, 1.8 V IOH= 20 µA 0.9 V Output Low Voltage 0.4 V Output High Voltage 0.6 V

VCC= 5 V; IO fall time register setting = 00b

VCC= 5 V;

Output Low Voltage

IO fall time register setting = 01b VCC= 5 V;

IO fall time register setting = 10b VCC= 5 V;

IO fall time register setting = 11b

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IOL= -1 mA

V V V

0.5

0.5 V

0.5

TCA5013

SCPS253C –JANUARY 2014–REVISED SEPTEMBER 2019

Electrical Characteristics—Card Interface IO, C4 and C8 (continued)

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VDD= V

DDI

OL - IO, 3 V

OL - IO, 3 V, 500uA

OL - IO, 1.8 V

OL - IO, 1.8 V, 500uA

PD - R - IOMC - IO

PD - F - IOMC - IO

FO - IO

RO - IO

RO - C4, C8

FO - C4, C8

RI - IO, C4, C8

FI - IO, C4, C8

I - IO, C4, C8

PU - IO, C4, C8

= 3.3 V; L

= 10 µH; C

VDD

= 10 µF; C

VDD

= 10 µF; TA= –40°C to 85°C unless otherwise noted

VUP

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Output Low Voltage

Rising edge propagation delay

Falling edge propagation delay

IO Line output fall time

IO Line output rise time C4, C8 Line output rise

time C4, C8 Line output fall

time IO, C4, C8 Input rise

time IO, C4, C8 Input fall

time

VCC= 3 V; IO fall time register setting = 01b

VCC= 3 V; IO fall time register setting = 10b

IOL= -1 mA

VCC= 3 V; IO fall time register setting = 11b

VCC= 3 V; IO fall time register setting = 00b

VCC= 3 V; IO fall time register setting = 01b

VCC= 3 V;

IOL= -500 µA

IO fall time register setting = 10b VCC= 3 V;

IO fall time register setting = 11b VCC= 1.8 V;

IO fall time register setting = 11b

IOL= -1 mA 0.18 V

VCC= 1.8 V; IO fall time register setting = 01b

VCC= 1.8 V; IO fall time register setting = 10b

IOL= -500 µA

VCC= 1.8 V; IO fall time register setting = 11b

From IOMC pin to card IO; CLon card IO = 30 pF; CLon IOMC = 30 pF; Prop delay measured from

70% V

to 70% of VCCfor rising edge

DDI

From IOMC pin to card IO; CLon card IO = 30 pF; CLon IOMC = 30 pF; Prop delay measured from

30% V CL= 30 pF ; 10% to 90%; IO fall time register setting

= 00b CL= 30 pF ; 10% to 90%; IO rise time register

setting = 100b

to 30% of VCCfor falling edge;

DDI

68 ns

100 ns

CL= 30 pF ; 10% to 90% 1.2 µs

CL= 30 pF ; 90% to 10% 1.2 µs

10% to 90% 1.2 µs

90% to 10% 1.2 µs

0.3

0.18

400 ns

250 ns

Input capacitance F = 1 MHz 10 pF Pull-up resistance IO, C4, C8 pull-up to V

4.25 8.1 kΩ

6.10 Electrical Characteristics—PRES

VDD= V

IL - PRES

IH - PRES

LEAK - PRES

DEB(P)

DEB(D)

= 3.3 V; L

DDI

PARAMETER TEST CONDITION MIN TYP MAX UNIT

= 10 µH; C

VDD

Input Low voltage 0.3 V Input high voltage 0.7 V Input leakage current Voltage on pin = V

Debounce time

= 10 µF; C

VDD

Time from transition on PRES pin to PRESL bit being set

Time from transition on PRES pin to start of deactivation sequence (RST going low)

= 10 µF; TA= –40°C to 85°C unless otherwise noted

VUP

DDI

20 ms

100 µs

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DDI

1 µA

V V

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6.11 Electrical Characteristics—IOMC1 and IOMC2

VDD= V

OL- IOMC

OH - IOMC

IL - IOMC

IH - IOMC

PD - F - IO - IOMC

RO - IOMC

FO - IOMC

RI - IOMC

FI - IOMC

I - IOMC

PU - IOMC

= 3.3 V; L

DDI

= 10 µH; C

VDD

= 10 µF; C

VDD

= 10 µF; TA= –40°C to 85°C unless otherwise noted

VUP

PARAMETER TEST CONDITION MIN TYP MAX UNIT

Output low voltage IOL= -100 µA 0.2 V Output high voltage IOH= 20 µA 0.8 V Input low signal 0.3 V Input high signal 0.7 V

Falling edge propagation delay

Rising edge propagation delay

From Card IO pin to IOMC; CLon card IO = 30 pF; Prop delay measured from 30% VCCto 30% of V

falling edge; From Card IO pin to IOMC; CLon card IO = 30 pF;

Prop delay measured from 70% VCCto 70% of V

rising edge; Output rise time CL= 30 pF ; 10% to 90% 1.2 µs Output fall time CL= 30 pF ; 90% to 10% 1.2 µs Input rise time 10% to 90% 1.2 µs Input fall time 90% to 10% 1.2 µs Input capacitance 10 pF Pull-up resistance Pull-up to V

DDI

6.12 Electrical Characteristics—CLKIN1 and CLKIN2

VDD= V

IL - CLKIN

IH - CLKIN

R - CLKIN

F - CLKIN

CLKIN

= 3.3 V; L

DDI

= 10 µH; C

VDD

= 10 µF; C

VDD

= 10 µF; TA= –40°C to 85°C unless otherwise noted

VUP

PARAMETER TEST CONDITION MIN TYP MAX UNIT

Input Low voltage 0.2 V Input high voltage 0.8 V Rise time 10% to 90% 0.1 µs Fall time 90% to 10% 0.1 µs Input clock frequency 26 MHz

TCA5013

SCPS253C –JANUARY 2014 –REVISED SEPTEMBER 2019

V V V V

V V

DDI

for

DDI

250 ns

400 ns

11 kΩ

DDI

6.13 Electrical Characteristics—A0 and SHDN

VDD= V

IL - A0, SHDN

IH - A0, SHDN

LEAK - A0, SHDN

I - A0, SHDN

PU - SHDN

= 3.3 V; L

DDI

= 10 µH; C

VDD

= 10 µF; C

VDD

= 10 µF; TA= –40°C to 85°C unless otherwise noted

VUP

PARAMETER TEST CONDITION MIN TYP MAX UNIT

input Low voltage 0.2 V input high voltage 0.8 V Input leakage current Voltage on pin = V Input Capacitance 10 pF Pull-up resistance on SHDN Pull-up to V

6.14 Electrical Characteristics—INT

VDD= V

LEAK - INT

OL - INT

= 3.3 V; L

DDI

= 10 µH; C

VDD

= 10 µF; C

VDD

= 10 µF; TA= –40°C to 85°C unless otherwise noted

VUP

PARAMETER TEST CONDITION MIN TYP MAX UNIT

Input leakage current Voltage on pin = V Output low voltage IOL= -3 mA 0.2 V

6.15 Electrical Characteristics—GPIO

VDD= V

OL - GPIO

LEAK - GPIO

PD - GPIO

= 3.3 V; L

DDI

= 10 µH; C

VDD

= 10 µF; C

VDD

= 10 µF; TA= –40°C to 85°C unless otherwise noted

VUP

PARAMETER TEST CONDITION MIN TYP MAX UNIT

Output low voltage IOL= -10 mA 0.2 V Output low current 10 mA Input leakage current Voltage on pin = V

State transition on GPIO to INT assertion

RPUon INT= 10 k; CLon INT 20 pF; GPIO and INT transition referenced to 0.5 V

DDI

V V

1 µA

2.5 MΩ

1 µA

DDI

1 µA 4 µs

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SCPS253C –JANUARY 2014–REVISED SEPTEMBER 2019

6.16 Electrical Characteristics—SDA and SCL

VDD= V

LEAK - SDA, SCL

OL - SDA, SCL

IL - SDA, SCL

IH - SDA, SCL

= 3.3 V; L

DDI

= 10 µH; C

VDD

PARAMETER TEST CONDITION MIN TYP MAX UNIT

Input leakage current Voltage on pin = V SDA output low voltage IOL= -3 mA 0.1 V SDA max output low current VOL= 0.3 V 10 mA Input low signal 0.2 V Input high signal 0.8 V

= 10 µF; C

VDD

= 10 µF; TA= –40°C to 85°C unless otherwise noted

VUP

DDI

6.17 Electrical Characteristics—Fault Condition Detection

VDD= V

LIM

= 3.3 V; L

DDI

Shutdown temperature 125 145 °C Shutdown current On card VCC pins 160 200 260 mA

Output current limit

= 10 µH; C

VDD

PARAMETER TEST CONDITION MIN TYP MAX UNIT

= 10 µF; C

VDD

= 10 µF; TA= –40°C to 85°C unless otherwise noted

VUP

On card IO pins –15 15 mA On card CLK pins –70 70 mA On card RST pins –20 20 mA

DDI

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1 µA

DDI

V V

6.18 I2C Interface Timing Requirements

(1)

STANDARD MODE

PARAMETER

I2C BUS

MIN MAX MIN MAX MIN MAX

f t t t t t t t t t t t t

scl sch scl sp sds sdh icr icf ocf buf sts sth sps

I2C clock frequency 100 400 1000 kHz I2C clock high time 4 0.6 0.26 μs I2C clock low time 4.7 1.3 0.5 μs I2C spike time 50 50 50 ns I2C serial data setup time 250 100 50 ns I2C serial data hold time 0 0 0 ns I2C input rise time 1000 300 120 ns I2C input fall time 300 300 120 ns I2C output fall time; 10 pF to 400 pF bus 300 300 120 μs I2C bus free time between Stop and Start 4.7 1.3 0.5 μs I2C Start or repeater start condition setup time 4.7 0.6 0.26 μs I2C Start or repeater start condition hold time 4 0.6 0.26 μs I2C Stop condition setup time 4 0.6 0.26 μs

(1) Refer to the Parameter Measurement Information section for more information.

6.19 I2C Interface Timing Characteristics

(1)

PARAMETER MIN TYP MAX UNIT

vd(data)

vd(ack)

Valid data time; SCL low to SDA output valid 450 ns Valid data time of ACK condition; ACK signal from SCL low to SDA (out) low 450 ns

(1) Refer to Parameter Measurement Information section for more information.

FAST MODE

I2C BUS

FAST MODE PLUS

(FM+) I2C BUS

UNIT

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0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

CLK Rise / Fall Time (ns)

Clock Slew Rate Settings Register Value (ns)

CLK Rise Time

CLK Fall Time

C001

TCA5013

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6.20 Synchronous Type 1 Card Activation Timing Characteristics

PARAMETER TEST CONDITION MIN TYP MAX UNIT

S1-RST-HI

S1-CLK-HI

S1-RST-CLK

S1-CLK-RST

S1-CLK-LO

S1-CLK-PER

S1-ATR-SETUP

CL= 30 pF ; VCC= 5 V; See Figure 4. 60 70 80 µs CL= 30 pF ; VCC= 5 V; See Figure 4. 10 12.5 15 µs CL= 30 pF ; VCC= 5 V; See Figure 4. 25 28 32 µs CL= 30 pF ; VCC= 5 V; See Figure 4. 25 28 32 µs CL= 30 pF ; VCC= 5 V; See Figure 4. 70 80 90 µs CL= 30 pF ; VCC= 5 V; See Figure 4. 22.5 25 27.5 µs CL= 30 pF ; VCC= 5 V; See Figure 4. 1 µs

Duty cycle CL= 30 pF ; VCC= 5 V; See Figure 4. 45 50 55 %

6.21 Synchronous Type 2 Card Activation Timing Characteristics

PARAMETER TEST CONDITION MIN TYP MAX UNIT

S2-VCC-CLK

S2-CLK-C4

S2-CLK-HI

CL= 30 pF ; VCC= 5 V; See Figure 5. 5 20 µs CL= 30 pF ; VCC= 5 V; See Figure 5. 14 18 22 µs CL= 30 pF ; VCC= 5 V; See Figure 5. 7 9 11 µs

6.22 Card Deactivation Timing Characteristics

PARAMETER TEST CONDITION MIN TYP MAX UNIT

DEAC-TOTS

DEAC-RST-CLK

DEAC-RST-IO

DEAC-RST-VCC

CL= 30 pF ; VCC= 5 V; See Figure 7. 0.5 0.6 ms CL= 30 pF ; VCC= 5 V; See Figure 7. 10 12 15 µs CL= 30 pF ; VCC= 5 V; See Figure 7. 22 24 26 µs CL= 30 pF ; VCC= 5 V; See Figure 7. 45 µs

6.23 Typical Characteristics

Figure 1. CLK Rise/Fall Time vs Clock Slew Rate Settings Register Value

CL= 30 pF

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70 %

30 %

SDA

70 %

30 %

70 %

30 %

70 % 30 %

SCL

HD;DAT

1 / f

1 clock cycle

SCL

70 %

30 %

70 %

30 %

cont.

VD;DAT

cont.

SDA

SCL

SU;STA

HD;STA

SU;STO

BUF

P S

HIGH

9 clock

HD;STA

LOW

70 %

30 %

VD;ACK

9 clock

SU;DAT

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7 Parameter Measurement Information

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VIL= 0.3 V

VIH= 0.7 V

DDI DDI

Figure 2. Parameter Measurement Information for I2C Timing Characteristics and Requirements

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8 Detailed Description

8.1 Overview

TCA5013 is a smartcard interface IC that enables POS terminals to interface with EMV4.3 and ISO7816-3 and ISO7816-10 compliant smartcards. The device has 4 smartcard interfaces (1 user card and 3 SAM cards). TCA5013 is capable of card activation and deactivation per EMV4.3, ISO7816-3 and ISO7816-10 standards.

TCA5013 has two power supply pins - VDD and VDDI. VDD is the main power supply for the device and VDDI is the reference supply for the interface operating voltage. VDDand V recommended operating conditions for the device to operate properly. Upon power up an internal Power-OnReset circuit initializes the digital core with all the registers in their default state as described in Register Maps.

TCA5013 can operate in various functional modes as defined in Device Functional Modes. When one of the device power supplies is not applied, that is, VDD< V

DDSH

or V

DDI

< V

DDITH

of the device functions are available in this mode. Shutdown Mode is the lowest power operating mode in the device. Shutdown mode is entered by asserting the SHDN = 0 when VDD> V can detect card insertion and removal even in Shutdown mode. The device is in Standby mode when VDD> V

DDSH

or V

DDI

> V

and the SHDN pin = 1. When any of the 4 smartcard interfaces is activated, the device

DDITH

enters active mode (see Active Mode). The user card interface module can be activated in synchronous type 1, synchronous type 2, asynchronous or manual operation mode. For synchronous type 1 and synchronous type 2 operation modes, the device can automatically generate activation sequences per the ISO7816-10 standard (see

Synchronous Type 1 Operating Mode and Synchronous Type 2 Operating Mode). For asynchronous cards the

device performs the activation sequence and also verifies the response from the card meets the requirements per ISO7816-3 and EMV4.3 standards (see Asynchronous Operating Mode). The device also supports WARM reset ( see Warm Reset Sequence) and card deactivation (see Deactivation Sequence) of smartcards per the ISO7816-3 and EMV4.3 standards. The SAM card interface modules can only be activated in aynchronous operation mode.

All smartcard interfaces have the standard CLK, IO and RST pins (as defined by EMV4.3 and ISO7816 standards). All these pins are designed to have internal current limiting to prevent device damage when shorted. CLK and IO pins also provide automatic level translation to the voltage at which the card has been activated. Rrise time and fall time of the CLK and IO pins can also be controlled using digital register settings (see IO Rise

Time and Fall Time control and CLK Rise Time and Fall Time Control). In addition to the CLK, IO and RST pins

the user card interface also has PRES pin to detect card insertion and removal (see User Card Insertion /

Removal Detection). C4 and C8 pins, as defined by ISO7816-10, are also present on the user card interface (see User Card Interface Module).

The device has internal boost and LDOs to generate the card activation voltage depending on the operating voltage required by the specific card being interfaced with. It also has a voltage supervisor that monitors VDDand V

and responds as described in Interrupt Operation . The power management section is described in more

DDI

detail in Power Management. In addition to these functions the device provides 8kV IEC 61000-4-2 ESD protection on all pins that interface to

smartcards. This removes the need for any external ESD protection on the board, thereby providing system robustness without compromising system security (removable components on secure lines).

TCA5013 is configured using a standard I2C interface that is capable of up to 1 MHz operation. The I2C interface is also used to read the status of various fault conditions that the device can detect. The I2C operation is described in detail in I2C Interface Operation.

need to ramped to within the

DDI

the device is in Power Off Mode. None

DDSH

and V

DDI

> V

. The device

DDITH

Product Folder Links: TCA5013

User Card Interface

Module

Card VCCLDO

IO level translator

CLK level translator

RST level translator

C4&C8 buffers

PRES detection logic

SAM 1 Interface Module

Card VCCLDO

IO level translator

CLK level translator

RST level translator

SAM 3 Interface Module

Card VCCLDO

IO level translator

CLK level translator

RST level translator

SAM 2 Interface Module

Card VCCLDO

IO level translator

CLK level translator

RST level translator

Boost

LDO

Oscillator

User card

clock divider

SAM clock

divider and

multiplexer

SAM card

Digital core

and register map

I2C

interface

RSTUC

C4 C8

PRES

VCCUC

IOUC

CLKUC

VCCS1

IOS1

CLKS1

VCCS2

IOS2

CLKS2

VCCS3

IOS3

CLKS3

RSTS1

RSTS2

RSTS3

VUPLX

VDD

LDOCAP

IOMC1

IOMC2

CLKIN1

CLKIN2

SCL

SDA

INT

SHDN

GPIO1 GPIO2 GPIO3 GPIO4

VDDI

GNDUC

GNDS

GNDP

TST1 TST2 TST3 TST 4

User card IO

multiplexer

Voltage

supervisor

IO multiplexer

and multiplexer

TCA5013

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8.2 Functional Block Diagram

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8.3 Feature Description

8.3.1 Card Interface Modules

TCA5013 has 1 user card interface module and 3 SAM card interface modules. All card modules have level translators and an LDO to support interfacing with smartcards operating at different voltages.

8.3.2 SAM Card Interface Modules

All SAM card interface modules can operate per the EMV4.3 and ISO7816-3 standard and support asynchronous operating mode. All SAM card interface modules have the standard IO, CLK and RST pins. Detailed operation of these pins is described in section IO operation, CLK operation and RST operation.

8.3.3 User Card Interface Module

User card interface module can also operate per the EMV4.3 and ISO7816-3 standard and support asynchronous operating mode. In addition, the user card interface module also supports synchronous type 1 operating mode and synchronous type 2 operating mode, per ISO7816-10. Like the SAM card interface modules, the user card interface module also has IO, CLK, and RST pins. The user card interface module also has a PRES pin that is used for detection of user card insertion or removal.

C4 and C8 are two pins that are only present on the user card interface. These are open drain bi-directional IOs that are controlled by the bit [5] and bit [4] of user card synchronous mode settings register (Reg 0x09) when the card interface is activated. These bits act as both control and status bits for the C4 and C8 signals. If a ‘0’ is written to either of these bits the corresponding pin is driven low by the TCA5013. However, when a ‘1’ is written to the register bit, the corresponding pin is pulled up by an internal pull-up resistor. In this state an external device can drive the pin low. If the pin is driven low, then the corresponding bit in the register changes to reflect the status of the pin.

8.3.4 Clock Division and Multiplexing

TCA5013 card interface modules all have a CLK pin that provide a clock signal that is used for smartcard operation. This clock signal is generated based on an internal oscillator or from the CLKIN1/CLKIN2 input clock signals, by the clock divider and multiplexer circuitry. The user card has a dedicated clock divider and multiplexer. The user card CLK output can be a configured to be a function of the CLKIN1 frequency or the internal oscillator frequency. CLKIN2 is shared by all the SAM card interface modules. The CLK output of each SAM card can be independently configured based on the CLKIN2 frequency or the internal oscillator frequency. CLK operation section describes the clock division and multiplexing in detail.

8.3.5 IO Multiplexing

IOMC1 and IOMC2 are connected to the IO pins in the card interface modules through IO multiplexer blocks. The user card IO module has a dedicated IO multiplexer, that can be connect or disconnect IOUC from the IOMC1 pin. The IOMC2 is connected to the SAM card interface modules IO pins through the SAM IO multiplexer block. The IOMC2 can only be connected to one of the SAM interface modules at any given time. IO operation section describes IO multiplexing in detail.

8.3.6 GPIO Operation

The TCA5013 has four 5 V tolerant open drain GPIO pins that can be configured as inputs or outputs through device settings register (Reg 0x42). If configured as outputs, each is capable of sinking up to 10mA of current. If configured as inputs they will assert the INT line when a state change occurs on the pin. The minimum pulse width for transition detection is 10 µs, that is, when a state transition occurs on a GPIO configured as an input, it needs to hold its state for a minimum of 10 µs in order to guarantee detection by the TCA5013. This, however, does not imply any glitch rejection on the GPIO pins. The GPIOs are available in Standby Mode and Active

Mode. GPIO state transitions are not tracked in shutdown mode.

8.3.7 Power Management Features

TCA5013 has a DC-DC boost and card LDOs that enable it to generate regulated smart card VCCfrom its input power rails (VDDand V devices also have a voltage supervisor that monitors the VDDand V

). It also has an internal LDO that is used to power its internal circuits. The TCA5013

DDI

rails to ensure they are stable and usable

DDI

for smartcard operation.

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Feature Description (continued)

8.3.8 ESD Protection

All the smart card interface pins in the TCA5013 devices are designed with in built IEC61000-4-2 level 4 8kV contact ESD protection. Table 1 shows a list of pins with the 8kV ESD protection. The pins not listed below all have 4kV HBM ESD protection.

Table 1. List of Pins with 8kV IEC ESD Protection

PIN SYMBOL TYPE DESCRIPTION

A1 PRES INPUT User card presence detection B1 C8 IO User card auxiliary IO (Open Drain) C2 C4 IO User card auxiliary IO (Open Drain) D1 CLKUC OUTPUT User card clock E2 IOUC IO User card IO F1 RSTUC OUTPUT User card RST F2 VCCUC PWR User card VCC H1 VCCUC OUTPUT SAM3 RST H2 IOS3 IO SAM3 IO H5 IOS2 IO SAM2 IO H8 IOS1 IO SAM1 IO H9 VCCS1 PWR SAM1 VCC J1 CLKS3 OUTPUT SAM3 CLK J2 VCCS3 PWR SAM3 VCC J4 RSTS2 OUTPUT SAM2 RST J5 CLKS2 OUTPUT SAM2 CLK J6 VCCS2 PWR SAM2 VCC J8 RSTS1 OUTPUT SAM1 RST J9 CLKS1 OUTPUT SAM1 CLK

8.3.9 I2C interface

The device has a standard I2C interface that is used to configure the device and to read the status of the device. For detailed I2C operation refer to I2C Interface Operation.

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Power off mode

Shutdown mode

Standby mode

Active mode

Power on

Reset

VCC Check

Assert INT

Deactivate all

card slots

VDD > V

DDSH

DDI

> V

DDITH

SHDN = 0

SHDN = 1

State change

on PRES pin

VDD < V

DDSH

DDI

< V

DDITH

SHDN = 0

VDD > V

DDSH

DDI

> V

DDITH

SHDN = 1

VDD < V

DDSH

DDI

< V

DDITH

Card

activation

command

VCC fail

VCC

active

Over current card

removal or

deactivation

command

Other cards

still active

Deactivate all

card slots

VDD < V

DDTH

Or over

temperature

No other card slot

active

Deactivate all

card slots

SHDN = 0

Deactivate all

card slots

DDI

< V

DDITH

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8.4 Device Functional Modes

At any given time the TCA5013 can be in one of several different functional modes. Figure 3 diagram shows the different functional modes and describes how the device transitions from one mode to another. The blue bubbles represent actual functional modes and the white bubbles represent transitional states that are used to move from one functional mode to another.

Figure 3. Device Operating Modes

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Device Functional Modes (continued)

8.4.1 Power Off Mode

The TCA5013 is in power off mode when VDD< V features are functional and available for use.

8.4.2 Shutdown Mode

TCA5013 is in shutdown mode when all the below conditions are true.

• VDD> V

• V

DDI

> V

DDSH

DDITH

• SHDN = 0 Shutdown mode is a low power mode where all circuits except card insertion detection circuitry are shutdown.

Even I2C communication is disabled in shutdown mode. The only active circuit in the device is card insertion detection circuit on the PRES pin (see User Card Insertion / Removal Detection). Shutdown mode is entered from Active Mode or Standby Mode by asserting the SHDN pin. When entering shutdown mode from Active

Mode all active card interfaces are automatically deactivated.

8.4.3 Standby Mode

The TCA5013 is in standby mode when all the below conditions are true.

• VDD> V

• V

DDI

> V

DDSH

DDITH

• SHDN = 1

• No card interfaces are activated. In standby mode, the device I2C and card detection circuits are fully functional. All other circuits are ready to be

activated based on I2C commands received from the microcontroller. Standby mode is entered from shutdown mode by releasing the SHDN pin or from power down mode by powering up the device or from active mode by deactivating all card interfaces.

DDSH

or V

DDI

< V

. In power off mode none of the device

DDITH

8.4.4 Active Mode

The TCA5013 is in active mode when all the below conditions are true.

• VDD> V

• V

DDI

> V

DDSH

DDITH

• SHDN = 1

• At least one card interface is activated In active mode, the device is fully functional with at least one of the card interfaces activated. The DC-DC

Boost and card LDOs are active and provide power to the card VCC pins of the active card interfaces. Active mode can only be entered from standby mode by activating one of the card interfaces. When the device is in active mode, the individual card interfaces can be active in different operating modes. The user card supports

Asynchronous Operating Mode, Synchronous Type 1 Operating Mode,Synchronous Type 2 Operating Mode,

or Manual Operating Mode. The SAM card interfaces can only be activated in asynchronous activation mode.

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RSTUC

CLKUC

IOUC

Bit 1 to Bit 30 of

ATR response

INT

32 Clock cycles (4 Bytes)

S1-RST-HI

S1-CLK-HI

S1-RST-CLK

S1-CLK-RST

S1-CLK-LO

S1-CLK-PER

VCCUC

All High levels refer to 0 .9 Vcc

All Low levels refer to 0 .1 Vcc

t = t < 0 .5 μs

Bit 0

S1-ATR-SETUP

Bit 31

C 4

C 8

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Device Functional Modes (continued)

8.4.4.1 User Card Operating Mode Selection

The user card interface in the TCA5013 can be activated in different operating modes. When the START_ASYNC bit (bit [0]; Reg 0x01) is set the user card interface is activated in asynchronous operating mode. When START_SYNC bit (bit[0]; Reg 0x09) is set the user card interface is activated in synchronous type1, synchronous type 2 or manual operating mode. When the START_SYNC bit is set, the operating mode is determined by the ACTIVATION_TYPE bit (bit [6]; Reg 0x09) and CARD_TYPE bit (bit [7] Reg 0x09).

If ACTIVATION_TYPE bit (bit [6]; Reg 0x09) is set to ‘0’, the user card interface is activated in manual operating mode. If the ACTIVATION_TYPE bit is set to’1’, the user card interface is set for automatic activation, where it will be activated in synchronous type 1 or synchronous type 2 operating mode based on CARD_TYPE bit (bit [7] Reg 0x09). If CARD_TYPE bit is set to ‘1’, the card interface is activated in synchronous type 2 operating mode. If CARD_TYPE bit is set to ‘0’ the card interface is activated in synchronous type 1 operating mode.

Any changes made to the START_SYNC, START_ASYNC, CARD_TYPE or ACTIVATION_TYPE bits when the user card interface is active, will be ignored and will have no effect on the device. These new settings will take effect only on the next card interface activation following deactivation (see Deactivation Sequence).

8.4.4.2 Synchronous Type 1 Operating Mode

Synchronous type 1 operating mode is only supported on the user card interface. To enter synchronous operating mode, the user card interface goes through the synchronous type 1 activation sequence. Figure 4 shows the synchronous type 1 activation sequence.

CLKIN1 shall be low before the synchronous type 1 activation sequence is initiated. The following bit settings are required to initiate a synchronous type 1 activation sequence.

• ACTIVATION_TYPE (bit [6]; Reg 0x09) = 1

• CARD_TYPE (bit [7]; Reg 0x09) = 0

• START_SYNC (bit [0]; Reg 0x09) = 1

Figure 4. Synchronous Type 1 Activation Sequence

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Device Functional Modes (continued)

Once synchronous type 1 activation has been initiated, the following sequence of events occurs on the user card interface:

• VCCUC, RSTUC, CLKUC, C4, C8 and IOUC are all default low.

• VCCis applied to the VCCUC pin per the SET_VCC_UC bit (bit[7:6]; Reg 0x01).

• After VCCis stable RSTUC and CLKUC pulses are applied per t

S1-RST-HI

• After VCCis stable, the IOUC line is pulled up to VCC.

• After VCCis stable C4 and C8 reflect the value in their corresponding I2C register bits (bit[5] and bit[4]; Reg 0x09).

• RSTUC is held low while the CLKUC line starts oscillating with a frequency of ~40Khz (generated from internal oscillator).

• The IO line is sampled on the 32 rising or falling (based on bit[1]; Reg 0x09) edges of CLK and stored in the FIFO registers 0AH to 0DH.

• At the end of the 32nd CLK pulse, the CLKUC is held low and the CLKUC pin is controlled by the clock settings register (Reg 0x02).

• IOUC is connected to IOMC1 if IO_EN_UC bit (bit[5] Reg 0x01) is set to 1.

• INT_SYNC_COMPLETE bit (Bit[1]; REG 0x41) is set and the INT line is asserted low.

• IOMC1 shall stay pulled up to V

i.e. IOMC1 shall not be pulled low until INT is asserted.

DDI

• CLKIN1 shall toggle only after INT is asserted.

• RSTUC is controllable by I2C after INT is asserted.

and t

S1-CLK-HI

defined in Table 2.

Table 2. Synchronous Type 1 Card Activation Timing Characteristics

MIN TYP MAX UNIT

S1-RST-HI

S1-CLK-HI

S1-RST-CLK

S1-CLK-RST

S1-CLK-LO

S1-CLK-PER

Duty cycle 45 50 55 %

60 70 80 µs 10 12.5 15 µs 25 28 32 µs 25 28 32 µs 70 80 90 µs

22.5 25 27.5 µs

8.4.4.3 Synchronous Type 2 Operating Mode

Synchronous type 2 operating mode is only supported on the user card interface. To enter synchronous operating mode, the user card interface goes through the synchronous type 2 activation sequence. Figure 5 shows the synchronous type 2 activation sequence.

CLKIN1 shall be low before the synchronous type 2 activation sequence is initiated. The following bit settings are required to initiate a synchronous type 1 activation sequence.

• ACTIVATION_TYPE (bit [6]; Reg 0x09) = 1

• CARD_TYPE (bit [7]; Reg 0x09) = 1

• START_SYNC (bit [0]; Reg 0x09) = 1

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VCCUC

CLKUC

RSTUC

RST stays LOW through entire activation

C 4

S2-VCC-CLK

INT

S2-CLK-C4

All High levels refer to 0.9Vcc

All Low levels refer to 0.1 Vcc

t = t < 0.5μs

IOUC

S2-CLK-HI

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Figure 5. Synchronous Type 2 Activation Sequence

Once synchronous type 2 activation has been initiated, the following sequence of events occur on the user card interface:

• VCCUC, RSTUC, CLKUC, C4, C8 and IOUC are all default low.

• VCCis applied to the VCCUC pin per the SET_VCC_UC bit (bit[7:6]; Reg 0x01).

• A single pulse is applied to CLKUC per the t

S2-CLK-HI

timing defined in Table 3.

• The C4 line is held low through the VCCramp.

• The C4 line is released high per the t

S2-CLK-C4

timing defined in Table 3.

• After C4 is released CLKUC is controlled by clock settings register (Reg 0x02).

• After VCCis stable, the IOUC line is pulled up to VCC.

• After VCCis stable, C8 reflects value in bit [4] Reg 0x09.

• IOUC is connected to IOMC1 if IO_EN_UC bit (bit[5] Reg 0x01) is set to 1.

• INT_SYNC_COMPLETE bit (Bit[1]; REG 0x41) is set and the INT line is asserted low.

• IOMC1 shall stay pulled up to V

DDI

, that is, IOMC1 shall not be pulled low until INT is asserted.

• CLKIN1 shall toggle only after INT is asserted.

• RSTUC is controllable by I2C after INT is asserted.

Table 3. Synchronous Type 2 Card Activation Timing Characteristics

MIN TYP MAX UNIT

S2-VCC-CLK

S2-CLK-C4

S2-CLK-HI

5 20 µs

14 18 22 µs

7 9 11 µs

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VCC

RST

CLK

200 CLK

cycles

IO ignored

200 CLK cycles

IO ignored

42100CLK

Cycles

(EARLY+MUTE)

ATR Valid

Window

EARLY answer

check

ATR Reception

Window

EARLY answer

check

Warm reset sequence

42100CLK

Cycles

(EARLY+MUTE)

MUTE

answer

check

MUTE

answer

check

Card activation sequence (Cold reset sequence)

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8.4.4.4 Manual Operating Mode

Manual operating mode is only supported on the user card interface. Unlike the other operating modes, the manual operating mode does not have a defined activation sequence. CLKIN1 shall be low before the manual activation sequence is initiated. The following bit settings are required to initiate a synchronous type 1 activation sequence.

• ACTIVATION_TYPE (bit [6]; Reg 0x09) = 0

• START_SYNC (bit [0]; Reg 0x09) = 1

Once manual activation has been initiated the following sequence of events occur on the user card interface.

• VCCUC, RSTUC, CLKUC, C4, C8 and IOUC are all default low.

• VCCis applied to the VCCUC pin per the SET_VCC_UC bit (bit[7:6]; Reg 0x01)

• After VCCis stable, the IOUC line is pulled up to V

• After VCCis stable C4 and C8 reflect the value in their corresponding I2C register bits (bit[5] and bit[4]; Reg 0x09)

• IOUC is connected to IOMC1 if IO_EN_UC bit (bit[5] Reg 0x01) is set to 1.

• INT_SYNC_COMPLETE bit (Bit[1]; REG 0x41) is set and the INT line is asserted low.

• IOMC1 shall stay pulled up to V

i.e. IOMC1 shall not be pulled low until INT is asserted.

DDI

• CLKIN1 shall toggle only after INT is asserted.

• RSTUC is controllable by I2C after INT is asserted.

8.4.4.5 Asynchronous Operating Mode

Asynchronous operating mode is supported on all card interfaces. To enter asynchronous operating mode, the user card interface goes through the asynchronous activation sequence. Figure 6 shows the asynchronous activation sequence. CLKIN1 shall be toggling before the asynchronous activation sequence is initiated. The asynchronous activation sequence is initiated by setting the START_ASYNC bit (bit[0]) of the card interface settings register (Reg 0x01 for User card, Reg 0x11 for SAM1, Reg 0x21 for SAM1, Reg 0x31 for SAM3) to ‘1’.

Figure 6. Asynchronous Activation and Warm Reset Sequence

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Once asynchronous activation has been initiated, the following sequence of events takes place on the card interface:

• VCC, RST, CLK, C4, C8 and IO are all default low.

• VCCis applied to the VCC pin per the SET_VCC bits (bit [7:6] of card interface settings register).

• After VCCis stable, the IO line is pulled up to VCC.

• After VCCis stable C4 and C8 reflect the value in their corresponding I2C register bits (bit[5] and bit[4]; Reg 0x09).

• IO is connected to IOMC if IO_EN bit (bit[5] of card interface settings register) is set to 1.

• The CLK line starts to oscillate based on the card clock settings register. Any change on the IO line during the first 200 card clock cycles on the CLK pin is ignored.

• After the first 42100 CLK cycles, the RST line is driven high.

• If there is a high to low transition on the IO line before RST is high, the EARLY bit (bit[6]) and MUTE bit (bit[5]) of the card interface status register (Reg 0x00 for user card, Reg 0x10 for SAM1, Reg 0x20 for SAM2 and Reg 0x30 for SAM3) is set and the INT pin is asserted low.

• After RST is high, an internal counter starts counting CLK cycles. If there is a high to low transition on IO pin before the internal counter reaches the value defined by in the EARLY_COUNT_HI register (Reg 0x03 for user card, Reg 0x13 for SAM1, Reg 0x23 for SAM2, Reg 0x33 for SAM3) and EARLY_ COUNT_LO Register (Reg 0x04 for user card, Reg 0x14 for SAM1, Reg 0x24 for SAM2, Reg 0x34 for SAM3) then the EARLY bit in the card interface status register is set and INT is asserted.

• If the internal counter reaches the value defined by MUTE_COUNT_HI register (Reg 0x05 for user card, Reg 0x15 for SAM1, Reg 0x25 for SAM2, Reg 0x35 for SAM3) and MUTE_COUNT_LO (Reg 0x06 for user card, Reg 0x16 for SAM1, Reg 0x26 for SAM2, Reg 0x36 for SAM3) registers without a high to low transition on the IO line, then the MUTE bit in the card interface status registers is set and INT pin is asserted low.

If the first high to low transition on IO pin happens very close to the clock edges (within ~10 ns) that defines the ATR VALID window (see Figure 6), the TCA5013 response would be non-deterministic, that is, it may not be able to identify whether the transition happened before or after the edge. This implies that the MUTE bit may or may not be set if the IO transition happens very close to the clock edge defining the end of the ATR VALID window. Likewise, if the IO transition happens very close to the clock edge defining the beginning of the EARLY window, it may or may not set the EARLY bit.

8.4.4.6 Warm Reset Sequence

When a card interface is active in asynchronous mode, it is possible to initiate a warm reset sequence on the card interface. The warm reset sequence is initiated by setting the WARM bit (bit [3]) of the card interface settings register to ‘1’. Once warm reset is initiated the below sequence of events takes place on the card interface.

• VCCis already ramped and stable per the SET_VCC bits (bit[7:6] of card interface settings register).

• CLK continues to oscillate per the card clock settings register.

• RST pin is pulled low (high before warm reset was initiated).

• C4 and C8 continue to reflect the value in their corresponding I2C register bits (bit[5] and bit[4]; Reg 0x09).

• IO stays connected to IOMC if IO_EN bit (bit5 of card interface settings register) is set to 1.

• Any change on the IO line during the first 200 card clock cycles after RST goes low is ignored.

• After the first 42100 CLK cycles, the RST line is driven high.

• If there is a high tow low transition on the IO line before RST is high, the EARLY bit (bit6) and MUTE bit (bit5) of the card interface status register (Reg 0x00 for user card, Reg 0x10 for SAM1, Reg 0x20 for SAM2 and Reg 0x30 for SAM3) is set and the INT pin is asserted low.

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RST

CLK

VCC

two card clock cycles

< 0.4 V

PRES

100 μs

DEAC-TOT

DEAC-RST-CLK

DEAC-RST-IO

DEAC-RST-VCC

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8.4.4.7 Deactivation Sequence

After a card interface has been activated in a certain operating mode, it can be deactivated by I2C command or certain interrupt events (see Interrupt Operation). The deactivation sequence is the same regardless of what operating mode the card interface is in.

Figure 7 shows the deactivation sequence initiated by card extraction on the user card interface. It is to be noted

that the deactivation sequence starts 100 µs after the transition on PRES. This delay is intended to provide a debounce period that provides unintended deactivation due to any glitch on the PRES pin. As mentioned previously any of the card interfaces may be deactivated due to a supervisor fault, over current fault or over temperature fault. In these cases there is no debounce period and the deactivation sequence is initiated as soon as the internal fault signal is asserted.

Figure 8 shows the deactivation of any card interface initiated by I2C command. If the card interface is activated

in asynchronous mode, it can be deactivated by clearing (writing ‘0’) the START_ASYNC bit in the card interface settings register. To deactivate the user card interface when it is activated in synchronous mode, the START_SYNC bit should be cleared (write ‘0’).

Figure 7. Deactivation Sequence

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RST

CLK

VCC

+ two card clock cycles

< 0 .4 V

I2C

SCL

DEAC-TOT

DEAC-RST-CLK

DEAC-RST-IO

DEAC-RST-VCC

< 5μs

Rising edge of SCL

corresponding to ACK

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Figure 8. Card Deactivation Sequence Initiated by I2C Command

Table 4. Card Deactivation Timing Characteristics

MIN TYP MAX UNIT

DEAC-TOT

DEAC-RST-CLK

DEAC-RST-IO

DEAC-RST-VCC

0.4 0.5 0.6 ms 10 12 15 µs 22 24 26 µs 33 36 39 µs

8.4.5 User Card Insertion / Removal Detection

User card interface module in the TCA5013 has a PRES pin that is used to detect the presence of a card in that interface. In normal application the signal is connected to a switch that opens or closes when a card is inserted. Whenever a transition is seen on the PRES pin, the PRESL bit (Reg 0x00, bit 2) will be set and INT pin is asserted. Because this transition is associated with a mechanical switch, there is an internal debounce of ~20 ms before the PRESL bit is set and the INT is asserted. If the device sees a transition on the PRESL pin when the card interface is active, the device initiates a card deactivation sequence (see Deactivation Sequence). TCA5013 is capable of detecting card insertion even when it is in shutdown mode (see Shutdown Mode).

In addition to the PRESL_UC bit mentioned above, there is also a PRES_UC bit (Reg 0x00, bit 2), which indicates to the host whether or not a card is present in the user card slot. In order to accommodate different card cage topologies, the TCA5013 can be configured to detect card presence with a low to high or high to low, transition on the PRES pin. The CARD_DETECT_UC bit (Reg 0x01, bit 2) is used to configure the device for different card detection topologies. If CARD_DETECT_UC = 0 indicates to the TCA5013 that when a card is inserted in the slot, the PRES pin shall be low. CARD_DETECT_UC = 1 indicates to the host that when a card is

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PRES bit = 1

SHDN

PRES

INT

Card insertion /

extraction

Debounce period

20ms

Power on Reset

I2C

Interrupt

status

read

SHDN

released

by µC

(pull-up)

POR interrupt

CARD

DETECT =1

PRES bit = 0

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inserted in the slot the PRES pin shall be high. The status of the PRES_UC bit is based on the status of the PRES pin and the CARD_DETECT_UC bit. The truth table in Table 1 shows the PRES_UC bit status based on the CARD_DETECT_UC bit and the PRES pin. When coming out of power off mode (see Power Off Mode) or shutdown mode (see Shutdown Mode) the CARD_DETECT_UC = 0. If there is a state transition on the PRES pin when the device is in shutdown mode, the INT pin asserted (after the 20 ms debounce).

Table 5. Truth Table Defining Status of PRES Bit

CARD DETECT BIT PRES PIN PRES BIT

0 0 1 0 1 0 1 0 0 1 1 1

Figure 9 to Figure 14 show timing waveforms of device power up and coming out of shutdown with and without a

card inserted in the system. In below figures’ low to high PRES topology’ means that a high level on the PRES pin indicates a card is present. In below figures high to low PRES topology’ means that a low level on the PRES pin indicates a card is present. The below figures also show operation of INT pin and interrupt status register. For detailed description of the interrupt operation, refer to Interrupt Operation section.

Figure 9. Card detection in shutdown mode - Low to High PRES Topology

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I2C

PRES

INT

Power on Reset

VDD /

VDDI

POR interrupt

Interrupt

status

read

CARD

DETECT = 1

PRES bit = 0

PRESL

Interrupt

Debounce period

20 ms

Card

insertion

PRES bit = 1

SHDN

PRES

INT

Card insertion /

extraction

Debounce period

20 ms

Power on reset

SHDN

released

by µC

(

pull-up

)

POR

interrupt

I2C

Interrupt

status

read

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Figure 10. Card detection in shutdown mode - High to Low PRES Topology

Figure 11. Device power up without card inserted in system - Low to High PRES Topology

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PRES

INT

Power on reset

VDD /

VDDI

POR interrupt

PRESL

interrupt

Debounce period

20 ms

Debounce period

100 us

Card slot

deactivated

Card extracted

I2C

Interrupt

status

read

CARD

DETECT = 1

PRES bit =1

PRES bit =0

PRES bit = 0

I2C

PRES

INT

Power on reset

VDD / VDDI

POR interrupt

Interrupt

status

read

PRES bit =1

Debounce period

20 ms

Card

insertion

PRES Bit = 0

PRESL

interrupt

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Figure 12. Device power up without card inserted in system - High to Low PRES Topology

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Figure 13. Device Power Up With Card Inserted in System - Low to High PRES Topology

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I2C

PRES

INT

Power on reset

VDD /

VDDI

POR interrupt

Interrupt

status

read

PRESL

Interrupt

Debounce period

20ms

Debounce period

100 us

Card slot

deactivated

Card extracted

PRES bit =1

PRES bit =0

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Figure 14. Device Power up with Card Inserted In System - High to Low PRES Topology

8.4.6 IO Operation

All card interfaces in the TCA5013 have an IO pin that connects data, to and from the microcontroller, with the smartcard. The TCA5013 provides automatic level translation from IOMC pin operating voltage (V

) to the

DDI

voltage at which the card is activated (VCC).

8.4.6.1 IO Switching Control

The card interface IOs (IOUC, IOS1, IOS2 and IOS3) connect to the IOMC1 and IOMC2 through switches inside the TCA5013.

The IOUC pin is connected to IOMC1 through an SPST (single-pole single-throw) switch. The switch is controlled by the IO_EN_UC bit (Reg 0x01, Bit 5).The IO_EN_UC bit shall be set to 1 before card activation is started to ensure that the host processor is able to receive the ATR response from the smartcard. When an I2C command is received to open or close the switch, it is immediately implemented regardless of the status of IOUC or IOMC1 pins. It is therefore possible that the switch opens or closes during a rising or falling edge, which could result in a glitch on the IOUC or IOMC1 pins.

The IOS1, IOS2 and IOS3 all are connected to IOMC2 through a SP3T (single-pole triple-throw) switch, such that only one of the SAM interfaces can be connected to IOMC2 at any one time. The connection between the IOMC2 and the SAM card IO pins is controlled by IO_EN_S1 (Reg 0x11, Bit 5), IO_EN_S2 (Reg 0x21, Bit 5), IO_EN_S3 (Reg 0x31, Bit 5). If any one of the IO_EN bits is set for example, if SAM1 is initially connected by setting IO_EN of the SAM1 interface settings register to 1. When the IO_EN bit of the SAM2 or SAM3 is set to 1, the SAM1 gets disconnected and its IO_EN bit will be set to 0. Only one SAM can be connected to the IOUC2 at one time and whenever the IO_EN bit of any SAM interface settings register is set to 1, all other IO_EN bits get cleared (set to 0). Similar to the user card, the SAM IO mux can also result in a short duration pulse, if IOUC2 is not in the same state as the SAMs being switched to/from. Also when making the switch, the TCA5013 uses a break –before-make switch topology in order to avoid any glitches on the lines due to the switching itself.

8.4.6.2 IO Rise Time and Fall Time control

The rise time and fall time of the card interface IO pins can be controlled using the IO slew rate settings register (Reg 0x07 for user card and Reg 0x17 for SAMs). The EMV4.3 specification, has strict restrictions on signal perturbations (overshoot and undershoot during transition). Controlling the rise time and fall time of the signals can help to meet these requirements.

Table 6 shows the typical IO rise time for different register settings (based on a typical 30 pF load).

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Table 6. IO Rise Time Register Settings

IO SLEW RATE SETTINGS

000 60 001 60 010 80 011 80 100 100 101 100 110 120 111 120

TYPICAL RISE TIME (ns)

Table 7 shows the typical IO fall time for different register settings (based on a typical 30 pF load). It should also

be noted that the output low logic level (VOL) is affected by the fall time settings. As the fall time becomes slower (higher value of fall time) the VOLwill be higher. Therefore, it is recommended that the fastest fall time setting (smallest fall time value) for IO be used whenever possible. Table 7 also shows which settings are usable for the different VCCvoltages, without risk of violating the VOLlevels required by the EMV4.3 and ISO7816 specifications.

Table 7. IO Fall Time Register Settings

IO SLEW

RATE SETTINGS REGISTER

BIT [4:3]

00 68 Usable Not usable Not usable 01 51 Usable Not usable Not usable 10 34 Usable Usable Not usable 11 17 Usable Usable Usable

TYPICAL FALL

TIME (ns)

VCC= 5 V VCC= 3 V VCC= 1.8 V

8.4.6.3 Current Limiting on IO Pin

The card IO pins have a current limiting feature that prevents excess current from being drawn on them. The actual current limit can vary based on the fall time setting used for the IO pin, but it is always within the limits defined in Electrical Characteristics—Fault Condition Detection. When an external load tries to draw a current higher than the limit, the device responds by adjusting the VOHor VOLto limit the current. The device does not deactivate the card interface when over current limit of the IO pins are reached.

8.4.7 CLK Operation

All card interfaces in the TCA5013 have a CLK pin that provides a clock signal to the smartcard. The TCA5013 provides automatic level translation of the CLK signal from the CLKIN1/CLKIN2 operating voltage (V

) to the

DDI

voltage at which the card is activated (VCC).

8.4.7.1 CLK Switching

The CLK output on each of the smartcard interfaces can be controlled by the corresponding clock settings register (Reg 0x02 for user card, Reg 0x12 for SAM1, Reg 0x22 for SAM2, Reg 0x32 for SAM3). The CLKIN1 pin is dedicated for the user card interface while The CLKIN2 is shared between the SAM interfaces. The clock settings register allows the CLK output to be configured in one of 4 different modes.

A. CLK 0 mode - The CLK output of the card interface is static low. B. CLK 1 mode - The CLK output of the card interface is static high. C. CLK div mode - The CLK output is a divided down frequency of the CLKIN1 or CLKIN2 frequency. Bit [4:2] of

clock settings register defines the division ratio.

D. Internal CLK mode - The CLK output is at a fixed frequency (~1.2 MHz) based off the internal oscillator.

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Output clock frequency transition when changing clock divide ratio

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The allowable changes in CLK output can vary depending on the mode in which the interface has been activated. In asynchronous mode (see Asynchronous Operating Mode), The CLK output can be dynamically switched from one state to another. Table 8 shows the permitted frequency transitions on CLK pin in asynchronous mode. Any I2C command that attempts to switch the CLK frequency outside of these state transitions can result in the change not happening on the output or other unpredictable behavior that could cause device to lock up. If the device enters such a locked state, it can be reset by toggling SHDN pin.

Table 8. Permitted CLK Switching Operations in Asynchronous Mode

FROM TO

Internal CLK CLK div Permitted

Internal CLK CLK 0 Not Permitted Internal CLK CLK 1 Not Permitted

CLK div Internal CLK Permitted CLK div CLK 0 Permitted CLK div CLK 1 Permitted

CLK 0 CLK div Permitted

CLK 0 Internal CLK Not Permitted CLK 0 CLK1 Not Permitted

CLK 1 CLK div Permitted

CLK 1 Internal CLK Not Permitted CLK 1 CLK 0 Not Permitted

When command sets the device in Internal clock mode or CLK 0 mode or CLK 1 mode, the division ratio is locked out, that is, when an I2C transaction that sets either one of the bits [7:5] of the card clock settings register to 1, the remaining bits in the register (bit [4:2]) will not not be updated. It is to be noted that an asynchronous activation cannot be performed with the internal clock. At the start of the asynchronous activation, if the internal CLK mode is selected in the clock settings register, then the device shall begin activation based on divide ratio defined by bit [4:2] of clock settings register. After the activation is completed, the CLK output will switch to Internal CLK mode. When switching to/from a CLK div mode from/to CLK 0 mode or CLK 1 mode, the device waits for the input clock (CLKIN1 or CLKIN2) phase to match the static level it will switch to/from and then makes the transition to ensure that no partial pulses or glitches are seen on the output clock. Similarly, when switching from one division ratio to another the change happens on the rising clock edges to ensure no glitch on the output. Figure 15 shows how the change in divide ratio is seen on the CLK pin.

Figure 15. CLK Divide Ratio Change on Card CLK Output

When switching from CLK divide mode to the Internal CLK mode, the device waits for the edges of the internal and external clock to line up (fall within ~10 ns of each other) and makes the switch on that edge. If the external clock is close to an exact harmonic of 1.2 MHz, there could be a situation where the rising edges of the two clocks take very long (milliseconds or seconds) to line up and this would mean the frequency switch at the output would happen long after the I2C command to make the switch is issued. The CLKSW bit (bit [3]) in the card interface status register (Reg 0x01 for user card, Reg 0x11 for SAM1, Reg 0x21 for SAM2, Reg 0x31for SAM3) is set when the internal clock frequency is seen on the CLK pin.

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User card Clock settings register

Internal

Oscillator

CLK

divider

circuit

CLKIN1/8

CLKIN1/5

CLKIN1/4

CLKIN1/2

CLKIN1/1

CLKIN1

User card Clock settings register

Bit [6:5]

CLK_SYNC_ENABLE

Sync mode/

Async Mode

[1:x]

[0:x]

Async

Sync

CLK_UC

Internal

Clock

Output

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Figure 16. Output CLK Frequency Transition When Switching From External Clock to Internal Clock

In CLK divide mode, when CLKIN/2, CLKIN/4 or CLKIN/8 division ratios are used, the output duty cycle is not affected by the duty cycle of the input clock on CLKIN. When the CLKIN/1 and CLKIN/5 division ratios are used, the output clock duty cycle is a function of the CLKIN1/CLKIN2 duty cycle. For CLKIN/1 the output duty cycle will be equal to the input duty cycle. For CLKIN/5 the output CLK duty cycle is given by (n+2) / 5, where n is the duty cycle of the input clk; for example, if the input clk has a 40% duty cycle (n = 0.4) the CLKIN/5 output will have a (0.4+2) / 5 = 0.48 or 48% duty cycle. In addition to asynchronous mode, the user card interface can also operate in synchronous mode (see Synchronous Type 1 Operating Mode and Synchronous Type 2 Operating

Mode).When in synchronous mode the user card CLK pin output is controlled by CLK_ENABLE_SYNC (bit [2],

Reg 0x09) in addition to the clock settings register. Figure 17 shows a simplified logical representation of the user card clock muxing circuit.

Figure 17. Clock Muxing Logic in Synchronous Mode

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Unlike all the other bits that control the CLK, the CLK_ENABLE_SYNC can cause the CLK state to transition instantly. This means that when switching from a static level to a toggling CLK (or vice-versa), there can be partial pulses (glitches) on the CLK output when CLK_ENABLE_SYNC is switched. In sync mode, the CLK output can be switched directly from one static level to another, by using the CLK settings register (when CLK_SYNC_ENABLE = 0).

Table 9. Card CLK Truth Table in Synchronous Mode

CLK_ENABLE_SYNC

0 X 1 X X X X 1 0 X 0 X X X X 0 1 X X X X X X CLKIN1

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2

CARD CLOCK SETTINGS REGISTER

CARD CLK OUTPUT

8.4.7.2 CLK Rise Time and Fall Time Control

The clock slew rate setting register (Reg 0x08 for user card and Reg 0x18 for SAM) is used to control the rise and fall time of the CLK pin. Table 10 shows the rise and fall time corresponding to each register setting. The EMV4.3 specification, has strict restrictions on signal perturbations (overshoot and undershoot during transition). Controlling the rise time and fall time of the CLK signals can help to meet these requirements.

Table 10. CLK Rise and Fall Time Settings

CLOCK SLEW RATE SETTINGS

0000 6 0001 7 0010 9 0011 11 0100 13 0101 14 0110 15 0111 16 1000 17 1001 18 1010 19 1011 20 1100 21 1101 22 1110 23 1111 25

TYPICAL RISE TIME and FALL

RATE

8.4.7.3 Current Limiting On CLK Pin

The card CLK pins have a current limiting feature that prevents excess current from being drawn on them. When an external load tries to draw a current higher than the limit, the device responds by adjusting the VOHor VOLto limit the current. The device does not deactivate the card interface when over current limit of the CLK pins are reached.

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8.4.8 RST Operation

The RST pin operation depends on the mode in which the card interface has been activated. For user card interface and all the SAM card interfaces, in asynchronous mode (see Asynchronous Operating Mode) the RST pin status is automatically controlled by the TCA5013 internal state machine.

In synchronous mode (Synchronous Type 1 Operating Mode and Synchronous Type 2 Operating Mode) the RST pin status is controlled by the TCA5013 internal state machine, until the activation sequence is complete. After activation is complete, the RST pin status is controlled by RST bit (bit [3]) in the user card synchronous mode settings register (Reg 0x09). This operation is described in further detail in Synchronous Type 1 Operating Mode and Synchronous Type 2 Operating Mode.

8.4.8.1 Current Limiting On RST

The card RST pins have a current limiting feature that prevents excess current from being drawn on them. When an external load tries to draw a current higher than the limit, the device responds by adjusting the VOHor VOLto limit the current. The device does not deactivate the card interface when over current limit of the RST pins are reached.

8.4.9 Interrupt Operation

The INT pin is an open drain active low output pin that needs to be pulled up to V

with an external pull-up

DDI

resistor. The pull-up resistor shall be sized such that the rise time of the INT pin is < 100 µs. This is important since slower rise time could cause POR Interrupt to not be detected by the processor during TCA5013 startup. Generally speaking faster rise times on the INT line will reduce the chances of missing interrupts. There various interrupt events in the TCA5013 that can cause the INT pin to be asserted low. These interrupt events are described in the below sections.

8.4.9.1 Card Insertion And Removal

When card insertion or removal is detected on the user card interface (see User Card Insertion / Removal

Detection) the INT_UC bit (bit[7]) of interrupt status register (Reg 0x41) and the PRESL_UC bit (bit[2]) of User

card interface status register (Reg 0x00) are both set to 1 and the INT pin is asserted low. INT_UC is cleared and the INT pin is released when the interrupt status register is read. PRESL_UC is cleared only when the user card interface status register is read.

8.4.9.2 Over Current Fault

When the current drawn on the VCC pin of any of the card interfaces exceeds the over current limit (see

Electrical Characteristics—Fault Condition Detection) the PROT bit (bit[4]) of the card interface status register

(Reg 0x00 for user card, Reg 0x10 for SAM1, Reg 0x20 for SAM2 and Reg 0x30 for SAM3) is set. The interrupt bit corresponding to the card interface in the interrupt status register (Reg 0x41) is also set and the INT pin is asserted low. The interrupt bit is cleared and the INT pin is released, when the interrupt status register is read. The PROT bit is cleared only when the corresponding card interface status register is read.

8.4.9.3 Supervisor Fault

When the voltage on the VDD pin falls below the V

the INT_SUPL bit (bit[2] of Reg 0x41) and The

DDTH

STAT_SUPL bit (bit[1], Reg 0x10) are both set to 1 and the INT pin is asserted low. The INT_SUPL bit is cleared and the INT pin is released when the interrupt status register is read. The STAT_SUPL bit clears when the fault condition goes away, that is, VDD> V

DDTH

8.4.9.4 Over Temperature Fault

When the die temperature exceeds a safe operating temperature (typ. 125°C) INT_OTP bit (bit[3], Reg 0x41) and The STAT_OTP bit (bit[2], Reg 0x10) are both set to 1 and the INT pin is asserted low. The INT_OTP bit is cleared and the INT pin is released when the interrupt status register is read. The STAT_OTP clears when the fault condition goes away.

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8.4.9.5 EARLY Fault

In Asynchronous Operating Mode when the ATR response from the smartcard is received before the ‘ATR valid window’ (see Figure 6) the EARLY bit (bit [6]) of card interface status register (Reg 0x00 for user card, Reg 0x10 for SAM1, Reg 0x20 for SAM2 and Reg 0x30 for SAM3) is set and the INT pin is asserted low. The interrupt bit corresponding to the card interface in the interrupt status register (Reg 0x41) is also set. The interrupt bit is cleared and the INT pin is released, when the interrupt status register is read. The EARLY bit is cleared only when the corresponding card interface status register is read.

8.4.9.6 MUTE Fault

In Asynchronous Operating Mode when the ATR response from the smartcard is received after the ‘ATR valid window’ (refer to Figure 6) the MUTE bit (bit [5]) of card interface status register (Reg 0x00 for user card, Reg 0x10 for SAM1, Reg 0x20 for SAM2 and Reg 0x30 for SAM3) is set and the INT pin is asserted low. The interrupt bit corresponding to the card interface in the interrupt status register (Reg 0x41) is also set. The interrupt bit is cleared and the INT pin is released, when the interrupt status register is read. The EARLY bit is cleared only when the corresponding card interface status register is read.

8.4.9.7 Synchronous Activation Complete

In synchronous activation mode (see Synchronous Type 1 Operating Mode and Synchronous Type 2 Operating

Mode) once the activation sequence is completed, the INT_SYNC_COMPLETE bit (bit[1]) of interrupt status

register (Reg 0x41) is set and the INT pin is asserted low. The INT_SYNC_COMPLETE bit is cleared and the INT pin is released when the interrupt status registers is read.

8.4.9.8 VCCRamp Fault

During any activation sequence if the VCCvoltage fails to ramp to programmed value within 5 ms (typ), then the VCC_FAIL bit (bit[0]) of card interface status register (Reg 0x00 for user card, Reg 0x10 for SAM1, Reg 0x20 for SAM2 and Reg 0x30 for SAM3) is set and the INT pin is asserted low. The interrupt bit corresponding to the card interface in the interrupt status register (Reg 0x41) is also set. The interrupt bit is cleared and the INT pin is released, when the interrupt status register is read. The VCC_FAIL bit is cleared only when the corresponding card interface status register is read.

8.4.9.9 GPIO Input State Transition

When there is a state change on a GPIO pin configured as an input the INT_GPIO bit (bit[0]) of the interrupt status register (Reg 0x41) is set and the INT pin is asserted low. The INT_GPIO bit is cleared and the INT pin is released when the interrupt status register is read.

8.4.9.10 POR Interrupt

Whenever the device comes out of Power Off Mode or Shutdown Mode it goes through a power-on-reset (POR). Once the device internal power up sequence is completed the INT pin is asserted low without any of the bits in the interrupt status register (Reg 0x41) being set. Once the interrupt status register is read, the INT pin is released. When the device is coming out of shutdown mode of power off mode, none of the device functions will be available until the POR interrupt is asserted.

8.4.10 Power Management

The TCA5013 has power management features that enable the device to generate the appropriate card activation voltages and monitor the device power supplies for safe and secure system operation.

8.4.10.1 Voltage Supervisor

The TCA5013 has internal voltage supervisors that monitor VDDand V

voltages. When VDDfalls below V

DDI

DDTH

all card interfaces are deactivated and the supervisor fault (see Supervisor Fault) is asserted. The V

deactivated and the device enters power off mode (see Power Off Mode). When V

supervisor monitors the voltage on the V

DDI

pin. When V

DDI

falls below V

DDI

all card interfaces are

DDITH

falls below V

DDI

DDITH

the

supervisor fault is not asserted.

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DDITH

DDSH

DDTH

VDD> V

DDSH

DDI

< V

DDITH

Device stays in

power down

mode

Supervisor fault

is asserted

Supervisor fault

is cleared

VDD> V

DDSH

DDI

> V

DDITH

Device comes

out of POR

VDD< V

DDSH

DDI

> V

DDITH

Device is in

power down

mode

DDTH>VDD

> V

DDSH

DDI

> V

DDITH

Device comes out

of POR.

Supervisor fault is

asserted.

Supervisor

fault is cleared

VDD> V

DDTH

DDI

< V

DDITH

Device is enters

power down

mode

VDD> V

DDTH

DDI

> V

DDITH

Device comes

out of POR

VDD< V

DDSH

DDI

> V

DDITH

Device enters

power down

mode

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SCPS253C –JANUARY 2014–REVISED SEPTEMBER 2019

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It is possible that the supervisor fault is asserted during power up If V VDDramp rate). If VDDis ramped and stable before V

is ramped, the supervisor fault will not be asserted.

DDI

ramps before VDD(depending on the

DDI

Figure 18 shows the operation of voltage supervisor for various combinations of VDDand V

DDI

Figure 18. Voltage Supervisor Operation

8.4.10.2 DC-DC Boost

TCA5013 contains a DC-DC boost circuit that can step up VDDvoltage to generate the required card VCC. The boost requires an external diode (D

) as a high side switch. It also requires an external inductor (L

VUP

series with the VDD pin. The normal switching frequency of the boost is ~2.4 Mhz. The boost is rated for 180 mA. This implies that the sum of the current drawn on individual card VCC pins cannot exceed 180 mA. If exceeded it could result in the card VCCfalling out of the operating range defined in Electrical

Characteristics—Power Supply and ESD.

The DC_DC bit (Reg 0x42; Bit [7]) can be used to disable the DC-DC boost circuit. The DC-DC boost should be disabled only in systems where the supply is always guaranteed to be at least 0.25V greater than maximum card VCCsupported on that system, for example, if 5 V cards need to be supported in a system the DC-DC boost can be disabled if VDDis guaranteed to be above 5.25 V. In systems where DC-DC is not used, the VDD pin shall be shorted to VUP pin. The LX pin should shorted to GNDP. Shorting to GNDP is recommended to prevent switching noise from impacting rest of system. Note that LX shall not be connected to anything other than GNDP in order to prevent excess power loss and/or damage to the part. If DC-DC boost is disabled and the VDDis not sufficient to activate a card interface at the voltage set by SET_VCC (Reg 0x01, Reg 0x11, Reg 0x21, Reg 0x31; bit [7:6]), it will result in a VCCramp fault (See VCCRamp Fault).

The DC-DC boost is always disabled in standby mode (See Standby Mode). When a card activation command is received, the DC-DC boost circuit is enabled by the digital core. The boost output voltage depends on voltage at which the card needs to be activated, that is, based on SET_VCC (Reg 0x01, Reg 0x11, Reg 0x21, Reg 0x31; bit [7:6]). For 1.8-V and 3-V card activation, the boost output voltage will be ~3.5 V. For 5-V card activations the boost output voltage will be ~5.5 V. In a scenario where a 3 V or 1.8 V card is active and an I2C command is received to activate another card with 5 V, the boost output voltage will go up to 5.5 V and the card LDOs (See

LDOs and Load Transient Response) on the already active card interface, will keep the card VCCwithin

regulation. Under light load conditions, the DC-DC boost can enter pulse skipping mode in order to improve efficiency. In

pulse skipping mode, the switching frequency is not constant and will be much lower than the normal switching frequency of 2.4 MHz.

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VDD

) in

3V3V

1.8V

TCA5013

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8.4.10.3 LDOs and Load Transient Response

The TCA5013 has an internal LDO that generates a stable supply for the internal circuits. The input to the internal LDO is VDD. The output of the internal LDO is connected to the LDOCAP pin. A 1 uF decoupling capacitor shall be connected to the LDOCAP pin to ensure proper device operation. The internal LDO voltage is typically 2.65 V but can be lower if VDDis not sufficient.

In addition to the internal LDO, the TCA5013 has a dedicated LDO per card interface to generate the VCCfor that card interface (here on forth, these LDOs are referred to as card LDOs). The card LDOs provide the power supply for smartcard operation. During the normal operation of the smartcard, the LDO output is subject to load transients. The EMV4.3 standard defines a load transient envelope shown in Figure 19. The card LDOs are able to handle these transients, while keeping VCCwithin limits defined in Electrical Characteristics—Card VCC. An external 200 nF capacitor shall be connected to their card VCC pins (VCCUC, VCCCS1, VCCS2, VCCS3) to ensure proper load transient response by the card LDOs.

SCPS253C –JANUARY 2014 –REVISED SEPTEMBER 2019

Figure 19. Load Transients defined by EMV4.3

The card LDOs are enabled only when the card interface is activated (see Active Mode). The output voltage is determined by the card interface settings registers (Reg 0x01, Reg 0x11, Reg 0x21, Reg 0x31). At the start of the activation sequence, the card LDO is enabled and starts to ramp to the voltage defined in the corresponding card interface settings register. Once the LDO has been enabled, any changes to the card interface settings registers will not have any effect on the LDO output voltage. The card also LDOs also have short circuit protection. When the current drawn exceeds ~150 mA (typ.) the LDO automatically shuts down and the card interface is deactivated (see Deactivation Sequence).

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8.5 Programming

8.5.1 I2C Interface Operation

The device has a standard bidirectional I2C that is used by the microcontroller to access the device Register

Maps that is used to configure the device and read the status of various fault flags in the device. The interface

consists of the serial clock (SCL) and serial data (SDA) lines and is capable of MHz operation. Both SDA and SCL must be connected to V amount of capacitance on the I2C lines (for further details refer to I2C standard specification).

I2C communication with this device is initiated by a master (microcontroller) sending a START condition, a highto-low transition on the SDA input/output, while the SCL input is high. Only one data bit is transferred during each clock pulse. A STOP condition is a low-to-high transition on the SDA input/output while the SCL input is high. A STOP condition shall be sent by the master to indicate to the slave that a particular transaction has been completed. The data on the SDA line must remain stable during the high phase of the clock period, as changes in the data line when SCL is high are interpreted as control commands (START or STOP).

Figure 20 shows the definition of an I2C START condition and Figure 21 shows timing of a bit transfer on the I2C

bus. I2C

through a pull-up resistor. The size of the pull-up resistor is determined by the

DDI

Figure 20. Definition of Start and Stop Conditions

Figure 21. Bit Transfer

Any number of data bytes can be transferred from the master to slave (TCA5013) between the START and STOP conditions. Each byte of eight bits is followed by one ACK bit. The master must release the SDA line before the slave can send an ACK bit. To send an ACK bit the slave pulls down the SDA line during the low phase of ACK-related clock period, so that the SDA line is stable low during the high phase of the ACK-related clock period. When the slave is addressed, it generates an ACK after each byte is received. The master is not required to generate an ACK after each byte that it receives from the slave transmitter

Figure 22 shows the timing diagram for generation of the ACK bit on the I2C interface of the TCA5013

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DEVICE ADDRESS A AREGISTER ADDRESS

2nd and subsequent bytes of Register data are written to next register if Auto increment is enabled (AI=1)

2nd and subsequent bytes of register data are ignored if auto increment is disabled (AI=0).

SDA line is controlled by

Master

SDA line is controlled by

Slave

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Programming (continued)

Figure 22. Acknowledgment on I2C Bus

8.5.1.1 I2C Read and Write Procedures

Following the successful acknowledgment of the I2C address byte, the bus master shall send one register address byte indicating the address of the register on which the read or write operation needs to be performed. This register address is stored in an internal register and used by the device for subsequent read/write to the device. After the device address is acknowledged by the slave, all register addresses will be acknowledged even if an actual register is not defined for that address

The TCA5013 supports an auto increment feature by which multiple bytes can be written to consecutive registers without requiring the master to send the device address and register address for each data byte. Auto increment is enabled by setting the MSB of the register address to a 1 (see Figure 23). If auto increment is used to write the entire register map, the gaps in the register address map need to be written with dummy bytes. If auto increment is used to read the entire register map then data read from gaps in the register map will be 8’hFF

Figure 23. I2C Write Procedure

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SDA line is controlled by

Master

SDA line is controlled by

Slave

DEVICE ADDRESS A AREGISTER ADDRESS

2nd and subsequent bytes of Register data are read from the next register if Auto increment is enabled (AI=1)

2nd and subsequent bytes of register data are ignored if auto increment is disabled (AI=0).

DEVICE ADDRESS

SDA line is controlled by

Master

SDA line is controlled by

Slave

DEVICE ADDRESS A AREGISTER ADDRESS

S P

2nd and subsequent bytes of Register data are read from the next register if Auto increment is enabled (AI=1)

2nd and subsequent bytes of register data are ignored if auto increment is disabled (AI=0).

DEVICE ADDRESS

TCA5013

SCPS253C –JANUARY 2014–REVISED SEPTEMBER 2019

Programming (continued)

Figure 24. I2C Read Procedure

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Figure 25. I2C Read Procedure with Repeated Start

8.5.1.2 I2C Address Configuration

The I2C address of the TCA5013 can be configured using the A0. The A0 pin shall be connected to VDDI or GND to select one of the addresses, as shown in Table 11. The last bit in the address byte defines the operation (read or write)

Table 11. TCA5013 I2C address selection

B7 B6 B5 B4 B3 B2 B1 B0

GND 0 1 1 1 0 0 1 W/R Write - 72(h), Read – 73(h)

VDDI 0 1 1 1 1 1 0 W/R Write - 7C(h), Read – 7D(h)

SLAVE ADDRESS

I2C BUS SLAVE ADDRESS

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8.6 Register Maps

Memory Map

Address

(Hex)

00 User Card Interface Status R 00 0000 0000

01 User Card Interface Settings R/W 60 0110 0000

02 User Card Clock Settings R/W 0C 0000 1100

06 07 User Card IO Slew Rate Settings R/W 80 1000 0000 IO_TR_UC IO_TF_UC

08 User Card Clock Slew Rate Settings R/W A0 1010 0000 CLK_SR_UC 09 User Card Synchronous Mode Settings R/W 76 0111 0110 0A Synchronous Mode ATR Byte 1 R 00 0000 0000 BYTE1_UC

0B Synchronous Mode ATR Byte 2 R 00 0000 0000 BYTE2_UC 0C Synchronous Mode ATR Byte 3 R 00 0000 0000 BYTE3_UC 0D Synchronous Mode ATR Byte 4 R 00 0000 0000 BYTE4_UC

10 SAM1 Interface Status R 00 0000 0000

11 SAM1 Interface Settings R/W 40 0100 0000 SET_VCC_SAM1

12 SAM1 Clock Settings R/W 0C 0000 1100

17 SAM IO Slew Rate Settings R/W 80 1000 0000 IO_TR_SAM IO_TF_SAM

18 SAM Clock Slew Rate Settings R/W A0 1010 0000 CLK_SR_SAM

Asynchronous Mode ATR EARLY Counter MSB for User Card

Asynchronous Mode ATR EARLY Counter LSB for User Card

Asynchronous Mode ATR MUTE Counter MSB for User Card

Asynchronous Mode ATR MUTE Counter LSB for User Card

Asynchronous Mode ATR EARLY Counter MSB for SAM1

Asynchronous Mode ATR EARLY Counter LSB for SAM1

Asynchronous Mode ATR MUTE Counter MSB for SAM1

Asynchronous Mode ATR MUTE Counter LSB for SAM1

R/W AA 1010 1010 EARLY_COUNT_HI_UC

R/W 00 0000 0000 EARLY_COUNT_LO_UC

R/W A4 1010 0100 MUTE_COUNT_HI_UC

R/W 74 0111 0100 MUTE_COUNT_LO_UC

R/W AA 1010 1010 EARLY_COUNT_HI_SAM1

R/W 00 0000 0000

R/W A4 1010 0100 MUTE_COUNT_HI_SAM1

R/W 74 0111 0100 MUTE_COUNT_LO_SAM1

(Binary)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

ACTIVE_UC EARLY_UC MUTE_UC PROT_UC CLKSW_UC PRESL_UC PRES_UC VCC_FAIL_

SET_VCC_UC IO_EN_UC WARM_UC CARD_DET

INTERN_CL

K_UC

CARD_TYPEACTIVATIO

ACTIVE_SAM1EARLY_SAM1MUTE_SAM1PROT_SAM1CLKSW_SA

INTERN_CL

K_SAM1

EARLY_COUNT_LO_SAM

CLK0_UC CLK1_UC CLK_DIV_UC

N_TYPE

CLK0_SAM1CLK1_SAM

C4 C8 RST

IO_EN_SA

TCA5013

SCPS253C –JANUARY 2014–REVISED SEPTEMBER 2019

START_AS

YNC_UC

START_SY

SAM1

START_AS

YNC_SAM1

WARM_SA

CLK_DIV_SAM1

ECT_UC

CLK_ENAB

LE_SYNC

STAT_OTP

EDGE

STAT_SUPLVCC_FAIL_

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Memory Map (continued)

Address

(Hex)

20 SAM2 Interface Status R 00 0000 0000

21 SAM2 Interface Settings R/W 40 0100 0000 SET_VCC_SAM2

22 SAM2 Clock Settings R/W 0C 0000 1100

30 SAM3 Interface Status R 00 0000 0000

31 SAM3 Interface Settings R/W 40 0100 0000 SET_VCC_SAM3

32 SAM3 Clock Settings R/W 0C 0000 1100

40 Product Version R 00 0000 0000 PRODUCT_VER

41 Interrupt Status Register R 00 0000 0000 INT_UC INT_SAM1 INT_SAM2 INT_SAM3 INT_OTP INT_SUPL

42 Device Settings R/W 80 1000 0000 DC_DC GPIO4 GPIO3 GPIO2 GPIO1

43 GPIO Settings R/W xF xxxx1111

44 User Card Interrupt Mask Register R/W 00 0000 0000

Asynchronous Mode ATR EARLY Counter MSB for SAM2

Asynchronous Mode ATR EARLY Counter LSB for SAM2

Asynchronous Mode ATR MUTE Counter MSB for SAM2

Asynchronous Mode ATR MUTE Counter LSB for SAM2

Asynchronous Mode ATR EARLY Counter MSB for SAM3

Asynchronous Mode ATR EARLY Counter LSB for SAM3

Asynchronous Mode ATR MUTE Counter MSB for SAM3

Asynchronous Mode ATR MUTE Counter LSB for SAM3

SAM1 and SAM2 Interrupt Mask Register

SAM3 and GPIO Interrupt Mask Register

R/W AA 1010 1010 EARLY_COUNT_HI_SAM2

R/W 00 0000 0000

R/W A4 1010 0100 MUTE_COUNT_HI_SAM2

R/W 74 0111 0100 MUTE_COUNT_LO_SAM2

R/W AA 1010 1010 EARLY_COUNT_HI_SAM3

R/W 00 0000 0000

R/W A4 1010 0100 MUTE_COUNT_HI_SAM3

R/W 74 0111 0100 MUTE_COUNT_LO_SAM3

R/W 00 0000 0000

(Binary)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

ACTIVE_SAM2EARLY_SAM2MUTE_SAM2PROT_SAM2CLKSW_SA

IO_EN_SA

INTERN_CL

K_SAM2

EARLY_COUNT_LO_SAM

ACTIVE_SAM3EARLY_SAM3MUTE_SAM3PROT_SAM3CLKSW_SA

INTERN_CL

K_SAM3

EARLY_COUNT_LO_SAM

GPIO4_INPUTGPIO3_INPUTGPIO2_INPUTGPIO1_INPUTGPIO4_OU

EARLY_UC

_ MASK

EARLY_SA

M1_MASK

EARLY_SA

M3_MASK

CLK0_SAM2CLK1_SAM

IO_EN_SA

CLK0_SAM3CLK1_SAM

MUTE_UC_

MASK

MUTE_SAM

1_MASK

MUTE_SAM

3_MASK

PROT_UC_

MASK

PROT_SAM

1_MASK

PROT_SAM

3_MASK

SYNC_COM

PLETE_MASKOTP_MASK

EARLY_SA

M2_MASK

GPIO4_INT

_MASK

WARM_SA

CLK_DIV_SAM2

WARM_SA

CLK_DIV_SAM3

TPUT

MUTE_SAM

2_MASK

GPIO3_INT

_MASK

INT_SYNC_ COMPLETE

GPIO3_OU

TPUT

SUPL_MASKGPIO_INT_

PROT_SAM

2 _MASK

GPIO2_INT

_MASK

GPIO2_OU

TPUT

MASK

VCC_FAIL_ SAM_MASK

GPIO1_INT

_ MASK

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VCC_FAIL_

SAM2

START_AS

YNC_SAM2

VCC_FAIL_

SAM3

START_AS

YNC_SAM3

INT_GPIO

GPIO1_OU

TPUT

PRESL_INT

_ MASK

VCC_FAIL_

UC_ MASK

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0x00 User Card Interface Status

0x00

ADDRESS

0x01 User Card Interface Settings

0x01

1: Card interface is active (VCCis ramped and stable) 0: Card interface is inactive

1: Indicates card ATR was received before the ATR valid window. INT_UC bit is set in interrupt register.

Bit is cleared when the register is read 1: Indicates card ATR was not received within the ATR valid window.

INT_UC bit is set in interrupt register. Bit is cleared when the register is read.

1: Indicates over current condition on the card interface. INT_UC bit is set in interrupt register.

Bit clears when the register is read 1: Indicates the card interface is in internal CLK mode i.e frequency on

CLK pin is ~1.2 Mhz 0: Indicates the card interface is not in internal clock mode.

1: indicates the card has been inserted or extracted. INT_UC bit is set in interrupt register.

Bit is cleared when the register is read 1: indicates a card is present

0: indicates a card is not present 1: indicates VCCramp fault on card interface. INT_UC bit is set in

interrupt register. Bit is cleared when register is read

00 : set VCCto 1.8 V 01 : set VCCto 1.8 V 10 : set VCCto 3 V 11 : set VCCto 5 V

1: IOMC1 is connected IOUC 0: IOMC1 is disconnected from IOUC

1: Warm reset sequence is started on user card interface Bit is clears when warm reset sequence starts. Bit is ignored if card interface is in synchronous type 1 operating mode, synchronous type 2 operating mode or manual operating mode.

1 :Low to high transition on PRES pin indicates card insertion 0 : High to low transition on PRES pin indicates card insertion

1: Starts asynchronous activation sequence 0: Starts deactivation sequence Bit clears when automatic deactivation occurs Bit is ignored if card interface is in synchronous type 1 operating mode, synchronous type 2 operating mode or manual operating mode.

TCA5013

SCPS253C –JANUARY 2014 –REVISED SEPTEMBER 2019

Table 12.

DESCRIPTION FIELD NAME BIT R/W DEFAULT

ACTIVE_UC 7 R 1'b0

EARLY_UC 6 R 1'b0

MUTE_UC 5 R 1'b0

PROT_UC 4 R 1'b0

CLKSW_UC 3 R 1'b0

PRESL_UC 2 R 1'b0

PRES_UC 1 R 1'b0

VCC_FAIL_UC 0 R 1’b0

Table 13.

DESCRIPTION FIELD NAME BIT R/W DEFAULT

SET_VCC_UC [7:6] R/W 2'b01

IO_EN_UC 5 R/W 1'b1

WARM_UC 3 R/W 1'b0

CARD_DETECT_UC 2 R/W 1'b0

START_ASYNC_UC 0 R/W 1'b0

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SCPS253C –JANUARY 2014–REVISED SEPTEMBER 2019

Table 14.

ADDRESS

0x02 User Card Clock Settings

In asynchronous operating mode (START_ASYNC=1)

0x02

0x03

0x03 MSB (8-bits) of programmable 10-bit clock counter value. EARLY_COUNT_HI_UC [7:0] R/W 8'b10101010

0x04

0x04 LSB (2-bits) of programmable 10-bit clock counter value. EARLY_COUNT_LO_UC [7:6] R/W 2'b00

0x05

0x06

0x06 LSB (8-bits) of programmable 16-Bit clock counter value. MUTE_COUNT_LO_UC [7:0] R/W 8'b01110100

0x07 User Card IO Slew Rate Settings

0x07 3 Bit value defining the rise time of IOUC IO_TR_UC [7:5] R/W 3'b100 0x07 2 Bit value defining the fall time of IOUC IO_TF_UC [4:3] R/W 2'b00

0x08 User Card Clock Slew Rate Settings

0x08

1: CLKUC is set to ~1.2 MHz 0: CLKUC is set by Bit[6] or Bit[5] or Bit[4:2]

In synchronous operating mode (START_SYNC=1)

Bit is ignored in Sync mode

In asynchronous operating mode (START_ASYNC=1)

1: CLKUC is set to 0 0: CLKUC is set by Bit[5] or Bit[4:2]

In synchronous operating mode (START_SYNC=1)

1: CLKUC is set to 0 0: CLKUC is set by Bit5.

In asynchronous operating mode (START_ASYNC=1)

1: CLKUC is set to 1 0: CLKUC is set by Bit[4:2]

In synchronous operating mode (START_SYNC=1) Usable only is CLK_ENABLE_SYNC=0

1: CLKUC is set to 1 0: CLKUC is set to 1

In asynchronous operating mode (START_ASYNC=1)

000: CLKUC frequency = CLKIN1 001: CLKUC frequency = CLKIN1/2. 010: CLKUC frequency = CLKIN1/4. 011: CLKUC frequency = CLKIN1/5. 100: CLKUC frequency = CLKIN1/8. 101: CLKUC frequency = CLKIN1/8. 110: CLKUC frequency = CLKIN1/8. 111: CLKUC frequency = CLKIN1/8.

In synchronous operating mode (START_SYNC=1) Usable only is CLK_ENABLE_SYNC=1

[111:000] : CLKUC = CLKIN1

Asynchronous Mode ATR EARLY Counter MSB for User Card

Asynchronous Mode ATR EARLY Counter LSB for User Card

Asynchronous Mode ATR MUTE Counter MSB for User Card

MSB (8-bits) of programmable 16-Bit clock counter value.

Asynchronous Mode ATR MUTE Counter LSB for User Card

4 Bit value defining the rise time and fall time of the CLKUC

DESCRIPTION FIELD NAME BIT R/W DEFAULT

INTERN_CLK_UC 7 R/W 1'b0

CLK0_UC 6 R/W 1'b0

CLK1_UC 5 R/W 1'b0

CLK_DIV_UC [4:2] R/W 3'b011

MUTE_COUNT_HI_UC [7:0] R/W 8'b10100100

CLK_SR_UC [7:4] R/W 4'b1010

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ADDRESS

0x09 User Card Synchronous Mode Settings

0x09

0: Synchronous Type 1 card activation is selected 1: Synchronous Type 2 card activation is selected

1: Automatic activation per bit[7] is selected 0: Manual operating mode is selected

0 :Llow level is driven on C4 or C4 is being driven low externally 1 : C4 is pulled up high by internal pull-up Bit has no effect if

card interface is not active 0 : Low level is driven on C8 or C8 is being driven low externally

1 : C8 is pulled up high by internal pull-up Bit has no effect if card interface is not active

0 : Low level is driven on RSTUC 1 : High level is driven on RSTUC

Bit has no effect when card interface is not active. Bit has no effect if card interface is activated in asynchronous operating mode

0 : CLKUC is driven low or high based on the clock settings register (Reg 0x02, Bit [6:5])

1 : CLK output is controlled by CLKIN1 Bit has no effect when card interface is not active. Bit has no effect if card interface is activated in asynchronous

operating mode 1 : IO line is sampled on rising edge during synchronous type 1

activation sequence 0 : IO line sampled on falling edge during synchronous type 1

activation sequence Bit has no effect when card interface is not active. Bit has no effect if card interface is activated in asynchronous

operating mode 1 : Start card interface activation based on bit[7:6]

0: Start deactivation sequence bit clears when automatic deactivation occurs.

DESCRIPTION FIELD NAME BIT R/W

TCA5013

SCPS253C –JANUARY 2014 –REVISED SEPTEMBER 2019

Table 15.

DEFAUL

CARD_TYPE 7 R/W 1'b0

ACTIVATION_TYPE 6 R/W 1'b1

C4 5 R/W 1'b1

C8 4 R/W 1'b1

RST 3 R/W 1'b0

CLK_ENABLE_SYNC 2 R/W 1'b1

EDGE 1 R/W 1'b1

START_SYNC 0 R/W 1'b0

ADDRESS

0x0A Synchronous Mode ATR Byte1

0x0A Bit 7 to Bit 0 of ATR response BYTE1_UC [7:0] R 8'b00000000

0x0B Synchronous Mode ATR Byte2

0x0B Bit 15 to Bit 8 of ATR response BYTE2_UC [7:0] R 8'b00000000

0x0C Synchronous Mode ATR Byte3

0x0C Bit 23 to Bit 16 of ATR response BYTE3_UC [7:0] R 8'b00000000 0x0D Synchronous Mode ATR Byte4 0x0D Bit 31 to Bit 24 of ATR response BYTE4_UC [7:0] R 8'b00000000

DESCRIPTION FIELD NAME BIT R/W DEFAULT

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SCPS253C –JANUARY 2014–REVISED SEPTEMBER 2019

ADDRESS

0x10 SAM1 Interface Status

0x10

0x11 SAM1 Interface Settings

0x11

1: Card interface is active (VCCis ramped and stable) 0: Card interface is inactive

1: Indicates card ATR was received before the ATR valid window. INT_SAM1 bit is set in interrupt register.

Bit is cleared when the register is read 1: Indicates card ATR was not received within the ATR valid

window. INT_SAM1 bit is set in interrupt register. Bit is cleared when the register is read.

1: Indicates over current condition on the card interface. INT_SAM1 bit is set in interrupt register. Bit clears when the register is read

1: Indicates the card interface is in internal CLK mode i.e frequency on CLK pin is ~1.2 Mhz

0: Indicates the card interface is not in internal clock mode. 1: Indicates that an over temperature fault condition exists

0: Over temperature fault doesn’t exist 1: Indicates a supervisor fault condition exists.

0: Supervisor fault condition doesn’t exist. 1: Indicates VCCramp fault on card interface.

INT_SAM1 bit is set in interrupt register. Bit is cleared when register is read

00 : Set VCCto 1.8 V 01 : Set VCCto 1.8 V 10 : Set VCCto 3 V 11 : Set VCCto 5 V

1: IOMC2 is connected to IOS1 0: IOMC2 is disconnected from IOS1

1: Warm reset sequence is started on SAM1 Bit is clears when warm reset sequence starts.

1: Starts activation sequence 0: Starts deactivation sequence

Bit clears when automatic deactivation occurs

DESCRIPTION FIELD NAME BIT R/W DEFAULT

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Table 16.

ACTIVE_SAM1 7 R 1'b0

EARLY_SAM1 6 R 1'b0

MUTE_SAM1 5 R 1'b0

PROT_UC_SAM1 4 R 1'b0

CLKSW_SAM1 3 R 1'b0

STAT_OTP 2 R 1'b0

STAT_SUPL 1 R 1'b0

VCC_FAIL_SAM1 0 R 1’b0

SET_VCC_SAM1 [7:6] R/W 2'b01

IO_EN_SAM1 5 R/W 1'b0

WARM_SAM1 3 R/W 1'b0

START_ASYNC_SAM1 0 R/W 1'b0

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SCPS253C –JANUARY 2014 –REVISED SEPTEMBER 2019

0x12 SAM1 Clock Settings

0x12

0x13

0x13 MSB (8-bits) of programmable 10-bit clock counter value EARLY_COUNT_HI_SAM1 [7:0] R/W 8'b10101010

0x14

0x14 LSB (2-bits) of programmable 10-bit clock counter value

1 : Card CLK is set to ~1.2 MHz 0 : Card CLK is set by Bit[6], Bit[5] or Bit[4:2]

1 : Card CLK is set to 0 0 : Card CLK is set by Bit[5] or Bit[4:2]

1 : Card CLK is set to 1 0 : Card CLK is set by Bit[4:2]

000 : CLKS1 frequency = CLKIN2 001 : CLKS1 frequency = CLKIN2/2 010 : CLKS1 frequency = CLKIN2/4 011 : CLKS1 frequency = CLKIN2/5 100: CLKS1 frequency = CLKIN2/8 101: CLKS1 frequency = CLKIN2/8 110: CLKS1 frequency = CLKIN2/8 111: CLKS1 frequency = CLKIN2/8

Asynchronous Mode ATR EARLY Counter MSB for SAM1

Asynchronous Mode ATR EARLY Counter LSB for SAM1

DESCRIPTION FIELD NAME BIT R/W DEFAULT

INTERN_CLK_SAM1 7 R/W 1'b0

CLK0_SAM1 6 R/W 1'b0

CLK1_SAM1 5 R/W 1'b0

CLK_DIV_SAM1 [4:2] R/W 3'b011

EARLY_COUNT_LO_SAM 1

[7:6] R/W 2'b00

Table 17.

ADDRESS

0x15 Asynchronous Mode ATR MUTE counter MSB for SAM1

0x15 MSB (8-bits) of programmable 16-bit clock counter value MUTE_COUNT_HI_SAM1 [7:0] R/W 8'b10100100

0x16 Asynchronous Mode ATR MUTE counter LSB for SAM1

0x16 MSB (8-bits) of programmable 16-bit clock counter value MUTE_COUNT_LO_SAM1 [7:0] R/W 8'b01110100

0x17 SAM IO Slew Rate Settings

0x17

0x18 SAM Clock Slew Rate Settings

0x18

3-Bit value defining the rise time of IO pin for all SAM interfaces

2-Bit value defining the rise time of IO pin for all SAM interfaces

4-Bit value defining the rise time and fall time of CLK for all SAM interfaces

DESCRIPTION FIELD NAME BIT R/W DEFAULT

IO_TR_SAM [7:5] R/W 3'b100

IO_TF_SAM [4:3] R/W 2'b00

CLK_SR_SAM1 [7:4] R/W 4'b1010

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ADDRESS

0x20 SAM2 Interface Status

0x20

0x21 SAM2 Interface Settings

0x21

1: Card interface is active (VCCis ramped and stable) 0: Card interface is inactive

1: Indicates card ATR was received before the ATR valid window. INT_SAM2 bit is set in interrupt register.

Bit is cleared when the register is read 1: Indicates card ATR was not received within the ATR valid

window. INT_SAM2 bit is set in interrupt register. Bit is cleared when the register is read.

1: Indicates over current condition on the card interface. INT_SAM2 bit is set in interrupt register.

Bit clears when the register is read 1: Indicates the card interface is in internal CLK mode i.e frequency

on CLK pin is ~1.2Mhz 0: Indicates the card interface is not in internal clock mode.

1: indicates VCCramp fault on card interface. INT_SAM2 bit is set in interrupt register.

Bit is cleared when register is read

00 : set VCCto 1.8 V 01 : set VCCto 1.8 V 10 : set VCCto 3 V 11 : set VCCto 5 V

1: IOMC2 is connected to IOS2 0: IOMC2 is disconnected from IOS2

1: Warm reset sequence is started on SAM2 Bit is clears when warm reset sequence starts.

1: Starts activation sequence 0: Starts deactivation sequence

Bit clears when automatic deactivation occurs

DESCRIPTION FIELD NAME BIT R/W

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Table 18.

DEFAU

ACTIVE_SAM2 7 R 1'b0

EARLY_SAM2 6 R 1'b0

MUTE_SAM2 5 R 1'b0

PROT_UC_SAM2 4 R 1'b0

CLKSW_SAM2 3 R 1'b0

VCC_FAIL_SAM2 0 R 1’b0

SET_VCC_SAM2 [7:6] R/W 2'b01

IO_EN_SAM2 5 R/W 1'b0

WARM_SAM2 3 R/W 1'b0

START_ASYNC_SAM2 0 R/W 1'b0

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ADDRESS

0x22 SAM2 Clock Settings

0x22

0x23

0x24

0x25

0x26

1 : Card CLK is set to ~1.2MHz 0 : CLKS2 is set by Bit[6] or Bit [5] or Bit[4:2]

1 : Card CLK is set to 0 0 : CLKS2 is set by Bit[5] or Bit[4:2]

1 : Card CLK is set to 1 0 : CLKS2 is set by Bit[4:2]

000 : CLKS2 frequency = CLKIN2 001 : CLKS2 frequency = CLKIN2/2 010 : CLKS2 frequency = CLKIN2/4 011 : CLKS2 frequency = CLKIN2/5 100: CLKS2 frequency = CLKIN2/8 101: CLKS2 frequency = CLKIN2/8 110: CLKS2 frequency = CLKIN2/8 111: CLKS2 frequency = CLKIN2/8

Asynchronous Mode ATR EARLY Counter MSB for SAM2

MSB (8-bits) of programmable 10-bit clock counter value.

Asynchronous Mode ATR EARLY Counter LSB for SAM2

LSB (2-bits) of programmable 10-bit clock counter value.

Asynchronous Mode ATR MUTE Counter MSB for SAM2

MSB (8-bits) of programmable 16-bit clock counter value.

Asynchronous Mode ATR MUTE Counter LSB for SAM2

MSB (8-bits) of programmable 16-bit clock counter value.

TCA5013

SCPS253C –JANUARY 2014 –REVISED SEPTEMBER 2019

Table 19.

DESCRIPTION FIELD NAME BIT R/W DEFAULT

INTERN_CLK_SAM2 7 R/W 1'b0

CLK0_SAM2 6 R/W 1'b0

CLK1_SAM2 5 R/W 1'b0

CLK_DIV_SAM2 [4:2] R/W 3'b011

EARLY_COUNT_HI_SAM2 [7:0] R/W 8'b10101010

EARLY_COUNT_LO_SAM2 [7:6] R/W 2'b00

MUTE_COUNT_HI_SAM2 [7:0] R/W 8'b10100100

MUTE_COUNT_LO_SAM2 [7:0] R/W 8'b01110100

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ADDRESS

0x30 SAM3 Interface Status

0x30

0x31 SAM3 Interface Settings

0x31

1: Card interface is active (VCCis ramped and stable) 0: Card interface is inactive

1: Indicates card ATR was received before the ATR valid window. INT_SAM3 bit is set in interrupt register.

Bit is cleared when the register is read 1: Indicates card ATR was not received within the ATR valid

window. INT_SAM3 bit is set in interrupt register. Bit is cleared when the register is read.

1: Indicates over current condition on the card interface. INT_SAM3 bit is set in interrupt register

Bit clears when the register is read 1: Indicates the card interface is in internal CLK mode i.e

frequency on CLK pin is ~1.2Mhz 0: Indicates the card interface is not in internal clock mode.

1: Indicates VCCramp fault on card interface. INT_SAM3 bit is set in interrupt register.

Bit is cleared when register is read

00 : set VCCto 1.8 V 01 : set VCCto 1.8 V 10 : set VCCto 3V 11 : set VCCto 5V

1: IOMC2 is connected to IOS3 0: IOMC2 is disconnected from IOS3

1: Warm reset sequence is started on SAM3 Bit is clears when warm reset sequence starts.

1: Starts activation sequence 0: Starts deactivation sequence

Bit clears when automatic deactivation occurs

DESCRIPTION FIELD NAME BIT R/W DEFAULT

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Table 20.

ACTIVE_SAM3 7 R 1'b0

EARLY_SAM3 6 R 1'b0

MUTE_SAM3 5 R 1'b0

PROT_UC_SAM3 4 R 1'b0

CLKSW_SAM3 3 R 1'b0

VCC_FAIL_SAM3 0 R 1’b0

SET_VCC_SAM3 [7:6] R/W 2'b01

IO_EN_SAM3 5 R/W 1'b0

WARM_SAM3 3 R/W 1'b0

START_ASYNC_SAM3 0 R/W 1'b0

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ADDRESS

0x32 SAM3 Clock Settings

0x32

0x33

0x34

0x35

0x36

1 : CLKS3 is set to ~1.2 Mhz 0 : CLKS3 is set by Bit[6] or Bit [5] or Bit[4:2]

1 : CLKS3 is set to 0 0 : CLKS3 is set by Bit[5] or Bit[4:2]

1 : CLKS3 is set to 1 0 : CLKS3 is set by Bit[4:2]

000 : CLKS3 frequency = CLKIN2 001 : CLKS3 frequency = CLKIN2/2 010 : CLKS3 frequency = CLKIN2/4 011 : CLKS3 frequency = CLKIN2/5 100: CLKS3 frequency = CLKIN2/8 101: CLKS3 frequency = CLKIN2/8 110: CLKS3 frequency = CLKIN2/8 111: CLKS3 frequency = CLKIN2/8

Asynchronous Mode ATR EARLY Counter MSB for SAM3

MSB (8-bits) of programmable 10-bit clock counter value.

Asynchronous Mode ATR EARLY Counter LSB for SAM3

LSB (2-bits) of programmable 10-bit clock counter value.

Asynchronous Mode ATR MUTE Counter MSB for SAM3

MSB (8-bits) of programmable 16-bit clock counter value.

Asynchronous Mode ATR MUTE Counter LSB for SAM3

MSB (8-bits) of programmable 16-bit clock counter value.

TCA5013

SCPS253C –JANUARY 2014 –REVISED SEPTEMBER 2019

Table 21.

DESCRIPTION FIELD NAME BIT R/W DEFAULT

INTERN_CLK_SAM3 7 R/W 1'b0

CLK0_SAM3 6 R/W 1'b0

CLK1_SAM3 5 R/W 1'b0

CLK_DIV_SAM3 [4:2] R/W 3'b011

EARLY_COUNT_HI_SAM3 [7:0] R/W 8'b10101010

EARLY_COUNT_LO_SAM3 [7:6] R/W 2'b00

MUTE_COUNT_HI_SAM3 [7:0] R/W 8'b10100100

[7:0] R/W 8'b01110100

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Table 22.

ADDRESS

0x40 Product Version

0x40 Product Version PRODUCT_VER [7:0] R 8'b00000000

0x41 Interrupt Status Register

1: PROT, MUTE, EARLY, VCC_FAIL or PRESL bit set in

0x41

0x42 Device Settings

0x42

User card. INT pin is asserted low when this bit is set. 0 : Bit clears when Register is read

1: PROT, VCC_FAIL, MUTE or EARLY bit set in SAM1. INT is asserted low when this bit is set.

0 : Bit clears when Register is read 1: PROT, VCC_FAIL, MUTE or EARLY bit set in SAM2. INT

is asserted low when this bit is set. 0 : Bit clears when Register is read

1: PROT, VCC_FAIL, MUTE or EARLY bit set in SAM3. INT is asserted low when this bit is set.

0 : Bit clears when Register is read 1: All card interfaces deactivated due to over temperature

fault. INT is asserted low when this bit is set. 0 : Bit clears when Register is read

1: All card interfaces deactivated due to Supervisor fault. INT is asserted low when this bit is set.

0 : Bit clears when register is read 1: Sync card activation sequence complete. INT is asserted

low when this bit is set. 0 : Bit clears when register is read

1: One of the GPIO inputs has changes state. INT is asserted low when this bit is set.

0 : Bit clears when register is read

1: DC-DC boost is enabled 0: DC-DC boost is disabled

1: GPIO4 is configured as input 0: GPIO4 is configured as output

1: GPIO3 is configured as input 0: GPIO3 is configured as output

1: GPIO2 is configured as input 0: GPIO2 is configured as output

1: GPIO1 is configured as input 0: GPIO1 is configured as output

DESCRIPTION FIELD NAME BIT R/W DEFAULT

INT_UC 7 R 1'b0

INT_SAM1 6 R 1'b0

INT_SAM2 5 R 1'b0

INT_SAM3 4 R 1'b0

INT_OTP 3 R 1'b0

INT_SUPL 2 R 1'b0

INT_SYNC_COMPLETE 1 R 1'b0

INT_GPIO 0 R 1'b0

DC_DC 7 R/W 1'b1

GPIO4 5 R/W 1'b0

GPIO3 4 R/W 1'b0

GPIO2 3 R/W 1'b0

GPIO1 2 R/W 1'b0

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SCPS253C –JANUARY 2014 –REVISED SEPTEMBER 2019

Table 23.

ADDRESS

0x43 GPIO Settings

0x43 Reflects level on GPIO4 (read only) GPIO4_INPUT 7 R 1'b0

0x43 Reflects level on GPIO3 (read only) GPIO3_INPUT 6 R 1'b0

0x43 Reflects level on GPIO2 (read only) GPIO2_INPUT 5 R 1'b0

0x43 Reflects level on GPIO1 (read only) GPIO1_INPUT 4 R 1'b0

0x43

0x44 User Card Interrupt Mask Register

0x44

Sets level on GPIO4 (Bit is ignored if pin is configured as input)

Sets level on GPIO3 (Bit is ignored if pin is configured as input)

Sets level on GPIO2 (Bit is ignored if pin is configured as input)

Sets level on GPIO1 (Bit is ignored if pin is configured as input)

1: Mask User card EARLY Interrupt 0: Unmask User card EARLY interrupt

1: Mask User Card MUTE Interrupt 0: Unmask User Card MUTE interrupt

1: Mask User Card PROT Interrupt 0: Unmask User Card PROT interrupt

1: Mask sync card activation complete Interrupt 0: Unmask sync card activation complete interrupt

1: Mask thermal shutdown Interrupt 0: Unmask thermal shutdown interrupt

1: Mask supervisor fault Interrupt 0: Unmask supervisor fault interrupt

1: Mask all GPIO Interrupt 0: Unmask all GPIO interrupt

1: Mask PRESL Interrupt 0: Unmask PRESL interrupt

DESCRIPTION FIELD NAME BIT R/W DEFAULT

GPIO4_OUTPUT 3 R/W 1'b1

GPIO3_OUTPUT 2 R/W 1'b1

GPIO2_OUTPUT 1 R/W 1'b1

GPIO1_OUTPUT 0 R/W 1'b1

EARLY_UC_MASK 7 R/W 1'b0

MUTE_UC _MASK 6 R/W 1'b0

PROT_UC_MASK 5 R/W 1'b0

SYNC_COMPLETE_MASK 4 R/W 1'b0

OTP_MASK 3 R/W 1'b0

SUPL_MASK 2 R/W 1'b0

GPIO_INT_MASK 1 R/W 1'b0

PRESL_INT_MASK 0 R/W 1'b0

TCA5013

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ADDRESS

0x45 SAM1 and SAM2 Interrupt Mask Register

0x45

0x46 SAM3 and GPIO Interrupt Mask Register

0x46

1: Mask SAM1 EARLY Interrupt 0: Unmask SAM1 EARLY interrupt

1: Mask SAM1 MUTE Interrupt 0: Unmask SAM1 MUTE interrupt

1: Mask SAM1 PROT Interrupt 0: Unmask SAM1 PROT interrupt

1: Mask SAM2 EARLY Interrupt 0: Unmask SAM2 EARLY interrupt

1: Mask SAM2 MUTE Interrupt 0: Unmask SAM2 MUTE interrupt

1: Mask SAM2 PROT Interrupt 0: Unmask SAM2 PROT interrupt

1: Mask VCC_FAIL Interrupt on all SAMs 0: Unmask VCC_FAIL Interrupt on all SAMs

1: Mask VCC_FAIL Interrupt on all User Card 0: Unmask VCC_FAIL Interrupt on all User Card

1: Mask SAM3 EARLY Interrupt 0: Unmask SAM3 EARLY interrupt

1: Mask SAM3 MUTE Interrupt 0: Unmask SAM3 MUTE interrupt

1: Mask SAM3 PROT Interrupt 0: Unmask SAM3 PROT interrupt

1: Mask GPIO4 Interrupt 0: Unmask GPIO4 interrupt

1: Mask GPIO3 Interrupt 0: Unmask GPIO3 interrupt

1: Mask GPIO2 Interrupt 0: Unmask GPIO2 interrupt

1: Mask GPIO1 Interrupt 0: Unmask GPIO1 interrupt

DESCRIPTION FIELD NAME BIT R/W DEFAULT

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Table 24.

EARLY_SAM1_MASK 7 R/W 1'b0

MUTE_SAM1 _MASK 6 R/W 1'b0

PROT_SAM1_MASK 5 R/W 1'b0

EARLY_SAM2_MASK 4 R/W 1'b0

MUTE_SAM2 _MASK 3 R/W 1'b0

PROT_SAM2_MASK 2 R/W 1'b0

VCC_FAIL_SAM_MASK 1 R/W 1'b0

VCC_FAIL_UC_MASK 0 R/W 1'b0

EARLY_SAM3_MASK 7 R/W 1'b0

MUTE_SAM3 _MASK 6 R/W 1'b0

PROT_SAM3_MASK 5 R/W 1'b0

GPIO4_INT_MASK 4 R/W 1'b0

GPIO3_INT_MASK 3 R/W 1'b0

GPIO2_INT_MASK 2 R/W 1'b0

GPIO1_INT_MASK 1 R/W 1'b0

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SDA SCL

SHDN

INT

IOMC1

CLKIN1

IOMC2

CLKIN2

VDD

VUP

VDDI

PRES

VCCUC

GNDUC

IOUC

CLKUC

RSTUC

VCCS1

IOS1

CLKS1

RSTS1

VCCS3

IOS3

VCCS2

IOS2

CLKS2

RSTS2

CLKS3 RSTS3

GNDS

TCA5013

GNDS

GPIO1

GPIO2

GPIO3

GPIO4

TST3

TST2

TST1

DDI

User Card

Slot

SAM1

Card

Slot

SAM2

Card

Slot

GNDP

Microcontroller

10k

10k 10k

10k

100nF

VUP

10uF

10k

VDD

10uH

VDD

100uF

200nF

LDOCAP

1uF

TST4

GND

SAM3

Card

Slot

200nF

VDD=V

DDI

= 3.3 V

VUP

TCA5013

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SCPS253C –JANUARY 2014 –REVISED SEPTEMBER 2019

9 Application and Implementation

9.1 Application Information

TCA5013 is a smartcard interface IC that is used in POS terminals that support EMV 4.3, ISO7816 - 3 and ISO 7816 - 10 smartcards. The below application note provides general guidelines for implementing the device in a POS terminal.

9.2 Typical Application

Figure 26. POS Terminal Typical Application

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100

150

200

250

300

350

0 200 400 600 800 1000 1200

(mV)

IOL (A)

REG 07H Bit [4:3] 00 REG 07H Bit [4:3] 01 REG 07H Bit [4:3] 10 REG 07H Bit [4:3] 11

C002

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SCPS253C –JANUARY 2014–REVISED SEPTEMBER 2019

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Typical Application (continued)

9.2.1 Design Requirements

For this design example shown below, Table 25 shows the input parameters.

Table 25. Design Parameters

DESIGN PARAMETER EXAMPLE VALUE

VDDinput Voltage range 2.7 V to 4.2 V

input Voltage range 2.7 V to 4.2 V

DDI

VCCoutput Voltage range 1.8 V, 3 V, 5 V

Sum of all ICC currents 180 mA (max)

VCCoutput ripple voltage 90 mV (max)

Max load transient supported on

9.2.2 Detailed Design Procedure

9.2.2.1 IO Pin Fall Time Setting

The VOLon the IO pin depends on the IO fall time setting shown in Table 7. It also shows the different IO fall time settings that are usable for different VCCvoltage. Care should be taken to select a register setting such that V meets the system requirements.

As defined in the Electrical

Characteristics—Card V

9.2.2.2 CLK Pin Rise Time And Fall Time Settings

Electrical Characteristics—Card CLK shows the typical rise and fall time of the clock signal for a 30 pF load.

Because most applications will not have a typical 30 pF load, the rise and fall time of the clock signal will need to be calibrated for the board. EMV 4.3 specifies that the rise/fall time on the clock signal shall not be more than 8% of the clock period. It is recommended that the slowest fall time setting that meets the EMV requirement be selected. For systems where multiple clock frequencies will be used, it is recommended that a different fall time setting be used for each clock frequency.

9.2.3 Application Curves

Figure 27. VOLvs IOLfor User Card

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10 Power Supply Recommendations

TCA5013

SCPS253C –JANUARY 2014 –REVISED SEPTEMBER 2019

The TCA5013 has two power supplies VDDand V V

can cause the supervisor fault to be asserted. The supervisor fault at power up can be avoided if VDDis

DDI

ramped and stable before V

is ramped.

DDI

. When the device is powering up, the ramp rates of VDDand

DDI

10.1 Power-On-Reset

When the voltage on these pins ramps an internal power-on-reset circuit holds the device in reset condition unless the voltage on both pins rises above the VPORR voltage defined Table 26. Values in Table 26 are ensured by design, but are not tested in production.

Table 26. Power On Reset Thresholds

PARAMETER DESCRIPTION MIN TYP MAX UNIT

PORF

PORR

Voltage trip point of POR on falling V Voltage trip point of POR on falling V Voltage trip point of POR on rising V Voltage trip point of POR on rising V

DDI DD DDI

1.8 1.85 1.95 V

1.4 1.5 1.55 V

1.9 1.95 2 V

1.45 1.5 1.55 V

11 Layout

11.1 Layout Guidelines

11.1.1 DC-DC Boost Layout Recommendation

Some key guidelines are listed here to be followed for the layout of the DC-DC boost in the TCA5013:

• The inductor must be placed close to the LX pin such that the trace resistance between the LX pin and the inductor terminal is as small as possible.

• The 10 µF input capacitor on VDD shall be placed close to the inductor terminal and the two shall be connected by a copper pour to minimize resistance as much as possible.

• The other terminal of the 10 µF capacitor should be connected to GNDP plane by multiple vias to provide a low resistance path to ground.

• The 100 nF capacitor should be placed as close to VDD pin as possible.

• The anode of the schottky diode shall be placed as close as possible to the inductor and shall be connected to it by a copper pour to minimize resistance as much as possible.

• The 10 µF output capacitor on VUP should have a very low resistive connection to VUP and GNDP.

11.1.2 Card Interface Layout Recommendations

The card interface layout is important for proper operation of the device and for meeting EMV4.3 electrical requirements:

• If possible two 100 nF capacitors should be connected to VCC. One near the TCA5013 and one close to the card slot.

• If only one 200 nF capacitor is used it should be placed close to the TCA5013.

• If possible the CLK trace should be routed on a separate signal layer different from the layer on which the other card interface traces (IO and RST) are routed. It is also recommended that the two signal layers be separated by a ground plane if possible.

• The GNDS, GNDUC and GND pins should be connected to the ground plane with the shortest trace possible to reduce inductance from the device ground to the ground plane. This is critical in order for the device to meet the 8 kV IEC protection level on the card interface pins.

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VUP

GNDP

VDD

GNDP

10uH

10uF

1uF

Top layer copper pour

Bottom layer copper pour

VIA to GND plane

VIA to VDD plane

VIA from top signal layer to bottom signal layer

Solder pad for device pin connection

TCA5013

SCPS253C –JANUARY 2014–REVISED SEPTEMBER 2019

11.2 Layout Example

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Figure 28. Example Layout of DC-DC Boost Section of TCA5013

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12 Device and Documentation Support

12.1 Trademarks

All trademarks are the property of their respective owners.

12.2 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

12.3 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OPTION ADDENDUM

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10-Dec-2020

PACKAGING INFORMATION

Orderable Device Status

TCA5013ZAHR ACTIVE NFBGA ZAH 48 3000 RoHS & Green SNAGCU Level-3-260C-168 HR -40 to 85 RN013

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

Package Type Package

(1)

Drawing

Pins Package

Qty

Eco Plan

(2)

Lead finish/ Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

(2)

RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3)

MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)

Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Samples

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com 24-Sep-2019

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

TCA5013ZAHR NFBGA ZAH 48 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q1

Type

Package Drawing

Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm)B0(mm)K0(mm)P1(mm)W(mm)

Pin1

Quadrant

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com 24-Sep-2019

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TCA5013ZAHR NFBGA ZAH 48 3000 336.6 336.6 31.8

Pack Materials-Page 2

PACKAGE OUTLINE

BALL A1 CORNER INDEX AREA

(0.89)

1.2 MAX

0.25 TYP

0.15

SCALE 2.500

BALL TYP

5.1

4.9

NFBGA - 1.2 mm max heightZAH0048A

PLASTIC BALL GRID ARRAY

5.1

4.9

SEATING PLANE

0.08 C

4 TYP

(0.5) TYP

SYMM

48X

0.35

0.25

0.15 C A B

0.05 C

4221741/A 10/2014

TYP

0.5 TYP

SYMM

0.5 TYP

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M.

2. This drawing is subject to change without notice.

www.ti.com

EXAMPLE BOARD LAYOUT

NFBGA - 1.2 mm max heightZAH0048A

PLASTIC BALL GRID ARRAY

(0.5) TYP

48X ( )0.25

SYMM

LAND PATTERN EXAMPLE

SCALE:15X

( )

0.25

METAL

SOLDER MASK

OPENING

NON-SOLDER MASK

DEFINED

(PREFERRED)

0.05 MAX

0.05 MIN

SOLDER MASK

DEFINED

SOLDER MASK DETAILS

NOT TO SCALE

NOTES: (continued)

3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For information, see Texas Instruments literature number SSYZ015 (www.ti.com/lit/ssyz015).

METAL UNDER SOLDER MASK

( )

0.25 SOLDER MASK OPENING

4221741/A 10/2014

www.ti.com

(0.5) TYP

48X ( 0.25)

EXAMPLE STENCIL DESIGN

NFBGA - 1.2 mm max heightZAH0048A

PLASTIC BALL GRID ARRAY

(R ) TYP0.05

(0.5) TYP

METAL

TYP

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL

SCALE:20X

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

www.ti.com

4221741/A 10/2014

IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS.

These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources.

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warranties or warranty disclaimers for TI products.

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

Texas Instruments TCA5013 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

1 Features

2 Applications

3 Description

Table of Contents

4 Revision History

5 Pin Configuration and Functions

6 Specifications

6.1 Absolute Maximum Ratings

6.2 Handling Ratings

6.3 Recommended Operating Conditions

6.4 Thermal Information

6.5 Electrical Characteristics—Power Supply and ESD

6.7 Electrical Characteristics—Card RST

6.8 Electrical Characteristics—Card CLK

6.9 Electrical Characteristics—Card Interface IO, C4 and C8

6.10 Electrical Characteristics—PRES

6.11 Electrical Characteristics—IOMC1 and IOMC2

6.12 Electrical Characteristics—CLKIN1 and CLKIN2

6.13 Electrical Characteristics—A0 and SHDN

6.14 Electrical Characteristics—INT

6.15 Electrical Characteristics—GPIO

6.16 Electrical Characteristics—SDA and SCL

6.17 Electrical Characteristics—Fault Condition Detection

6.18 I2C Interface Timing Requirements

6.19 I2C Interface Timing Characteristics

6.20 Synchronous Type 1 Card Activation Timing Characteristics

6.21 Synchronous Type 2 Card Activation Timing Characteristics

6.22 Card Deactivation Timing Characteristics

6.23 Typical Characteristics

7 Parameter Measurement Information

8 Detailed Description

8.1 Overview

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 Card Interface Modules

8.3.2 SAM Card Interface Modules

8.3.3 User Card Interface Module

8.3.4 Clock Division and Multiplexing

8.3.5 IO Multiplexing

8.3.6 GPIO Operation

8.3.7 Power Management Features

8.3.8 ESD Protection

8.3.9 I2C interface

8.4 Device Functional Modes

8.4.1 Power Off Mode

8.4.2 Shutdown Mode

8.4.3 Standby Mode

8.4.4 Active Mode

8.4.4.1 User Card Operating Mode Selection

8.4.4.2 Synchronous Type 1 Operating Mode

8.4.4.3 Synchronous Type 2 Operating Mode

8.4.4.4 Manual Operating Mode

8.4.4.5 Asynchronous Operating Mode

8.4.4.6 Warm Reset Sequence

8.4.4.7 Deactivation Sequence

8.4.5 User Card Insertion / Removal Detection

8.4.6 IO Operation

8.4.6.1 IO Switching Control

8.4.6.2 IO Rise Time and Fall Time control

8.4.6.3 Current Limiting on IO Pin

8.4.7 CLK Operation

8.4.7.1 CLK Switching

8.4.7.2 CLK Rise Time and Fall Time Control

8.4.7.3 Current Limiting On CLK Pin

8.4.8 RST Operation

8.4.8.1 Current Limiting On RST

8.4.9 Interrupt Operation

8.4.9.1 Card Insertion And Removal

8.4.9.2 Over Current Fault

8.4.9.3 Supervisor Fault

8.4.9.4 Over Temperature Fault

8.4.9.5 EARLY Fault

8.4.9.6 MUTE Fault

8.4.9.7 Synchronous Activation Complete

8.4.9.8 VCCRamp Fault

8.4.9.9 GPIO Input State Transition