Texas Instruments TCA5013 User Manual
SDA
SCL
SHDN
INT
IOMC1
CLKIN1
IOMC2
CLKIN2
VDD
LX
VUP
VDDI
PRES
VCCUC
GNDUC
IOUC
CLKUC
RSTUC
VCCS1
IOS1
CLKS1
RSTS1
VCCS3
IOS3
VCCS2
IOS2
CLKS2
RSTS2
CLKS3
RSTS3
GNDS
TCA5013
C4
C8
GNDS
GNDS
GPIO1
GPIO2
GPIO3
GPIO4
A0
TST3
TST2
TST1
V
DDI
User
Card
Slot
SAM1
Card
Slot
SAM2
Card
Slot
GNDP
GNDP
Microcontroller
10k
10k 10k
10k
100 nF
100 nF
C
VUP
=
10 µF
10k
L
VDD
=
10 µH
C
VDD
= 100
µF
200nF
200nF
200nF
LDOCAP
1 µF
TST4
GND
SAM3
Card
Slot
200nF
VDD=V
DDI
= 3.3 V
D
VUP
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TCA5013
SCPS253C –JANUARY 2014–REVISED SEPTEMBER 2019
TCA5013 Feature Rich Smartcard Interface IC with 1 User Card and 3 SAM Card Support
1 Features
1
• Operating supply voltage range of 2.7 V to 5.5 V
• Supports EMV 4.3, ISO7816-3 and ISO7816-10
standards
• Supports 1 user card and 3 secure access module
cards
• IEC61000-4-2 8-kV Contact discharge esd
protection on all smartcard interface pins
• Low power mode for power saving when inactive
(shutdown mode)
• Automatic card deactivation in the event of short
circuit, card pull out, over temperature or power
supply fault
• Integrated DC-DC boost to generate VCCfor 5 V
and 3 V on all card interfaces
• Automatic card clock generation for synchronous
card activation
• 4-byte FIFO for storing ATR from ISO7816-10
Type 1 cards
• Programmable rise/fall time control for IO and
clock lines of all smartcards
• Input clock frequency up to 26 MHz
• Tamper proof package design
2 Applications
• High-end point of sale (POS) terminals
• Multi secure accesscard capable EPOS systems
3 Description
TCA5013 is a smartcard interface IC that is targeted
for use in Point of Sale (POS) terminals. The device
enables POS terminals to interface with EMV4.3,
ISO7816-3 and ISO7816-10 compliant cards. It
supports up to 3 Secure Access Module (SAM) cards
in addition to 1 user card. It operates from a single
supply and generates all the card voltages. The
device is controlled by a standard I2C interface and is
capable of card activation and deactivation per
EMV4.3 and ISO7816-3 standards. In addition it also
supports ISO7816-10 synchronous cards. It has a 4byte FIFO that stores the ATR (Answer to Reset)
sequence in ISO7816-10 type 1 cards. Synchronous
cards (ISO7816-10 type 1 and type 2) can be set up
for automatic activation or manual activation. The
device has multiple power saving modes and also
supports power saving in the smartcard itself by
“clock stop” or lowering clock frequency to lowest
allowable levels per the ISO7816 - 3 standard.
TCA5013 has IEC 61000-4-2 8kV contact discharge
on all pins that interface with smartcards. This
enables the system to be resistant to ESD in the field
without the need for external ESD devices. It is
available in an 5 mm x 5 mm BGA package. The pin
out of the device is such that all the IO pins are
securely surrounded by other pins. This prevents the
secure pins from being probed during device
operation.
Device Information
PART NUMBER PACKAGE BODY SIZE (NOM)
TCA5013 NFBGA (48) 5.00 mm × 5.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
(1)
Simplified Schematic
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TCA5013
SCPS253C –JANUARY 2014–REVISED SEPTEMBER 2019
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Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions......................... 3
6 Specifications......................................................... 5
6.1 Absolute Maximum Ratings ...................................... 5
6.2 Handling Ratings....................................................... 5
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics—Power Supply and ESD . 6
6.6 Electrical Characteristics—Card VCC........................ 6
6.7 Electrical Characteristics—Card RST....................... 6
6.8 Electrical Characteristics—Card CLK ....................... 7
6.9 Electrical Characteristics—Card Interface IO, C4 and
C8............................................................................... 7
6.10 Electrical Characteristics—PRES ........................... 8
6.11 Electrical Characteristics—IOMC1 and IOMC2 ...... 9
6.12 Electrical Characteristics—CLKIN1 and CLKIN2.... 9
6.13 Electrical Characteristics—A0 and SHDN .............. 9
6.14 Electrical Characteristics—INT ............................... 9
6.15 Electrical Characteristics—GPIO............................ 9
6.16 Electrical Characteristics—SDA and SCL............. 10
6.17 Electrical Characteristics—Fault Condition
Detection.................................................................. 10
6.18 I2C Interface Timing Requirements....................... 10
6.19 I2C Interface Timing Characteristics ..................... 10
6.20 Synchronous Type 1 Card Activation Timing
Characteristics ......................................................... 11
6.21 Synchronous Type 2 Card Activation Timing
Characteristics ......................................................... 11
6.22 Card Deactivation Timing Characteristics............. 11
6.23 Typical Characteristics.......................................... 11
7 Parameter Measurement Information ................ 12
8 Detailed Description ............................................ 13
8.1 Overview ................................................................. 13
8.2 Functional Block Diagram....................................... 14
8.3 Feature Description................................................. 15
8.4 Device Functional Modes........................................ 17
8.5 Programming........................................................... 38
8.6 Register Maps......................................................... 41
9 Application and Implementation ........................ 55
9.1 Application Information............................................ 55
9.2 Typical Application ................................................. 55
10 Power Supply Recommendations..................... 57
10.1 Power-On-Reset ................................................... 57
11 Layout................................................................... 57
11.1 Layout Guidelines ................................................. 57
11.2 Layout Example .................................................... 58
12 Device and Documentation Support ................. 59
12.1 Trademarks........................................................... 59
12.2 Electrostatic Discharge Caution............................ 59
12.3 Glossary................................................................ 59
13 Mechanical, Packaging, and Orderable
Information........................................................... 59
4 Revision History
Changes from Revision B (January 2016) to Revision C Page
• Changed the Pin Configuration view ..................................................................................................................................... 3
• Added: (Cold reset sequence) to Figure 6 ........................................................................................................................... 22
Changes from Revision A (July 2014) to Revision B Page
• Changed the datasheet title to "TCA5013 Feature Rich Smartcard Interface IC with 1 User Card and 3 SAM Card
Support".................................................................................................................................................................................. 1
• Added the Features: Tamper proof package design.............................................................................................................. 1
• Changed the Applications ...................................................................................................................................................... 1
• Full Version release of document........................................................................................................................................... 1
Changes from Original (July 2014) to Revision A Page
• Full version release of document. ......................................................................................................................................... 1
2
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1 2 3 4 5 6 7 8 9
A
B
C
D
E
F
G
H
J
Not to scale
PRES GPIO4 GPIO3 GPIO2 GPIO1 VUP LX
C8 A0 INT SHDN SCL SDA LDOCAP TS T4 GNDP
C4 VDD
CLKUC TST3 GND CLKIN1
GNDUC IOUC IOMC1 GN D
RSTUC VCCUC IOMC2 CL KIN2
TST2 VDDI
RSTS3 IOS3 GNDS TS T1 IOS2 GNDS GNDS IOS1 VC CS1
CLKS3 VCCS3 RSTS2 CL KS2 VCCS2 RSTS1 CL KS1
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5 Pin Configuration and Functions
TCA5013
SCPS253C –JANUARY 2014 –REVISED SEPTEMBER 2019
ZAH Package
NFBGA 48-Pins
Bottom View
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TCA5013
SCPS253C –JANUARY 2014–REVISED SEPTEMBER 2019
Pin Functions
PIN
NO. NAME
A1 PRES INPUT User card presence detection
A2 GPIO4 I/O General purpose IO (5-V tolerant)
A4 GPIO3 I/O General purpose IO (5-V tolerant)
A5 GPIO2 I/O General purpose IO (5-V tolerant)
A6 GPIO1 I/O General purpose IO (5-V tolerant)
A8 VUP PWR Boost output terminal
A9 LX PWR Boost inductor input terminal
B1 C8 I/O User card auxiliary IO (Open Drain)
B2 A0 INPUT
B3 INT OUTPUT Interrupt output (open drain)
B4 SHDN INPUT Shutdown and reset pin
B5 SCL INPUT
B6 SDA I/O
B7 LDOCAP PWR Internal LDO output. Connect to 1 µf decoupling capacitor.
B8 TST4 NA Test pin. Grounded in application.
B9 GNDP PWR Power ground
C2 C4 I/O User card auxiliary IO (Open drain)
C8 VDD PWR Device main power supply
D1 CLKUC OUTPUT User card clock
D2 TST3 NA Test pin. Grounded in application.
D8 GND PWR Device ground
D9 CLKIN1 INPUT User card external clock input pin
E1 GNDUC PWR User card ground pin
E2 IOUC I/O User card IO pin
E8 IOMC1 I/O User card microcontroller data IO
E9 GND PWR Device ground
F1 RSTUC OUTPUT User card reset output pin
F2 VCCUC PWR User card VCC pin
F8 IOMC2 I/O SAM microcontroller data IO
F9 CLKIN2 INPUT User card external clock input pin
G2 TST2 NA Test pin. Grounded in application.
G8 VDDI PWR Microcontroller interface supply voltage.
H1 RSTS3 OUTPUT Reset output for SAM3
H2 IOS3 I/O IO pin for SAM3
H3 GNDS PWR Ground for all SAMs
H4 TST1 NA Test pin. Grounded in application
H5 IOS2 I/O IO pin for SAM2
H6 GNDS PWR Ground for all SAMs
H7 GNDS PWR Ground for all SAMs
H8 IOS1 I/O IO pin for SAM1
H9 VCCS1 PWR VCC for SAM1
J1 CLKS3 OUTPUT Clock output for SAM3
J2 VCCS3 PWR VCC for SAM3
J4 RSTS2 OUTPUT Reset output for SAM2
J5 CLKS2 OUTPUT Clock output for SAM2
J6 VCCS2 PWR VCC for SAM2
J8 RSTS1 OUTPUT Reset output for SAM1
J9 CLKS1 OUTPUT Clock output for SAM1
TYPE DESCRIPTION
I2C address selection pin. Connect to VDDI, GND.
I2C clock input
I2C data
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6 Specifications
TCA5013
SCPS253C –JANUARY 2014 –REVISED SEPTEMBER 2019
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)(2)
(3)
MIN MAX UNIT
V
DD
V
DDI
V
I
I
OL
Supply voltage range –0.3 6 V
Interface voltage range –0.3 4 V
V
+
Input voltage range on digital I/O pins referenced to V
Input voltage range on digital I/O pins referenced to V
DDI
CC
-0.3
-0.3
DDI
0.3
VCC+
0.3
V
V
Load current on GPIO pins -15 mA
Load current on INT and SDA pins -6 mA
(1) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(2) The package thermal impedance is calculated in accordance with JESD 51-7.
(3) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 Handling Ratings
MIN MAX UNIT
T
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Storage temperature range –65 150 °C
stg
Electrostatic discharge
(ESD)
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
(1)
pins
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins
(2)
–4 4
-1.5 1.5
kV
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
V
DD
V
DDI
I
CC(TOT)
T
A
Supply voltage range – DC-DC enabled 2.7 5.5 V
Supply voltage Range – DC-DC disabled 5.25 5.5 V
Interface voltage range 1.65 3.6 V
Sum of the currents that can be drawn on all Card VCC pins 180 mA
Operating temperature range –40 85 °C
6.4 Thermal Information
TCA5013
THERMAL METRIC
R
θJA
R
θJC(top)
R
θJB
ψ
JT
ψ
JB
Junction-to-ambient thermal resistance 96.9
Junction-to-case (top) thermal resistance 59.0
Junction-to-board thermal resistance 49.4
Junction-to-top characterization parameter 1.9
Junction-to-board characterization parameter 58.6
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(1)
UNITZAH
48 PINS
°C/W
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SCPS253C –JANUARY 2014–REVISED SEPTEMBER 2019
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6.5 Electrical Characteristics—Power Supply and ESD
VDD= V
V
DDTH
V
DDSH
V
DDITH
I
DDSH
I
DDST
I
DDA
I
DDA1
I
DDISH
I
DDIA
t
WAKE
f
OSC
f
DC-DC
V
DC-DC
V
ESD-IEC
(1) Values highly dependent on external components like boost inductor and external rectifier. The specification is based on 75% boost
= 3.3 V; L
DDI
= 10 µH; C
VDD
= 10 µF; C
VDD
= 10 µF; TA= –40°C to 85°C unless otherwise noted
VUP
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VDD supervisor fault threshold VDDvoltage below which SUPL fault is asserted 2.45 2.7 V
VDD shutdown threshold VDDvoltage below which device will shutdown 2.0 V
VDDI shutdown threshold V
VDD Shutdown current Shutdown Mode at T
VDD Standby current Shutdown Mode at T
Supply current
(1)
voltage below which device will shutdown 1.4 1.6 V
DDI
= 25 C 22 28 µA
ambient
= 25°C 300 650 µA
ambient
IOMC1 = IOMC2 = V
CLKIN1 = CLKIN2 = GND; T
Current consumption per card interface activated
V
= V
CCUC
ambient
= f
= I
= 25°C
CCS1
CLKIN2
CCS1
= 55 mA; I
f
CLKIN1
I
CCUC
T
= V
= f
DDI
CCS2
CLKUC
;
= V
= f
CCS2
ambient
CCS3
CLKS1
= I
= 25°C
= 5 V;
= 5 MHz;
= 2 mA;
CCS3
235 280 mA
VDD Interface shutdown current Shutdown Mode at 25°C 3.5 5 µA
VDD Interface supply current
All Card VCC= 5 V; CLKIN1 = CLKIN2 = 5 MHz; @ 25°C;
IOMC1 = IOMC2 = V
DDI
290 300 µA
Time from
Device wakeup time
SHDN > VIHto
INT < V
OL
0.1 10 ms
Internal Oscillator Frequency Measured on CLKUC, CLKS1,CLKS2,CLKS3 1 1.2 1.4 MHz
DC-DC switching frequency 2.4 MHz
DC-DC output voltage
IEC61000-4-2 level 4 ESD protection
on pins defined in Table 1
If any card VCCis 5 V 5.5
If all card VCCis 3 V or 1.8 V 3.5
-8 8 kV
efficiency for max value and 85% efficiency for typical value
2 mA
V
6.6 Electrical Characteristics—Card V
VDD= V
= 3.3 V; L
DDI
= 10 µH; C
VDD
= 10 µF; C
VDD
CC
VUP
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
CC
∆VCC/∆I
V
RIPPLE
I
CC
V
DO
Card supply voltage
Load transient response
CC
Current pulses I < 100 mA,
t < 400 ns
Peak to peak ripple voltage Measured on VCC= 5 V, 3 V, 1.8 V 90 mV
Card supply Current
Card LDO dropout voltage ICC= 65 mA 250 mV
6.7 Electrical Characteristics—Card RST
VDD= V
V
OL - RST
V
OH - RST
t
R - RST
t
F - RST
= 3.3 V; L
DDI
= 10 µH; C
VDD
= 10 µF; C
VDD
VUP
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Output Low voltage IOL= -200 µA 0.1 V
Output high voltage IOH= 150 µA 0.9 V
Rise time CL= 30 pF ; 10% to 90% 0.1 µs
Fall time CL= 30 pF ; 90% to 10% 0.1 µs
= 10 µF; TA= –40°C to 85°C unless otherwise noted
VCC= 5 V; ICC≤ 65 mA 4.75 5 5.25
VCC= 1.8 V; ICC≤ 45 mA 1.71 1.8 1.89
VCC= 5 V ; 40 nA.s current spike 4.65 5.35 V
VCC= 3 V ; 17.5 nA.s current spike 2.76 3.24 V
VCC= 1.8 V ; 11.1 nA.s current spike 1.62 1.98 V
VCC= 5 V 65
VCC= 1.8 V 45
= 10 µF; TA= –40°C to 85°C unless otherwise noted
CC
VVCC= 3 V; ICC≤ 65 mA 2.85 3 3.15
mAVCC= 3 V 65
CC
V
V
6
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SCPS253C –JANUARY 2014 –REVISED SEPTEMBER 2019
6.8 Electrical Characteristics—Card CLK
VDD= V
V
OL - CLK
V
OH - CLK
t
R - CLK
CLK
f
CLK
D Clock duty cycle Internal clock = 1.2 MHz; CL= 30 pF 45 55 %
DDI
/ t
F - CLK
PU-PD-SKEW
= 3.3 V; L
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
= 10 µH; C
VDD
Output Low voltage IOL= -100 µA 0.1 V
Output high voltage IOH= 100 µA 0.9 V
Rise/Fall time
Clock pull-up / pull-down skew t
Frequency on CLK pin CL= 30 pF 20 MHz
= 10 µF; C
VDD
VUP
CL= 30 pF ;
10% to 90%;
– t
R-CLK
F-CLK
= 10 µF; TA= –40°C to 85°C unless otherwise noted
CC
CLK slew rate settings register =
0000b
CLK slew rate settings register =
0001b
CLK slew rate settings register =
0010b
CLK slew rate settings register =
0011b
CLK slew rate settings register =
0100b
CLK slew rate settings register =
0101b
CLK slew rate settings register =
0110b
CLK slew rate settings register =
0111b
CLK slew rate settings register =
1000b
CLK slew rate settings register =
1001b
CLK slew rate settings register =
1010b
CLK slew rate settings register =
1011b
CLK slew rate settings register =
1100b
CLK slew rate settings register =
1101b
CLK slew rate settings register =
1110b
CLK slew rate settings register =
1111b
/ t
; CL= 30 pF 10 %
F-CLK
7
9
11
13
13.5
14
15
16
17
18
19
20
21
22
23
25
CC
V
V
ns
6.9 Electrical Characteristics—Card Interface IO, C4 and C8
VDD= V
V
OL - C4, C8
V
OH - C4, C8
V
IL - IO, C4, C8
V
IH - IO, C4, C8
V
OL - IO, 5 V
= 3.3 V; L
DDI
= 10 µH; C
VDD
= 10 µF; C
VDD
= 10 µF; TA= –40°C to 85°C unless otherwise noted
VUP
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Output Low Voltage VCC= 5 V IOL= -1 mA 0.5 V
Output Low Voltage VCC= 5 V, 3 V, 1.8 V IOH= 20 µA 0.9 V
Output Low Voltage 0.4 V
Output High Voltage 0.6 V
VCC= 5 V;
IO fall time register setting = 00b
VCC= 5 V;
Output Low Voltage
IO fall time register setting = 01b
VCC= 5 V;
IO fall time register setting = 10b
VCC= 5 V;
IO fall time register setting = 11b
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IOL= -1 mA
CC
V
V
V
CC
CC
0.5
0.5
V
0.5
0.5
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SCPS253C –JANUARY 2014–REVISED SEPTEMBER 2019
Electrical Characteristics—Card Interface IO, C4 and C8 (continued)
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VDD= V
DDI
V
OL - IO, 3 V
V
OL - IO, 3 V, 500uA
V
OL - IO, 1.8 V
V
OL - IO, 1.8 V, 500uA
t
PD - R - IOMC - IO
t
PD - F - IOMC - IO
t
FO - IO
t
RO - IO
t
RO - C4, C8
t
FO - C4, C8
t
RI - IO, C4, C8
t
FI - IO, C4, C8
C
I - IO, C4, C8
R
PU - IO, C4, C8
= 3.3 V; L
= 10 µH; C
VDD
= 10 µF; C
VDD
= 10 µF; TA= –40°C to 85°C unless otherwise noted
VUP
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Output Low Voltage
Output Low Voltage
Output Low Voltage
Output Low Voltage
Rising edge
propagation delay
Falling edge
propagation delay
IO Line output fall time
IO Line output rise time
C4, C8 Line output rise
time
C4, C8 Line output fall
time
IO, C4, C8 Input rise
time
IO, C4, C8 Input fall
time
VCC= 3 V;
IO fall time register setting = 01b
VCC= 3 V;
IO fall time register setting = 10b
IOL= -1 mA
VCC= 3 V;
IO fall time register setting = 11b
VCC= 3 V;
IO fall time register setting = 00b
VCC= 3 V;
IO fall time register setting = 01b
VCC= 3 V;
IOL= -500
µA
IO fall time register setting = 10b
VCC= 3 V;
IO fall time register setting = 11b
VCC= 1.8 V;
IO fall time register setting = 11b
IOL= -1 mA 0.18 V
VCC= 1.8 V;
IO fall time register setting = 01b
VCC= 1.8 V;
IO fall time register setting = 10b
IOL= -500
µA
VCC= 1.8 V;
IO fall time register setting = 11b
From IOMC pin to card IO; CLon card IO = 30 pF;
CLon IOMC = 30 pF; Prop delay measured from
70% V
to 70% of VCCfor rising edge
DDI
From IOMC pin to card IO; CLon card IO = 30 pF;
CLon IOMC = 30 pF; Prop delay measured from
30% V
CL= 30 pF ; 10% to 90%; IO fall time register setting
= 00b
CL= 30 pF ; 10% to 90%; IO rise time register
setting = 100b
to 30% of VCCfor falling edge;
DDI
68 ns
100 ns
CL= 30 pF ; 10% to 90% 1.2 µs
CL= 30 pF ; 90% to 10% 1.2 µs
10% to 90% 1.2 µs
90% to 10% 1.2 µs
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.18
0.18
0.18
400 ns
250 ns
Input capacitance F = 1 MHz 10 pF
Pull-up resistance IO, C4, C8 pull-up to V
CC
4.25 8.1 kΩ
V
V
V
6.10 Electrical Characteristics—PRES
VDD= V
V
IL - PRES
V
IH - PRES
I
LEAK - PRES
t
DEB(P)
t
DEB(D)
8
= 3.3 V; L
DDI
PARAMETER TEST CONDITION MIN TYP MAX UNIT
= 10 µH; C
VDD
Input Low voltage 0.3 V
Input high voltage 0.7 V
Input leakage current Voltage on pin = V
Debounce time
= 10 µF; C
VDD
Time from transition on PRES pin to PRESL bit being
set
Time from transition on PRES pin to start of
deactivation sequence (RST going low)
= 10 µF; TA= –40°C to 85°C unless otherwise noted
VUP
DDI
DDI
20 ms
100 µs
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DDI
1 µA
V
V
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6.11 Electrical Characteristics—IOMC1 and IOMC2
VDD= V
V
OL- IOMC
V
OH - IOMC
V
IL - IOMC
V
IH - IOMC
t
PD - F - IO - IOMC
t
PD - F - IO - IOMC
t
RO - IOMC
t
FO - IOMC
t
RI - IOMC
t
FI - IOMC
C
I - IOMC
R
PU - IOMC
= 3.3 V; L
DDI
= 10 µH; C
VDD
= 10 µF; C
VDD
= 10 µF; TA= –40°C to 85°C unless otherwise noted
VUP
PARAMETER TEST CONDITION MIN TYP MAX UNIT
Output low voltage IOL= -100 µA 0.2 V
Output high voltage IOH= 20 µA 0.8 V
Input low signal 0.3 V
Input high signal 0.7 V
Falling edge propagation
delay
Rising edge propagation
delay
From Card IO pin to IOMC; CLon card IO = 30 pF;
Prop delay measured from 30% VCCto 30% of V
falling edge;
From Card IO pin to IOMC; CLon card IO = 30 pF;
Prop delay measured from 70% VCCto 70% of V
rising edge;
Output rise time CL= 30 pF ; 10% to 90% 1.2 µs
Output fall time CL= 30 pF ; 90% to 10% 1.2 µs
Input rise time 10% to 90% 1.2 µs
Input fall time 90% to 10% 1.2 µs
Input capacitance 10 pF
Pull-up resistance Pull-up to V
DDI
6.12 Electrical Characteristics—CLKIN1 and CLKIN2
VDD= V
V
IL - CLKIN
V
IH - CLKIN
t
R - CLKIN
t
F - CLKIN
f
CLKIN
= 3.3 V; L
DDI
= 10 µH; C
VDD
= 10 µF; C
VDD
= 10 µF; TA= –40°C to 85°C unless otherwise noted
VUP
PARAMETER TEST CONDITION MIN TYP MAX UNIT
Input Low voltage 0.2 V
Input high voltage 0.8 V
Rise time 10% to 90% 0.1 µs
Fall time 90% to 10% 0.1 µs
Input clock frequency 26 MHz
TCA5013
SCPS253C –JANUARY 2014 –REVISED SEPTEMBER 2019
V
V
V
V
V
V
DDI
DDI
for
for
DDI
DDI
DDI
DDI
250 ns
400 ns
11 kΩ
DDI
DDI
6.13 Electrical Characteristics—A0 and SHDN
VDD= V
V
IL - A0, SHDN
V
IH - A0, SHDN
I
LEAK - A0, SHDN
C
I - A0, SHDN
R
PU - SHDN
= 3.3 V; L
DDI
= 10 µH; C
VDD
= 10 µF; C
VDD
= 10 µF; TA= –40°C to 85°C unless otherwise noted
VUP
PARAMETER TEST CONDITION MIN TYP MAX UNIT
input Low voltage 0.2 V
input high voltage 0.8 V
Input leakage current Voltage on pin = V
Input Capacitance 10 pF
Pull-up resistance on SHDN Pull-up to V
6.14 Electrical Characteristics—INT
VDD= V
I
LEAK - INT
V
OL - INT
= 3.3 V; L
DDI
= 10 µH; C
VDD
= 10 µF; C
VDD
= 10 µF; TA= –40°C to 85°C unless otherwise noted
VUP
PARAMETER TEST CONDITION MIN TYP MAX UNIT
Input leakage current Voltage on pin = V
Output low voltage IOL= -3 mA 0.2 V
6.15 Electrical Characteristics—GPIO
VDD= V
V
OL - GPIO
I
OL - GPIO
I
LEAK - GPIO
T
PD - GPIO
= 3.3 V; L
DDI
= 10 µH; C
VDD
= 10 µF; C
VDD
= 10 µF; TA= –40°C to 85°C unless otherwise noted
VUP
PARAMETER TEST CONDITION MIN TYP MAX UNIT
Output low voltage IOL= -10 mA 0.2 V
Output low current 10 mA
Input leakage current Voltage on pin = V
State transition on GPIO to INT assertion
RPUon INT= 10 k; CLon INT 20 pF;
GPIO and INT transition referenced to 0.5 V
DDI
DDI
DDI
DDI
DDI
DDI
DDI
V
V
1 µA
2.5 MΩ
1 µA
DDI
DDI
V
V
1 µA
4 µs
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6.16 Electrical Characteristics—SDA and SCL
VDD= V
I
LEAK - SDA, SCL
V
OL - SDA, SCL
I
OL - SDA, SCL
V
IL - SDA, SCL
V
IH - SDA, SCL
= 3.3 V; L
DDI
= 10 µH; C
VDD
PARAMETER TEST CONDITION MIN TYP MAX UNIT
Input leakage current Voltage on pin = V
SDA output low voltage IOL= -3 mA 0.1 V
SDA max output low current VOL= 0.3 V 10 mA
Input low signal 0.2 V
Input high signal 0.8 V
= 10 µF; C
VDD
= 10 µF; TA= –40°C to 85°C unless otherwise noted
VUP
DDI
6.17 Electrical Characteristics—Fault Condition Detection
VDD= V
T
SD
I
SD
I
LIM
= 3.3 V; L
DDI
Shutdown temperature 125 145 °C
Shutdown current On card VCC pins 160 200 260 mA
Output current limit
= 10 µH; C
VDD
PARAMETER TEST CONDITION MIN TYP MAX UNIT
= 10 µF; C
VDD
= 10 µF; TA= –40°C to 85°C unless otherwise noted
VUP
On card IO pins –15 15 mA
On card CLK pins –70 70 mA
On card RST pins –20 20 mA
DDI
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1 µA
DDI
DDI
V
V
V
6.18 I2C Interface Timing Requirements
(1)
STANDARD MODE
PARAMETER
I2C BUS
MIN MAX MIN MAX MIN MAX
f
t
t
t
t
t
t
t
t
t
t
t
t
scl
sch
scl
sp
sds
sdh
icr
icf
ocf
buf
sts
sth
sps
I2C clock frequency 100 400 1000 kHz
I2C clock high time 4 0.6 0.26 μs
I2C clock low time 4.7 1.3 0.5 μs
I2C spike time 50 50 50 ns
I2C serial data setup time 250 100 50 ns
I2C serial data hold time 0 0 0 ns
I2C input rise time 1000 300 120 ns
I2C input fall time 300 300 120 ns
I2C output fall time; 10 pF to 400 pF bus 300 300 120 μs
I2C bus free time between Stop and Start 4.7 1.3 0.5 μs
I2C Start or repeater start condition setup time 4.7 0.6 0.26 μs
I2C Start or repeater start condition hold time 4 0.6 0.26 μs
I2C Stop condition setup time 4 0.6 0.26 μs
(1) Refer to the Parameter Measurement Information section for more information.
6.19 I2C Interface Timing Characteristics
(1)
PARAMETER MIN TYP MAX UNIT
t
vd(data)
t
vd(ack)
Valid data time; SCL low to SDA output valid 450 ns
Valid data time of ACK condition; ACK signal from SCL low to SDA (out) low 450 ns
(1) Refer to Parameter Measurement Information section for more information.
FAST MODE
I2C BUS
FAST MODE PLUS
(FM+) I2C BUS
UNIT
10
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0
5
10
15
20
25
30
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
CLK Rise / Fall Time (ns)
Clock Slew Rate Settings Register Value (ns)
CLK Rise Time
CLK Fall Time
C001
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6.20 Synchronous Type 1 Card Activation Timing Characteristics
PARAMETER TEST CONDITION MIN TYP MAX UNIT
t
S1-RST-HI
t
S1-CLK-HI
t
S1-RST-CLK
t
S1-CLK-RST
t
S1-CLK-LO
t
S1-CLK-PER
t
S1-ATR-SETUP
CL= 30 pF ; VCC= 5 V; See Figure 4. 60 70 80 µs
CL= 30 pF ; VCC= 5 V; See Figure 4. 10 12.5 15 µs
CL= 30 pF ; VCC= 5 V; See Figure 4. 25 28 32 µs
CL= 30 pF ; VCC= 5 V; See Figure 4. 25 28 32 µs
CL= 30 pF ; VCC= 5 V; See Figure 4. 70 80 90 µs
CL= 30 pF ; VCC= 5 V; See Figure 4. 22.5 25 27.5 µs
CL= 30 pF ; VCC= 5 V; See Figure 4. 1 µs
Duty cycle CL= 30 pF ; VCC= 5 V; See Figure 4. 45 50 55 %
6.21 Synchronous Type 2 Card Activation Timing Characteristics
PARAMETER TEST CONDITION MIN TYP MAX UNIT
t
S2-VCC-CLK
t
S2-CLK-C4
t
S2-CLK-HI
CL= 30 pF ; VCC= 5 V; See Figure 5. 5 20 µs
CL= 30 pF ; VCC= 5 V; See Figure 5. 14 18 22 µs
CL= 30 pF ; VCC= 5 V; See Figure 5. 7 9 11 µs
6.22 Card Deactivation Timing Characteristics
PARAMETER TEST CONDITION MIN TYP MAX UNIT
t
DEAC-TOTS
t
DEAC-RST-CLK
t
DEAC-RST-IO
t
DEAC-RST-VCC
CL= 30 pF ; VCC= 5 V; See Figure 7. 0.5 0.6 ms
CL= 30 pF ; VCC= 5 V; See Figure 7. 10 12 15 µs
CL= 30 pF ; VCC= 5 V; See Figure 7. 22 24 26 µs
CL= 30 pF ; VCC= 5 V; See Figure 7. 45 µs
6.23 Typical Characteristics
Figure 1. CLK Rise/Fall Time vs Clock Slew Rate Settings Register Value
CL= 30 pF
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002aac938
t
f
70 %
30 %
SDA
t
f
70 %
30 %
S
t
r
70 %
30 %
70 %
30 %
t
SCL
HD;DAT
1 / f
1 clock cycle
SCL
st
70 %
30 %
70 %
30 %
t
r
t
cont.
VD;DAT
cont.
SDA
SCL
t
SU;STA
t
HD;STA
Sr
t
SP
t
SU;STO
t
BUF
P S
t
HIGH
9 clock
th
t
HD;STA
t
LOW
70 %
30 %
t
VD;ACK
9 clock
th
t
SU;DAT
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7 Parameter Measurement Information
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VIL= 0.3 V
VIH= 0.7 V
DDI
DDI
Figure 2. Parameter Measurement Information for I2C Timing Characteristics and Requirements
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8 Detailed Description
8.1 Overview
TCA5013 is a smartcard interface IC that enables POS terminals to interface with EMV4.3 and ISO7816-3 and
ISO7816-10 compliant smartcards. The device has 4 smartcard interfaces (1 user card and 3 SAM cards).
TCA5013 is capable of card activation and deactivation per EMV4.3, ISO7816-3 and ISO7816-10 standards.
TCA5013 has two power supply pins - VDD and VDDI. VDD is the main power supply for the device and VDDI is
the reference supply for the interface operating voltage. VDDand V
recommended operating conditions for the device to operate properly. Upon power up an internal Power-OnReset circuit initializes the digital core with all the registers in their default state as described in Register Maps.
TCA5013 can operate in various functional modes as defined in Device Functional Modes. When one of the
device power supplies is not applied, that is, VDD< V
DDSH
or V
DDI
< V
DDITH
of the device functions are available in this mode. Shutdown Mode is the lowest power operating mode in the
device. Shutdown mode is entered by asserting the SHDN = 0 when VDD> V
can detect card insertion and removal even in Shutdown mode. The device is in Standby mode when VDD>
V
DDSH
or V
DDI
> V
and the SHDN pin = 1. When any of the 4 smartcard interfaces is activated, the device
DDITH
enters active mode (see Active Mode). The user card interface module can be activated in synchronous type 1,
synchronous type 2, asynchronous or manual operation mode. For synchronous type 1 and synchronous type 2
operation modes, the device can automatically generate activation sequences per the ISO7816-10 standard (see
Synchronous Type 1 Operating Mode and Synchronous Type 2 Operating Mode). For asynchronous cards the
device performs the activation sequence and also verifies the response from the card meets the requirements
per ISO7816-3 and EMV4.3 standards (see Asynchronous Operating Mode). The device also supports WARM
reset ( see Warm Reset Sequence) and card deactivation (see Deactivation Sequence) of smartcards per the
ISO7816-3 and EMV4.3 standards. The SAM card interface modules can only be activated in aynchronous
operation mode.
All smartcard interfaces have the standard CLK, IO and RST pins (as defined by EMV4.3 and ISO7816
standards). All these pins are designed to have internal current limiting to prevent device damage when shorted.
CLK and IO pins also provide automatic level translation to the voltage at which the card has been activated.
Rrise time and fall time of the CLK and IO pins can also be controlled using digital register settings (see IO Rise
Time and Fall Time control and CLK Rise Time and Fall Time Control). In addition to the CLK, IO and RST pins
the user card interface also has PRES pin to detect card insertion and removal (see User Card Insertion /
Removal Detection). C4 and C8 pins, as defined by ISO7816-10, are also present on the user card interface (see
User Card Interface Module).
The device has internal boost and LDOs to generate the card activation voltage depending on the operating
voltage required by the specific card being interfaced with. It also has a voltage supervisor that monitors VDDand
V
and responds as described in Interrupt Operation . The power management section is described in more
DDI
detail in Power Management.
In addition to these functions the device provides 8kV IEC 61000-4-2 ESD protection on all pins that interface to
smartcards. This removes the need for any external ESD protection on the board, thereby providing system
robustness without compromising system security (removable components on secure lines).
TCA5013 is configured using a standard I2C interface that is capable of up to 1 MHz operation. The I2C interface
is also used to read the status of various fault conditions that the device can detect. The I2C operation is
described in detail in I2C Interface Operation.
need to ramped to within the
DDI
the device is in Power Off Mode. None
DDSH
and V
DDI
> V
. The device
DDITH
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User Card Interface
Module
Card VCCLDO
IO level translator
CLK level translator
RST level translator
C4&C8 buffers
PRES detection logic
SAM 1 Interface Module
Card VCCLDO
IO level translator
CLK level translator
RST level translator
SAM 3 Interface Module
Card VCCLDO
IO level translator
CLK level translator
RST level translator
SAM 2 Interface Module
Card VCCLDO
IO level translator
CLK level translator
RST level translator
Boost
LDO
Oscillator
User card
clock divider
SAM clock
divider and
multiplexer
SAM card
Digital core
and register map
I2C
interface
RSTUC
C4
C8
PRES
VCCUC
IOUC
CLKUC
VCCS1
IOS1
CLKS1
VCCS2
IOS2
CLKS2
VCCS3
IOS3
CLKS3
RSTS1
RSTS2
RSTS3
VUPLX
VDD
LDOCAP
IOMC1
IOMC2
CLKIN1
CLKIN2
SCL
SDA
INT
SHDN
A0
GPIO1 GPIO2 GPIO3 GPIO4
VDDI
GNDUC
GNDS
GNDS
GNDS
GNDP
GNDP
GNDP
TST1 TST2 TST3 TST 4
User card IO
multiplexer
Voltage
supervisor
IO multiplexer
and multiplexer
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8.2 Functional Block Diagram
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8.3 Feature Description
8.3.1 Card Interface Modules
TCA5013 has 1 user card interface module and 3 SAM card interface modules. All card modules have level
translators and an LDO to support interfacing with smartcards operating at different voltages.
8.3.2 SAM Card Interface Modules
All SAM card interface modules can operate per the EMV4.3 and ISO7816-3 standard and support asynchronous
operating mode. All SAM card interface modules have the standard IO, CLK and RST pins. Detailed operation of
these pins is described in section IO operation, CLK operation and RST operation.
8.3.3 User Card Interface Module
User card interface module can also operate per the EMV4.3 and ISO7816-3 standard and support
asynchronous operating mode. In addition, the user card interface module also supports synchronous type 1
operating mode and synchronous type 2 operating mode, per ISO7816-10. Like the SAM card interface modules,
the user card interface module also has IO, CLK, and RST pins. The user card interface module also has a
PRES pin that is used for detection of user card insertion or removal.
C4 and C8 are two pins that are only present on the user card interface. These are open drain bi-directional IOs
that are controlled by the bit [5] and bit [4] of user card synchronous mode settings register (Reg 0x09) when the
card interface is activated. These bits act as both control and status bits for the C4 and C8 signals. If a ‘0’ is
written to either of these bits the corresponding pin is driven low by the TCA5013. However, when a ‘1’ is written
to the register bit, the corresponding pin is pulled up by an internal pull-up resistor. In this state an external
device can drive the pin low. If the pin is driven low, then the corresponding bit in the register changes to reflect
the status of the pin.
8.3.4 Clock Division and Multiplexing
TCA5013 card interface modules all have a CLK pin that provide a clock signal that is used for smartcard
operation. This clock signal is generated based on an internal oscillator or from the CLKIN1/CLKIN2 input clock
signals, by the clock divider and multiplexer circuitry. The user card has a dedicated clock divider and
multiplexer. The user card CLK output can be a configured to be a function of the CLKIN1 frequency or the
internal oscillator frequency. CLKIN2 is shared by all the SAM card interface modules. The CLK output of each
SAM card can be independently configured based on the CLKIN2 frequency or the internal oscillator frequency.
CLK operation section describes the clock division and multiplexing in detail.
8.3.5 IO Multiplexing
IOMC1 and IOMC2 are connected to the IO pins in the card interface modules through IO multiplexer blocks.
The user card IO module has a dedicated IO multiplexer, that can be connect or disconnect IOUC from the
IOMC1 pin. The IOMC2 is connected to the SAM card interface modules IO pins through the SAM IO multiplexer
block. The IOMC2 can only be connected to one of the SAM interface modules at any given time. IO operation
section describes IO multiplexing in detail.
8.3.6 GPIO Operation
The TCA5013 has four 5 V tolerant open drain GPIO pins that can be configured as inputs or outputs through
device settings register (Reg 0x42). If configured as outputs, each is capable of sinking up to 10mA of current. If
configured as inputs they will assert the INT line when a state change occurs on the pin. The minimum pulse
width for transition detection is 10 µs, that is, when a state transition occurs on a GPIO configured as an input, it
needs to hold its state for a minimum of 10 µs in order to guarantee detection by the TCA5013. This, however,
does not imply any glitch rejection on the GPIO pins. The GPIOs are available in Standby Mode and Active
Mode. GPIO state transitions are not tracked in shutdown mode.
8.3.7 Power Management Features
TCA5013 has a DC-DC boost and card LDOs that enable it to generate regulated smart card VCCfrom its input
power rails (VDDand V
devices also have a voltage supervisor that monitors the VDDand V
). It also has an internal LDO that is used to power its internal circuits. The TCA5013
DDI
rails to ensure they are stable and usable
DDI
for smartcard operation.
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Feature Description (continued)
8.3.8 ESD Protection
All the smart card interface pins in the TCA5013 devices are designed with in built IEC61000-4-2 level 4 8kV
contact ESD protection. Table 1 shows a list of pins with the 8kV ESD protection. The pins not listed below all
have 4kV HBM ESD protection.
Table 1. List of Pins with 8kV IEC ESD Protection
PIN SYMBOL TYPE DESCRIPTION
A1 PRES INPUT User card presence detection
B1 C8 IO User card auxiliary IO (Open Drain)
C2 C4 IO User card auxiliary IO (Open Drain)
D1 CLKUC OUTPUT User card clock
E2 IOUC IO User card IO
F1 RSTUC OUTPUT User card RST
F2 VCCUC PWR User card VCC
H1 VCCUC OUTPUT SAM3 RST
H2 IOS3 IO SAM3 IO
H5 IOS2 IO SAM2 IO
H8 IOS1 IO SAM1 IO
H9 VCCS1 PWR SAM1 VCC
J1 CLKS3 OUTPUT SAM3 CLK
J2 VCCS3 PWR SAM3 VCC
J4 RSTS2 OUTPUT SAM2 RST
J5 CLKS2 OUTPUT SAM2 CLK
J6 VCCS2 PWR SAM2 VCC
J8 RSTS1 OUTPUT SAM1 RST
J9 CLKS1 OUTPUT SAM1 CLK
8.3.9 I2C interface
The device has a standard I2C interface that is used to configure the device and to read the status of the device.
For detailed I2C operation refer to I2C Interface Operation.
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Power off mode
Shutdown mode
Standby mode
Active mode
Power on
Reset
VCC Check
Assert INT
Deactivate all
card slots
VDD > V
DDSH
V
DDI
> V
DDITH
SHDN = 0
SHDN = 1
State change
on PRES pin
VDD < V
DDSH
or
V
DDI
< V
DDITH
SHDN = 0
VDD > V
DDSH
V
DDI
> V
DDITH
SHDN = 1
VDD < V
DDSH
or
V
DDI
< V
DDITH
Card
activation
command
VCC fail
VCC
active
Over current card
removal or
deactivation
command
Other cards
still active
Deactivate all
card slots
VDD < V
DDTH
Or over
temperature
No other
card slot
active
Deactivate all
card slots
SHDN = 0
Deactivate all
card slots
V
DDI
< V
DDITH
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8.4 Device Functional Modes
At any given time the TCA5013 can be in one of several different functional modes. Figure 3 diagram shows the
different functional modes and describes how the device transitions from one mode to another. The blue bubbles
represent actual functional modes and the white bubbles represent transitional states that are used to move from
one functional mode to another.
Figure 3. Device Operating Modes
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Device Functional Modes (continued)
8.4.1 Power Off Mode
The TCA5013 is in power off mode when VDD< V
features are functional and available for use.
8.4.2 Shutdown Mode
TCA5013 is in shutdown mode when all the below conditions are true.
• VDD> V
• V
DDI
> V
DDSH
DDITH
• SHDN = 0
Shutdown mode is a low power mode where all circuits except card insertion detection circuitry are shutdown.
Even I2C communication is disabled in shutdown mode. The only active circuit in the device is card insertion
detection circuit on the PRES pin (see User Card Insertion / Removal Detection). Shutdown mode is entered
from Active Mode or Standby Mode by asserting the SHDN pin. When entering shutdown mode from Active
Mode all active card interfaces are automatically deactivated.
8.4.3 Standby Mode
The TCA5013 is in standby mode when all the below conditions are true.
• VDD> V
• V
DDI
> V
DDSH
DDITH
• SHDN = 1
• No card interfaces are activated.
In standby mode, the device I2C and card detection circuits are fully functional. All other circuits are ready to be
activated based on I2C commands received from the microcontroller. Standby mode is entered from shutdown
mode by releasing the SHDN pin or from power down mode by powering up the device or from active mode by
deactivating all card interfaces.
DDSH
or V
DDI
< V
. In power off mode none of the device
DDITH
8.4.4 Active Mode
The TCA5013 is in active mode when all the below conditions are true.
• VDD> V
• V
DDI
> V
DDSH
DDITH
• SHDN = 1
• At least one card interface is activated
In active mode, the device is fully functional with at least one of the card interfaces activated. The DC-DC
Boost and card LDOs are active and provide power to the card VCC pins of the active card interfaces. Active
mode can only be entered from standby mode by activating one of the card interfaces. When the device is in
active mode, the individual card interfaces can be active in different operating modes. The user card supports
Asynchronous Operating Mode, Synchronous Type 1 Operating Mode,Synchronous Type 2 Operating Mode,
or Manual Operating Mode. The SAM card interfaces can only be activated in asynchronous activation mode.
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RSTUC
CLKUC
IOUC
Bit 1 to Bit 30 of
ATR response
INT
32 Clock cycles (4 Bytes)
t
S1-RST-HI
S1-CLK-HI
t
S1-RST-CLK
t
S1-CLK-RST
t
S1-CLK-LO
t
S1-CLK-PER
VCCUC
All High levels refer to 0 .9 Vcc
All Low levels refer to 0 .1 Vcc
t = t < 0 .5 μs
Bit 0
t
S1-ATR-SETUP
t
S1-ATR-SETUP
Bit 31
C 4
C 8
t
F
R
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Device Functional Modes (continued)
8.4.4.1 User Card Operating Mode Selection
The user card interface in the TCA5013 can be activated in different operating modes. When the
START_ASYNC bit (bit [0]; Reg 0x01) is set the user card interface is activated in asynchronous operating mode.
When START_SYNC bit (bit[0]; Reg 0x09) is set the user card interface is activated in synchronous type1,
synchronous type 2 or manual operating mode. When the START_SYNC bit is set, the operating mode is
determined by the ACTIVATION_TYPE bit (bit [6]; Reg 0x09) and CARD_TYPE bit (bit [7] Reg 0x09).
If ACTIVATION_TYPE bit (bit [6]; Reg 0x09) is set to ‘0’, the user card interface is activated in manual operating
mode. If the ACTIVATION_TYPE bit is set to’1’, the user card interface is set for automatic activation, where it
will be activated in synchronous type 1 or synchronous type 2 operating mode based on CARD_TYPE bit (bit [7]
Reg 0x09). If CARD_TYPE bit is set to ‘1’, the card interface is activated in synchronous type 2 operating mode.
If CARD_TYPE bit is set to ‘0’ the card interface is activated in synchronous type 1 operating mode.
Any changes made to the START_SYNC, START_ASYNC, CARD_TYPE or ACTIVATION_TYPE bits when the
user card interface is active, will be ignored and will have no effect on the device. These new settings will take
effect only on the next card interface activation following deactivation (see Deactivation Sequence).
8.4.4.2 Synchronous Type 1 Operating Mode
Synchronous type 1 operating mode is only supported on the user card interface. To enter synchronous
operating mode, the user card interface goes through the synchronous type 1 activation sequence. Figure 4
shows the synchronous type 1 activation sequence.
CLKIN1 shall be low before the synchronous type 1 activation sequence is initiated. The following bit settings are
required to initiate a synchronous type 1 activation sequence.
• ACTIVATION_TYPE (bit [6]; Reg 0x09) = 1
• CARD_TYPE (bit [7]; Reg 0x09) = 0
• START_SYNC (bit [0]; Reg 0x09) = 1
Figure 4. Synchronous Type 1 Activation Sequence
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Device Functional Modes (continued)
Once synchronous type 1 activation has been initiated, the following sequence of events occurs on the user card
interface:
• VCCUC, RSTUC, CLKUC, C4, C8 and IOUC are all default low.
• VCCis applied to the VCCUC pin per the SET_VCC_UC bit (bit[7:6]; Reg 0x01).
• After VCCis stable RSTUC and CLKUC pulses are applied per t
S1-RST-HI
• After VCCis stable, the IOUC line is pulled up to VCC.
• After VCCis stable C4 and C8 reflect the value in their corresponding I2C register bits (bit[5] and bit[4]; Reg
0x09).
• RSTUC is held low while the CLKUC line starts oscillating with a frequency of ~40Khz (generated from
internal oscillator).
• The IO line is sampled on the 32 rising or falling (based on bit[1]; Reg 0x09) edges of CLK and stored in the
FIFO registers 0AH to 0DH.
• At the end of the 32nd CLK pulse, the CLKUC is held low and the CLKUC pin is controlled by the clock
settings register (Reg 0x02).
• IOUC is connected to IOMC1 if IO_EN_UC bit (bit[5] Reg 0x01) is set to 1.
• INT_SYNC_COMPLETE bit (Bit[1]; REG 0x41) is set and the INT line is asserted low.
• IOMC1 shall stay pulled up to V
i.e. IOMC1 shall not be pulled low until INT is asserted.
DDI
• CLKIN1 shall toggle only after INT is asserted.
• RSTUC is controllable by I2C after INT is asserted.
and t
S1-CLK-HI
defined in Table 2.
Table 2. Synchronous Type 1 Card Activation Timing Characteristics
MIN TYP MAX UNIT
t
S1-RST-HI
t
S1-CLK-HI
t
S1-RST-CLK
t
S1-CLK-RST
t
S1-CLK-LO
t
S1-CLK-PER
Duty cycle 45 50 55 %
60 70 80 µs
10 12.5 15 µs
25 28 32 µs
25 28 32 µs
70 80 90 µs
22.5 25 27.5 µs
8.4.4.3 Synchronous Type 2 Operating Mode
Synchronous type 2 operating mode is only supported on the user card interface. To enter synchronous
operating mode, the user card interface goes through the synchronous type 2 activation sequence. Figure 5
shows the synchronous type 2 activation sequence.
CLKIN1 shall be low before the synchronous type 2 activation sequence is initiated. The following bit settings are
required to initiate a synchronous type 1 activation sequence.
• ACTIVATION_TYPE (bit [6]; Reg 0x09) = 1
• CARD_TYPE (bit [7]; Reg 0x09) = 1
• START_SYNC (bit [0]; Reg 0x09) = 1
20
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