Texas Instruments SN74ACT3631-15PCB, SN74ACT3631-15PQ, SN74ACT3631-20PCB, SN74ACT3631-20PQ, SN74ACT3631-30PCB Datasheet
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SN74ACT3631
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS246G – AUGUST 1993 – REVISED APRIL 1998
D
Free-Running CLKA and CLKB Can Be
Asynchronous or Coincident
D
Clocked FIFO Buffering Data From Port A
to Port B
D
Synchronous Read-Retransmit Capability
D
Mailbox Register in Each Direction
D
Programmable Almost-Full and
Almost-Empty Flags
D
Microprocessor Interface Control Logic
D
Input-Ready and Almost-Full Flags
Synchronized by CLKA
description
The SN74ACT3631 is a high-speed, low-power, CMOS clocked FIFO memory. It supports clock frequencies
up to 67 MHz and has read access times as fast as 1 1 ns. The 512 × 36 dual-port SRAM FIFO buffers data from
port A to port B. The FIFO memory has retransmit capability , which allows previously read data to be accessed
again. The FIFO has flags to indicate empty and full conditions and two programmable flags (almost full and
almost empty) to indicate when a selected number of words is stored in memory . Communication between each
port can take place with two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail
has been stored. Two or more devices can be used in parallel to create wider datapaths. Expansion also is
possible in word depth.
D
Output-Ready and Almost-Empty Flags
Synchronized by CLKB
D
Low-Power 0.8-µm Advanced CMOS
Technology
D
Supports Clock Frequencies up to 67 MHz
D
Fast Access Times of 11 ns
D
Pin-to-Pin Compatible With the
SN74ACT3641 and SN74ACT3651
D
Package Options Include 120-Pin Thin
Quad Flat (PCB) and 132-Pin Plastic Quad
Flat (PQ) Packages
512 × 36
The SN74ACT3631 is a clocked FIFO, which means each port employs a synchronous interface. All data
transfers through a port are gated to the low-to-high transition of a continuous (free-running) port clock by enable
signals. The continuous clocks for each port are independent of one another and can be asynchronous or
coincident. The enables for each port are arranged to provide a simple interface between microprocessors
and/or buses with synchronous control.
The input-ready (IR) flag and almost-full (AF
output-ready (OR) flag and almost-empty (AE
values for the AF and AE flags of the FIFO can be programmed from port A or through a serial input.
The SN74ACT3631 is characterized for operation from 0°C to 70°C.
For more information on this device family, see the following application reports:
D
FIFO Patented Synchronous Retransmit: Programmable DSP-Interface Application for FIR Filtering
(literature number SCAA007)
D
FIFO Mailbox-Bypass Registers: Using Bypass Registers to Initialize DMA Control
SCAA007)
D
Metastability Performance of Clocked FIFOs (literature number SCZA004).
) flag of the FIFO are two-stage synchronized to CLKA. The
) flag of the FIFO are two-stage synchronized to CLKB. Offset
(literature number
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1998, Texas Instruments Incorporated
1
SN74ACT3631
512 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS246G – AUGUST 1993 – REVISED APRIL 1998
PCB PACKAGE
(TOP VIEW)
A35
A34
A33
A32
V
CC
A31
A30
GND
A29
A28
A27
A26
A25
A24
A23
GND
A22
V
CC
A21
A20
A19
A18
GND
A17
A16
A15
A14
A13
V
CC
A12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
GND
CLKA
119
120
32
31
ENA
W/RA
117
118
33
CSAIROR
116
35
34
115
36
114
37
V
113
38
CC
CC
MBF2
V
110
41
MBAAFGND
108
109
43
42
AE
111
112
40
39
RST
107
44
FS0/SD
105
106
46
45
FS1/SEN
104
47
RTM
103
48
V
RFM
101
102
49
50
CC
NC
100
51
GND
MBB
98
99
53
52
MBF1
CSB
GND
96
97
95
54
5556575859
W/RB
94
ENB
CLKB
92
93
CC
V
91
60
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
B35
B34
B33
B32
GND
B31
B30
B29
B28
B27
B26
V
CC
B25
B24
GND
B23
B22
B21
B20
B19
B18
GND
B17
B16
V
CC
B15
B14
B13
B12
GND
A9
A8
A7
A1 1
A10
GND
NC – No internal connection
2
A6
A4
A5
A3
GND
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
V
CC
A2
A1
A0
B0
GND
B1
B2
B3
B4
B5
B6
GND
V
CC
B7
B8
B9
B10
B1 1
†
SN74ACT3631
512 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS246G – AUGUST 1993 – REVISED APRIL 1998
PQ PACKAGE
(TOP VIEW)
NC
B35
B34
B33
B32
GND
B31
B30
B29
B28
B27
B26
V
CC
B25
B24
GND
B23
B22
B21
B20
B19
B18
GND
B17
B16
V
CC
B15
B14
B13
B12
GND
NC
NC
CC
NCNCV
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
CLKB
5251 83828180797877767574737271706968676665646362616059585756555453
ENB
CSB
W/RB
GND
MBF1
GND
MBB
NC
V
CC
RFM
RTM
FS1/SEN
1
FS0/SD
GND
RST
132
131
130
MBA
129
CC
V
MBF2AEAF
126
128
127
125
CC
V
124
ORIRCSA
122
121
123
W/RA
ENA
120
119
CLKA
GND
118
117
NC
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
NC
NC
A35
A34
A33
A32
V
CC
A31
A30
GND
A29
A28
A27
A26
A25
A24
A23
GND
A22
V
CC
A21
A20
A19
A18
GND
A17
A16
A15
A14
A13
V
CC
A12
NC
B1 1
B9B8B7
B10
NC
NC – No internal connection
†
Uses Yamaichi socket IC51-1324-828
V
CC
B6
B5B4B3B2B1
GND
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
B0
A0A1A2
GND
CC
A3A4A5
V
A6A7A8
GND
A9
A10
A1 1
NC
GND
NC
3
SN74ACT3631
512 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS246G – AUGUST 1993 – REVISED APRIL 1998
functional block diagram
CLKA
CSA
W/RA
ENA
MBA
RST
Port-A
Control
Logic
Reset
Logic
Input Register
MBF1
Mail1
Register
512 × 36
SRAM
Output Register
A0–A35
AF
FS0/SD
FS1/SEN
MBF2
36
Logic
Synch
Write
Pointer
IR
10
Status-Flag
Flag-Offset
Register
Register
Read
Pointer
Logic
Mail2
Retransmit
Port-B
Control
Logic
RTM
RFM
B0–B35
OR
AE
CLKB
CSB
W/RB
ENB
MBB
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT3631
512 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS246G – AUGUST 1993 – REVISED APRIL 1998
Terminal Functions
TERMINAL
NAME
A0–A35 I/O Port-A data. The 36-bit bidirectional data port for side A.
AE O
AF O
B0–B35 I/O Port-B data. The 36-bit bidirectional data port for side B.
CLKA I
CLKB I
CSA I
CSB I
ENA I Port-A master enable. ENA must be high to enable a low-to-high transition of CLKA to read or write data on port A.
ENB I Port-B master enable. ENB must be high to enable a low-to-high transition of CLKB to read or write data on port B.
FS1/SEN,
FS0/SD
IR O
MBA I Port-A mailbox select. A high level on MBA chooses a mailbox register for a port-A read or write operation.
MBB I
MBF1 O
MBF2 O
OR O
RFM I
RST I
RTM I
I/O DESCRIPTION
Almost-empty flag. Programmable flag synchronized to CLKB. AE is low when the number of words in the FIFO is less
than or equal to the value in the almost-empty offset register (X).
Almost-full flag. Programmable flag synchronized to CLKA. AF is low when the number of empty locations in the FIFO
is less than or equal to the value in the almost-full offset register (Y).
Port-A clock. CLKA is a continuous clock that synchronizes all data transfers through port A and can be asynchronous
or coincident to CLKB. IR and AF
Port-B clock. CLKB is a continuous clock that synchronizes all data transfers through port B and can be asynchronous
or coincident to CLKA. OR and AE
Port-A chip select. CSA must be low to enable a low-to-high transition of CLKA to read or write data on port A. The
A0–A35 outputs are in the high-impedance state when CSA
Port-B chip select. CSB must be low to enable a low-to-high transition of CLKB to read or write data on port B. The
B0–B35 outputs are in the high-impedance state when CSB
Flag offset select 1/serial enable, flag offset select 0/serial data. FS1/SEN and FS0/SD are dual-purpose inputs used
for flag offset register programming. During a device reset, FS1/SEN
method. Three offset register programming methods are available: automatically load one of two preset values, parallel
load from port A, and serial load.
I
When serial load is selected for flag offset register programming, FS1/SEN
low-to-high transition of CLKA. When FS1/SEN
X- and Y -offset registers. The number of bit writes required to program the offset register is 18. The first bit write stores
the Y-register MSB and the last bit write stores the X-register LSB.
Input-ready flag. IR is synchronized to the low-to-high transition of CLKA. When IR is low, the FIFO is full and writes
to its array are disabled. When the FIFO is in retransmit mode, IR indicates when the memory has been filled to the
point of the retransmit data and prevents further writes. IR is set low during reset and is set high after reset.
Port-B mailbox select. A high level on MBB chooses a mailbox register for a port-B read or write operation. When the
B0–B35 outputs are active, a high level on MBB selects data from the mail1 register for output and a low level selects
FIFO data for output.
Mail1 register flag. MBF1 is set low by the low-to-high transition of CLKA that writes data to the mail1 register . MBF1
is set high by a low-to-high transition of CLKB when a port-B read is selected and MBB is high. MBF1 is set high by
a reset.
Mail2 register flag. MBF2 is set low by the low-to-high transition of CLKB that writes data to the mail2 register . MBF2
is set high by a low-to-high transition of CLKA when a port-A read is selected and MBA is high. MBF2 is set high by
a reset.
Output-ready flag. OR is synchronized to the low-to-high transition of CLKB. When OR is low, the FIFO is empty and
reads are disabled. Ready data is present in the output register of the FIFO when OR is high. OR is forced low during
the reset and goes high on the third low-to-high transition of CLKB after a word is loaded to empty memory.
Read from mark. When the FIFO is in retransmit mode, a high on RFM enables a low-to-high transition of CLKB to reset
the read pointer to the beginning retransmit location and output the first selected retransmit data.
Reset. To reset the device, four low-to-high transitions of CLKA and four low-to-high transitions of CLKB must occur
while RST
Retransmit mode. When RTM is high and valid data is present in the FIFO output register (OR is high), a low-to-high
transition of CLKB selects the data for the beginning of a retransmit and puts the FIFO in retransmit mode. The selected
word remains the initial retransmit point until a low-to-high transition of CLKB occurs while RTM is low , taking the FIFO
out of retransmit mode.
is low. The low-to-high transition of RST latches the status of FS0 and FS1 for AF and AE offset selection.
are synchronous to the low-to-high transition of CLKA.
are synchronous to the low-to-high transition of CLKB.
is high.
is high.
and FS0/SD select the flag offset programming
is used as an enable synchronous to the
is low, a rising edge on CLKA loads the bit present on FS0/SD into the
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
SN74ACT3631
512 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS246G – AUGUST 1993 – REVISED APRIL 1998
Terminal Functions (Continued)
TERMINAL
NAME
W/RA I
W/RB I
I/O DESCRIPTION
Port-A write/read select. A high on W/RA selects a write operation and a low selects a read operation on port A for a
low-to-high transition of CLKA. The A0–A35 outputs are in the high-impedance state when W/R
Port-B write/read select. A low on W/RB selects a write operation and a high selects a read operation on port B for a
low-to-high transition of CLKB. The B0–B35 outputs are in the high-impedance state when W
A is high.
/RB is low.
detailed description
reset
The SN74ACT3631 is reset by taking the reset (RST
port-B clock (CLKB) low-to-high transitions. The reset input can switch asynchronously to the clocks. A reset
initializes the memory read and write pointers and forces the input-ready (IR) flag low, the output-ready (OR)
flag high, the almost-empty (AE
the mailbox flags (MBF1
, MBF2) high. After a FIFO is reset, its input-ready flag is set high after at least two clock
) flag low, and the almost-full (AF) flag high. Resetting the device also forces
cycles to begin normal operation. A FIFO must be reset after power up before data is written to its memory.
almost-empty flag and almost-full flag offset programming
Two registers in the SN74ACT3631 are used to hold the of fset values for the almost-empty and almost-full flags.
The almost-empty (AE
) flag offset register is labeled X, and the almost-full (AF) flag of fset register is labeled Y.
The offset registers can be loaded with a value in three ways: one of two preset values is loaded into the offset
registers, parallel load from port A, or serial load. The offset register programming mode is chosen by the flag
select (FS1, FS0) inputs during a low-to-high transition on the RST
) input low for at least four port-A clock (CLKA) and four
input (see Table 1).
Table 1. Flag Programming
FS1 FS0 RST
H H ↑ Serial load
H L ↑ 64
L H ↑ 8
L L ↑ Parallel load from port A
†
X register holds the offset for AE
offset for AF
.
X AND Y REGISTERS
; Y register holds the
†
preset values
If a preset value of 8 or 64 is chosen by FS1 and FS0 at the time of a RST low-to-high transition according to
Table 1, the preset value is automatically loaded into the X and Y registers. No other device initialization is
necessary to begin normal operation, and the IR flag is set high after two low-to-high transitions on CLKA.
parallel load from port A
To program the X and Y registers from port A, the device is reset with FS0 and FS1 low during the low-to-high
transition of RST
. After this reset is complete, the IR flag is set high after two low-to-high transitions on CLKA.
The first two writes to the FIFO do not store data in its memory but load the offset registers in the order Y, X.
Each offset register of the SN74ACT3631 uses port-A inputs (A8 –A0). The highest number input is used as
the most-significant bit of the binary number in each case. Each register value can be programmed from 1 to
508. After both offset registers are programmed from port A, subsequent FIFO writes store data in the SRAM.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT3631
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS246G – AUGUST 1993 – REVISED APRIL 1998
serial load
To serially program the X and Y registers, the device is reset with FS0/SD and FS1/SEN high during the
low-to-high transition of RST
FS0/SD on each low-to-high transition of CLKA that FS1/SEN
the programming. The first bit write stores the most-significant bit of the Y register, and the last bit write stores
the least-significant bit of the X register. Each register value can be programmed from 1 to 508.
When the option to program the offset registers serially is chosen, the input-ready (IR) flag remains low until
all register bits are written. The IR flag is set high by the low-to-high transition of CLKA after the last bit is loaded
to allow normal FIFO operation.
FIFO write/read operation
. After this reset is complete, the X- and Y -register values are loaded bitwise through
is low. W rites of 18 bits are needed to complete
512 × 36
The state of the port-A data (A0 –A35) outputs is controlled by the port-A chip select (CSA
write/read select (W/R
high. The A0–A35 outputs are active when both CSA
A). The A0–A35 outputs are in the high-impedance state when either CSA or W/RA is
and W/RA are low.
Data is loaded into the FIFO from the A0–A35 inputs on a low-to-high transition of CLKA when CSA
port-A mailbox select (MBA) are low, W/R
A, the port-A enable (ENA), and the input-ready (IR) flag are high
) and the port-A
and the
(see Table 2). Writes to the FIFO are independent of any concurrent FIFO reads.
Table 2. Port-A Enable Function Table
CSA W/RA ENA MBA CLKA
H X X X X In high-impedance state None
L H L X X In high-impedance state None
L H H L ↑ In high-impedance state FIFO write
L H H H ↑ In high-impedance state Mail1 write
L L L L X Active, mail2 register None
L L H L ↑ Active, mail2 register None
L L L H X Active, mail2 register None
L L H H ↑ Active, mail2 register Mail2 read (set MBF2 high)
A0–A35 OUTPUTS PORT FUNCTION
The port-B control signals are identical to those of port A, with the exception that the port-B write/read select
(W
/RB) is the inverse of the port-A write/read select (W/RA). The state of the port-B data (B0–B35) outputs is
controlled by the port-B chip select (CSB
in the high-impedance state when either CSB
) and the port-B write/read select (W/RB). The B0–B35 outputs are
is high or W/RB is low. The B0–B35 outputs are active when CSB
is low and W/RB is high.
Data is read from the FIFO to its output register on a low-to-high transition of CLKB when CSB
mailbox select (MBB) are low, W
/RB, the port-B enable (ENB), and the output-ready (OR) flag are high
(see Table 3). Reads from the FIFO are independent of any concurrent FIFO writes.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
and the port-B
7
SN74ACT3631
FIFO
†‡
512 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS246G – AUGUST 1993 – REVISED APRIL 1998
FIFO write/read operation (continued)
Table 3. Port-B Enable Function Table
CSB W/RB ENB MBB CLKB
H X X X X In high-impedance state None
L L L X X In high-impedance state None
L L H L ↑ In high-impedance state None
L L H H ↑ In high-impedance state Mail2 write
L H L L X Active, FIFO output register None
L H H L ↑ Active, FIFO output register FIFO read
L H L H X Active, mail1 register None
L H H H ↑ Active, mail1 register Mail1 read (set MBF1 high)
B0–B35 OUTPUTS PORT FUNCTION
The setup- and hold-time constraints to the port clocks for the port-chip selects and write/read selects are only
for enabling write and read operations and are not related to high-impedance control of the data outputs. If a
port enable is low during a clock cycle, the port-chip select and write/read select can change states during the
setup- and hold-time window of the cycle.
When the output-ready (OR) flag is low, the next data word is sent to the FIFO output register automatically by
the CLKB low-to-high transition that sets the output-ready flag high. When OR is high, an available data word
is clocked to the FIFO output register only when a FIFO read is selected by the port-B chip select (CSB
write/read select (W
/RB), enable (ENB), and mailbox select (MBB).
synchronized FIFO flags
Each FIFO flag is synchronized to its port clock through at least two flip-flop stages. This is done to improve the
flags’ reliability by reducing the probability of metastable events on their outputs when CLKA and CLKB operate
asynchronously to one another .
OR and AE are synchronized to CLKB. IR and AF are synchronized to CLKA.
Table 4 shows the relationship of each flag to the number of words stored in memory.
),
Table 4. FIFO Flag Operation
NUMBER OF WORDS IN
0 L L H H
1 to X H LHH
(X + 1) to [512 – (Y + 1)] H HHH
(512 – Y) to 511 H HLH
512 H H L L
†
X is the almost-empty offset for AE. Y is the almost-full offset for AF.
‡
When a word is present in the FIFO output register, its previous memory
location is free.
SYNCHRONIZED
TO CLKB
OR AE AF IR
SYNCHRONIZED
TO CLKA
8
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