Texas Instruments SN74ACT241DBLE, SN74ACT241DBR, SN74ACT241DW, SN74ACT241DWR, SN74ACT241N Datasheet

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SN54ACT241, SN74ACT241
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCAS516B – JUNE 1995 – REVISED MA Y 1996
D
D
EPIC
(Enhanced-Performance Implanted
CMOS) 1-µm Process
D
Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), and DIP (N) Packages, Ceramic Chip Carriers (FK), Flat (W), and DIP (J) Packages
description
These octal buffers and line drivers are designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.
The ’ACT241 are organized as two 4-bit buffers/drivers with separate complementary output-enable (1OE is low or 2OE is high, the device passes noninverted data from the A inputs to the Y outputs. When 1OE outputs are in the high-impedance state.
The SN54ACT241 is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74ACT241 is characterized for operation from –40°C to 85°C.
and 2OE) inputs. When 1OE
is high or 2OE is low, the
SN74ACT241 . . . DB, DW, N, OR PW PACKAGE
FUNCTION TABLES
INPUTS
1OE 1A
L H H L LL
H X Z
OUTPUT
1Y
SN54ACT241 ...J OR W PACKAGE
(TOP VIEW)
1OE
1
1A1
2
2Y4
3
1A2
4
2Y3
5
1A3
6
2Y2
7 8
1A4
9
2Y1
GND
SN54ACT241 . . . FK PACKAGE
1A2 2Y3 1A3 2Y2 1A4
10
(TOP VIEW)
2Y4
1A1
3 2 1 20 19
4 5 6 7 8
9 10 11 12 13
2Y1
GND
20 19 18 17 16 15 14 13 12 11
V
1OE
2A1
CC
1Y4
V
CC
2OE 1Y1 2A4 1Y2 2A3 1Y3 2A2 1Y4 2A1
18 17 16 15 14
2A2 2OE
1Y1 2A4 1Y2 2A3 1Y3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
INPUTS
2OE 2A
H H H H LL
L X Z
OUTPUT
2Y
Copyright 1996, Texas Instruments Incorporated
1
SN54ACT241, SN74ACT241 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SCAS516B – JUNE 1995 – REVISED MA Y 1996
logic symbol
1OE
1A1 1A2 1A3 1A4
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
1
2 4 6 8
EN
18 16 14 12
1Y1 1Y2 1Y3 1Y4
2OE
2A1 2A2 2A3 2A4
logic diagram (positive logic)
1
1OE
1A1
1A2
1A3
2
4
6
18
16
14
1Y1
1Y2
1Y3
2OE
2A1
2A2
2A3
11 13 15 17
19
19
11
13
15
EN
9
2Y1
7
2Y2
5
2Y3
3
2Y4
9
2Y1
7
2Y2
5
2Y3
1A4
8
12
1Y4
2A4
17
3
2Y4
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0 or VI > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
Continuous current through VCC or GND ±200 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum power dissipation at TA = 55°C (in still air) (see Note 2):DB package 0.6 W. . . . . . . . . . . . . . . . . . .
Storage temperature range, T
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils, except for the N package, which has a trace length of zero.
(VO = 0 to VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
D package 1.6 W. . . . . . . . . . . . . . . . . . . .
N package 1.3 W. . . . . . . . . . . . . . . . . . . .
PW package 0.7 W. . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
UNIT
PARAMETER
TEST CONDITIONS
V
UNIT
I
A
V
V
I
A
V
I
mA
V
SN54ACT241, SN74ACT241
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCAS516B – JUNE 1995 – REVISED MA Y 1996
recommended operating conditions (see Note 3)
SN54ACT241 SN74ACT241
MIN MAX MIN MAX
V V V V V I
OH
I
OL
t/v Input transition rise or fall rate 0 8 0 8 ns/V T
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
Not more than one output should be tested at a time, and the duration of the test should not exceed 2 ms.
This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
Supply voltage 4.5 5.5 4.5 5.5 V
CC
High-level input voltage 2 2 V
IH
Low-level input voltage 0.8 0.8 V
IL
Input voltage 0 V
I
Output voltage 0 V
O
High-level output current –24 –24 mA Low-level output current 24 24 mA
Operating free-air temperature –55 125 –40 85 °C
A
TA = 25°C SN54ACT241 SN74ACT241
MIN TYP MAX MIN MAX MIN MAX
I I I
I C
C
OH
OL
OZ I CC
i o
CC
CC
= –50 µ
OH
IOL = –24 mA IOH = –50 mA
IOH = –75 mA
= 50 µ
OL
= 24
OL
IOL = 50 mA IOL = 75 mA VO = VCC or GND 5.5 V ±0.25 ±5 ±2.5 µA VI = VCC or GND 5.5 V ±0.1 ±1 ±1 µA VI = VCC or GND, IO = 0 5.5 V 4 80 40 µA One input at 3.4 V ,
Other inputs at GND or V VI = VCC or GND 5 V 2.5 pF VI = VCC or GND 5 V 8 pF
† †
† †
CC
4.5 V 4.4 4.49 4.4 4.4
5.5 V 5.4 5.49 5.4 5.4
4.5 V 3.86 3.7 3.76
5.5 V 4.86 4.7 4.76
5.5 V 3.85
5.5 V 3.85
4.5 V 0.001 0.1 0.1 0.1
5.5 V 0.001 0.1 0.1 0.1
4.5 V 0.36 0.5 0.44
5.5 V 0.36 0.5 0.44
5.5 V 1.65
5.5 V 1.65
5.5 V 0.6 1.6 1.5 mA
CC CC
0 V 0 V
CC CC
V V
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
3
SN54ACT241, SN74ACT241
PARAMETER
UNIT
A
Y
ns
OE
OE
Y
ns
OE
OE
Y
ns
OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
SCAS516B – JUNE 1995 – REVISED MA Y 1996
switching characteristics over recommended operating free-air temperature range,
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
V
CC
FROM TO
(INPUT) (OUTPUT)
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
or
or
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
C
Power dissipation capacitance per buffer/driver CL = 50 pF, f = 1 MHz 45 pF
pd
PARAMETER MEASUREMENT INFORMATION
TA = 25°C SN54ACT241 SN74ACT241
MIN TYP MAX MIN MAX MIN MAX
1.5 6 8.5 1 9.5 1.5 9.5
1.5 5.5 7.5 1 9 1.5 8.5
1.5 7 8.5 1 10 1 9.5 2 7 9.5 1 11.5 1.5 10.5 2 8 9.5 1 11 2 10.5
2.5 6.5 10 1 11.5 2 10.5
500
50% V
500
CC
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
Input
t
PLH
Output
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one input transition per measurement.
1.5 V 1.5 V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
S1
t
PHL
50% V
0 V
V
CC
V
2 × V
Open
3 V
OH
OL
CC
Control
(low-level
enabling)
Waveform 1
S1 at 2 × V
(see Note B)
Waveform 2
S1 at Open
(see Note B)
Output
Output
CC
Output
t
PZL
t
PZH
TEST S1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
t
PLZ
50% V
CC
t
PHZ
50% V
CC
Open
2 × V
Open
1.5 V1.5 V
CC
VOL + 0.3 V
VOH – 0.3 V
3 V
0 V
[
V
V
[
V
OL
OH
0 V
CC
4
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
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Copyright 1998, Texas Instruments Incorporated
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