Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), Thin Shrink Small-Outline (PW), and
DIP (N) Packages, Ceramic Chip Carriers
(FK), Flat (W), and DIP (J) Packages
description
These octal buffers and line drivers are designed
specifically to improve the performance and
density of 3-state memory address drivers, clock
drivers, and bus-oriented receivers and
transmitters.
The ’ACT241 are organized as two 4-bit
buffers/drivers with separate complementary
output-enable (1OE
is low or 2OE is high, the device passes
noninverted data from the A inputs to the
Y outputs. When 1OE
outputs are in the high-impedance state.
The SN54ACT241 is characterized for operation
over the full military temperature range of –55°C
to 125°C. The SN74ACT241 is characterized for
operation from –40°C to 85°C.
and 2OE) inputs. When 1OE
is high or 2OE is low, the
SN74ACT241 . . . DB, DW, N, OR PW PACKAGE
FUNCTION TABLES
INPUTS
1OE1A
LHH
LLL
HXZ
OUTPUT
1Y
SN54ACT241 ...J OR W PACKAGE
(TOP VIEW)
1OE
1
1A1
2
2Y4
3
1A2
4
2Y3
5
1A3
6
2Y2
7
8
1A4
9
2Y1
GND
SN54ACT241 . . . FK PACKAGE
1A2
2Y3
1A3
2Y2
1A4
10
(TOP VIEW)
2Y4
1A1
3 2 1 20 19
4
5
6
7
8
9 10 11 12 13
2Y1
GND
20
19
18
17
16
15
14
13
12
11
V
1OE
2A1
CC
1Y4
V
CC
2OE
1Y1
2A4
1Y2
2A3
1Y3
2A2
1Y4
2A1
18
17
16
15
14
2A22OE
1Y1
2A4
1Y2
2A3
1Y3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
INPUTS
2OE2A
HHH
HLL
LXZ
OUTPUT
2Y
Copyright 1996, Texas Instruments Incorporated
1
SN54ACT241, SN74ACT241
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCAS516B – JUNE 1995 – REVISED MA Y 1996
logic symbol
1OE
1A1
1A2
1A3
1A4
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
†
1
2
4
6
8
EN
18
16
14
12
1Y1
1Y2
1Y3
1Y4
2OE
2A1
2A2
2A3
2A4
logic diagram (positive logic)
1
1OE
1A1
1A2
1A3
2
4
6
18
16
14
1Y1
1Y2
1Y3
2OE
2A1
2A2
2A3
11
13
15
17
19
19
11
13
15
EN
9
2Y1
7
2Y2
5
2Y3
3
2Y4
9
2Y1
7
2Y2
5
2Y3
1A4
8
12
1Y4
2A4
17
3
2Y4
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Maximum power dissipation at TA = 55°C (in still air) (see Note 2):DB package 0.6 W. . . . . . . . . . . . . . . . . . .
Storage temperature range, T
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils,
except for the N package, which has a trace length of zero.
IOL = 50 mA
IOL = 75 mA
VO = VCC or GND5.5 V±0.25±5±2.5µA
VI = VCC or GND5.5 V±0.1±1±1µA
VI = VCC or GND,IO = 05.5 V48040µA
One input at 3.4 V ,
‡
Other inputs at GND or V
VI = VCC or GND5 V2.5pF
VI = VCC or GND5 V8pF
†
†
†
†
CC
4.5 V4.44.494.44.4
5.5 V5.45.495.45.4
4.5 V3.863.73.76
5.5 V4.864.74.76
5.5 V3.85
5.5 V3.85
4.5 V0.0010.10.10.1
5.5 V0.0010.10.10.1
4.5 V0.360.50.44
5.5 V0.360.50.44
5.5 V1.65
5.5 V1.65
5.5 V0.61.61.5mA
CC
CC
0V
0V
CC
CC
V
V
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN54ACT241, SN74ACT241
PARAMETER
UNIT
A
Y
ns
OE
OE
Y
ns
OE
OE
Y
ns
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCAS516B – JUNE 1995 – REVISED MA Y 1996
switching characteristics over recommended operating free-air temperature range,
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
V
CC
FROMTO
(INPUT)(OUTPUT)
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
or
or
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETERTEST CONDITIONSTYPUNIT
C
Power dissipation capacitance per buffer/driverCL = 50 pF,f = 1 MHz45pF
pd
PARAMETER MEASUREMENT INFORMATION
TA = 25°CSN54ACT241SN74ACT241
MINTYPMAXMINMAXMINMAX
1.568.519.51.59.5
1.55.57.5191.58.5
1.578.511019.5
279.5111.51.510.5
289.5111210.5
2.56.510111.5210.5
500 Ω
50% V
500 Ω
CC
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
Input
t
PLH
Output
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one input transition per measurement.
1.5 V1.5 V
VOLTAGE WAVEFORMSVOLTAGE WAVEFORMS
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
S1
t
PHL
50% V
0 V
V
CC
V
2 × V
Open
3 V
OH
OL
CC
Control
(low-level
enabling)
Waveform 1
S1 at 2 × V
(see Note B)
Waveform 2
S1 at Open
(see Note B)
Output
Output
CC
Output
t
PZL
t
PZH
TESTS1
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
t
PLZ
50% V
CC
t
PHZ
50% V
CC
Open
2 × V
Open
1.5 V1.5 V
CC
VOL + 0.3 V
VOH – 0.3 V
3 V
0 V
[
V
V
[
V
OL
OH
0 V
CC
4
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICA TIONS USING SEMICONDUCT OR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
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