Texas Instruments SN74ABTH18504APM, SN74ABTH182504APM Datasheet
D
Members of the Texas Instruments
SCOPE
D
Members of the Texas Instruments
Widebus
D
Compatible With the IEEE Standard
SN54ABTH18504A, SN54ABTH182504A, SN74ABTH18504A, SN74ABTH182504A
Family of Testability Products
Family
1149.1-1990 (JTAG) Test Access Port and
Boundary-Scan Architecture
D
UBT
(Universal Bus Transceiver)
Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, or Clocked Mode
D
Bus Hold on Data Inputs Eliminates the
Need for External Pullup Resistors
D
B-Port Outputs of ’ABTH182504A Devices
Have Equivalent 25-Ω Series Resistors, So
No External Resistors Are Required
D
State-of-the-Art
EPIC-ΙΙB
BiCMOS Design
SN54ABTH18504A, SN54ABTH182504A . . . HV PACKAGE
(TOP VIEW)
SCAN TEST DEVICES WITH
20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS165C – AUGUST 1993 – REVISED JUL Y 1996
D
One Boundary-Scan Cell Per I/O
Architecture Improves Scan Efficiency
D
SCOPE
– IEEE Standard 1149.1-1990 Required
– Parallel-Signature Analysis at Inputs
– Pseudo-Random Pattern Generation
– Sample Inputs/Toggle Outputs
– Binary Count From Outputs
– Device Identification
– Even-Parity Opcodes
D
Packaged in 64-Pin Plastic Thin Quad Flat
(PM) Packages Using 0.5-mm
Center-to-Center Spacings and 68-Pin
Ceramic Quad Flat (HV) Packages Using
25-mil Center-to-Center Spacings
Instruction Set
Instructions and Optional CLAMP and
HIGHZ
From Outputs
CC
A3A2A1
10
A4
11
A5
12
A6
A7
A8
A9
A10
NC
CC
A11
A12
A13
A14
A15
A16
13
14
15
16
17
18
19
20
21
22
23
24
25
26
28 29 30 31 32 33 34
A17
GND
V
GND
NC – No internal connection
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
GND
OEBA
87 65493168672
A19
GND
A20
A18
VNCTMS
LEBA
TDO
35 36 37 38 39
TDI
CLKAB
CLKENAB
NC
CLKBA
CLKENBA
B1
66 652764 63 62 61
CC
V
TCK
LEAB
OEAB
40 41 42 43
B3
GNDB2B4
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
B20
B19
GND
B18
B5
B6
B7
GND
B8
B9
B10
V
CC
NC
B11
B12
B13
B14
GND
B15
B16
B17
SCOPE, Widebus, UBT, and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1996, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
1
SN54ABTH18504A, SN54ABTH182504A, SN74ABTH18504A, SN74ABTH182504A
SCAN TEST DEVICES WITH
20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS165C – AUGUST 1993 – REVISED JUL Y 1996
A4
A5
A6
GND
A7
A8
A9
A10
V
CC
A11
A12
A13
GND
A14
A15
A16
SN74ABTH18504A, SN74ABTH182504A . . . PM PACKAGE
A1
A2
GND
20
A3
63 62 61 60 5964 58 56 55 5457
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
18 19
(TOP VIEW)
LEBA
TDO
OEBA
21 22 23 24
CC
V
CLKENBAB1B2
TMS
CLKBA
53 521751 50 49
25 26 27 28 29
GND
30 31 32
B3
B4
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
B5
B6
B7
GND
B8
B9
B10
V
CC
B11
B12
B13
B14
GND
B15
B16
B17
CC
A17
A18
A19
GND
A20
TDI
CLKAB
B20
B19
V
TCK
LEAB
OEAB
GND
B18
CLKENAB
description
The ’ABTH18504A and ’ABTH182504A scan test devices with 20-bit universal bus transceivers are members
of the Texas Instruments SCOPE testability integrated-circuit family. This family of devices supports IEEE
Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to
the test circuitry is accomplished via the 4-wire test access port (TAP) interface.
In the normal mode, these devices are 20-bit universal bus transceivers that combine D-type latches and D-type
flip-flops to allow data flow in transparent, latched, or clocked modes. The test circuitry can be activated by the
TAP to take snapshot samples of the data appearing at the device pins or to perform a self test on the
boundary-test cells. Activating the TAP in the normal mode does not affect the functional operation of the
SCOPE universal bus transceivers.
Data flow in each direction is controlled by output-enable (OEAB
clock-enable (CLKENAB and CLKENBA), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the
device operates in the transparent mode when LEAB is high. When LEAB is low, the A-bus data is latched while
CLKENAB is high and/or CLKAB is held at a static low or high logic level. Otherwise, if LEAB is low and
CLKENAB is low , A-bus data is stored on a low-to-high transition of CLKAB. When OEAB is low , the B outputs
are active. When OEAB
is high, the B outputs are in the high-impedance state. B-to-A data flow is similar to
A-to-B data flow, but uses the OEBA, LEBA, CLKENBA, and CLKBA inputs.
In the test mode, the normal operation of the SCOPE universal bus transceivers is inhibited, and the test
circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry
performs boundary-scan test operations according to the protocol described in IEEE Standard 1149.1-1990.
and OEBA), latch-enable (LEAB and LEBA),
2
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SN54ABTH18504A, SN54ABTH182504A, SN74ABTH18504A, SN74ABTH182504A
SCAN TEST DEVICES WITH
20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS165C – AUGUST 1993 – REVISED JUL Y 1996
description (continued)
Four dedicated test pins observe and control the operation of the test circuitry: test data input (TDI), test data
output (TDO), test mode select (TMS), and test clock (TCK). Additionally , the test circuitry performs other testing
functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation
(PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.
Improved scan efficiency is accomplished through the adoption of a one boundary-scan cell (BSC) per I/O pin
architecture. This architecture is implemented in such a way as to capture the most pertinent test data. A
PSA/COUNT instruction also is included to ease the testing of memories and other circuits where a binary count
addressing scheme is useful.
Active bus-hold circuitry holds unused or floating data inputs at a valid logic level.
The B-port outputs of ’ABTH182504A, which are designed to source or sink up to 12 mA, include 25-Ω series
resistors to reduce overshoot and undershoot.
The SN54ABTH18504A and SN54ABTH182504A are characterized for operation over the full military
temperature range of –55°C to 125°C. The SN74ABTH18504A and SN74ABTH182504A are characterized for
operation from –40°C to 85°C.
FUNCTION TABLE
(normal mode, each register)
INPUTS
OEAB LEAB CLKENAB CLKAB A
L L L L X B
L LL ↑ LL
L LL ↑ HH
L LH XXB
L HX XLL
L HX XHH
H X X X X Z
†
A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA,
LEBA, CLKENBA
‡
Output level before the indicated steady-state input conditions were
established
, and CLKBA.
†
OUTPUT
B
‡
0
‡
0
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN54ABTH18504A, SN54ABTH182504A, SN74ABTH18504A, SN74ABTH182504A
SCAN TEST DEVICES WITH
20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS165C – AUGUST 1993 – REVISED JUL Y 1996
functional block diagram
Boundary-Scan Register
CLKENAB
LEAB
CLKAB
OEAB
CLKENBA
LEBA
CLKBA
OEBA
A1
22
27
23
28
54
59
55
60
62
V
CC
V
CC
C1
1D
C1
1D
C1
1D
C1
1D
53
B1
V
CC
24
TDI
V
CC
56
TMS
TAP
26
TCK
Pin numbers shown are for the PM package.
Controller
1 of 20 Channels
Bypass Register
Boundary-Control
Register
Identification
Register
Instruction
Register
58
TDO
4
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SN54ABTH18504A, SN54ABTH182504A, SN74ABTH18504A, SN74ABTH182504A
20-BIT UNIVERSAL BUS TRANSCEIVERS
Terminal Functions
TERMINAL NAME DESCRIPTION
A1–A20 Normal-function A-bus I/O ports. See function table for normal-mode logic.
B1–B20 Normal-function B-bus I/O ports. See function table for normal-mode logic.
CLKAB, CLKBA Normal-function clock inputs. See function table for normal-mode logic.
CLKENAB, CLKENBA Normal-function clock enables. See function table for normal-mode logic.
GND Ground
LEAB, LEBA Normal-function latch enables. See function table for normal-mode logic.
OEAB, OEBA
TCK
TDI
TDO
TMS
V
CC
Normal-function output enables. See function table for normal-mode logic. An internal pullup at each terminal
forces the terminal to a high level if left unconnected.
Test clock. One of four terminals required by IEEE Standard 1149.1-1990. Test operations of the device are
synchronous to TCK. Data is captured on the rising edge of TCK and outputs change on the falling edge of TCK.
Test data input. One of four terminals required by IEEE Standard 1149.1-1990. TDI is the serial input for shifting
data through the instruction register or selected data register. An internal pullup forces TDI to a high level if left
unconnected.
T est data output. One of four terminals required by IEEE Standard 1149.1-1990. TDO is the serial output for shifting
data through the instruction register or selected data register.
T est mode select. One of four terminals required by IEEE Standard 1149.1-1990. TMS directs the device through
its TAP controller states. An internal pullup forces TMS to a high level if left unconnected.
Supply voltage
SCAN TEST DEVICES WITH
SCBS165C – AUGUST 1993 – REVISED JUL Y 1996
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
SN54ABTH18504A, SN54ABTH182504A, SN74ABTH18504A, SN74ABTH182504A
SCAN TEST DEVICES WITH
20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS165C – AUGUST 1993 – REVISED JUL Y 1996
test architecture
Serial-test information is conveyed by means of a 4-wire test bus or TAP that conforms to IEEE Standard
1 149.1-1990. All test instructions, test data, and test control signals are passed along this serial-test bus. The
TAP controller monitors two signals from the test bus, TCK and TMS. The TAP controller extracts the
synchronization (TCK) and state control (TMS) signals from the test bus and generates the appropriate on-chip
control signals for the test structures in the device. Figure 1 shows the TAP-controller state diagram.
The T AP controller is fully synchronous to the TCK signal. Input data is captured on the rising edge of TCK and
output data changes on the falling edge of TCK. This scheme ensures that data to be captured is valid for fully
one-half of the TCK cycle.
The functional block diagram shows the IEEE Standard 1149.1-1990 4-wire test bus and boundary-scan
architecture and the relationship among the test bus, the T AP controller, and the test registers. As shown, the
device contains an 8-bit instruction register and four test-data registers: a 48-bit boundary-scan register, a 3-bit
boundary-control register, a 1-bit bypass register, and a 32-bit device-identification register.
Test-Logic-Reset
TMS = H
TMS = L
TMS = L
Run-Test/Idle Select-DR-Scan
TMS = L
Capture-DR
TMS = L
Shift-DR
TMS = L
TMS = H
TMS = H
Exit1-DR
TMS = L
Pause-DR
TMS = L
TMS = H
Exit2-DR
TMS = H
TMS = HTMS = H
TMS = H TMS = H
TMS = L
TMS = L
Select-IR-Scan
TMS = H
TMS = L
Capture-IR
TMS = L
Shift-IR
TMS = L
TMS = H
TMS = H
Exit1-IR
TMS = L
Pause-IR
TMS = L
TMS = H
Exit2-IR
TMS = H
Update-DR
TMS = LTMS = H
Update-IR
TMS = LTMS = H
Figure 1. TAP-Controller State Diagram
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABTH18504A, SN54ABTH182504A, SN74ABTH18504A, SN74ABTH182504A
SCAN TEST DEVICES WITH
20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS165C – AUGUST 1993 – REVISED JUL Y 1996
state diagram description
The T AP controller is a synchronous finite state machine that provides test control signals throughout the device.
The state diagram shown in Figure 1 is in accordance with IEEE Standard 1149.1-1990. The TAP controller
proceeds through its states based on the level of TMS at the rising edge of TCK.
As shown, the T AP controller consists of 16 states. There are six stable states (indicated by a looping arrow in
the state diagram) and ten unstable states. A stable state is a state the T AP controller can retain for consecutive
TCK cycles. Any state that does not meet this criterion is an unstable state.
There are two main paths through the state diagram: one to access and control the selected data register and
one to access and control the instruction register. Only one register can be accessed at a time.
Test-Logic-Reset
The device powers up in the T est-Logic-Reset state. In the stable Test-Logic-Reset state, the test logic is reset
and is disabled so that the normal logic function of the device is performed. The instruction register is reset to
an opcode that selects the optional IDCODE instruction, if supported, or the BYP ASS instruction. Certain data
registers also can be reset to their power-up values.
The state machine is constructed such that the T AP controller returns to the Test-Logic-Reset state in no more
than five TCK cycles if TMS is left high. TMS has an internal pullup resistor that forces it high if left unconnected
or if a board defect causes it to be open circuited.
For the ’ABTH18504A and ’ABTH182504A, the instruction register is reset to the binary value 10000001, which
selects the IDCODE instruction. Bits 47–46 in the boundary-scan register are reset to logic 1, ensuring that
these cells, which control A-port and B-port outputs, are set to benign values (i.e., if test mode were invoked
the outputs would be at high-impedance state). Reset values of other bits in the boundary-scan register should
be considered indeterminate. The boundary-control register is reset to the binary value 010, which selects the
PSA test operation.
Run-Test/Idle
The T AP controller must pass through the Run-T est/Idle state (from T est-Logic-Reset) before executing any test
operations. The Run-Test/Idle state also can be entered following data-register or instruction-register scans.
Run-Test/Idle is a stable state in which the test logic can be actively running a test or can be idle. The test
operations selected by the boundary-control register are performed while the TAP controller is in the
Run-Test/Idle state.
Select-DR-Scan, Select-lR-Scan
No specific function is performed in the Select-DR-Scan and Select-lR-Scan states, and the T AP controller exits
either of these states on the next TCK cycle. These states allow the selection of either data-register scan or
instruction-register scan.
Capture-DR
When a data-register scan is selected, the TAP controller must pass through the Capture-DR state. In the
Capture-DR state, the selected data register can capture a data value as specified by the current instruction.
Such capture operations occur on the rising edge of TCK, upon which the TAP controller exits the
Capture-DR state.
Shift-DR
Upon entry to the Shift-DR state, the data register is placed in the scan path between TDI and TDO, and on the
first falling edge of TCK, TDO goes from the high-impedance state to an active state. TDO enables to the logic
level present in the least-significant bit of the selected data register.
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7
SN54ABTH18504A, SN54ABTH182504A, SN74ABTH18504A, SN74ABTH182504A
SCAN TEST DEVICES WITH
20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS165C – AUGUST 1993 – REVISED JUL Y 1996
Shift-DR (continued)
While in the stable Shift-DR state, data is serially shifted through the selected data register on each TCK cycle.
The first shift occurs on the first rising edge of TCK after entry to the Shift-DR state (i.e., no shifting occurs during
the TCK cycle in which the T AP controller changes from Capture-DR to Shift-DR or from Exit2-DR to Shift-DR).
The last shift occurs on the rising edge of TCK, upon which the TAP controller exits the Shift-DR state.
Exit1-DR, Exit2-DR
The Exit1-DR and Exit2-DR states are temporary states that end a data-register scan. It is possible to return
to the Shift-DR state from either Exit1-DR or Exit2-DR without recapturing the data register. On the first falling
edge of TCK after entry to Exit1-DR, TDO goes from the active state to the high-impedance state.
Pause-DR
No specific function is performed in the stable Pause-DR state, in which the TAP controller can remain
indefinitely . The Pause-DR state can suspend and resume data-register scan operations without loss of data.
Update-DR
If the current instruction calls for the selected data register to be updated with current data, such update occurs
on the falling edge of TCK, following entry to the Update-DR state.
Capture-IR
When an instruction-register scan is selected, the TAP controller must pass through the Capture-IR state. In
the Capture-IR state, the instruction register captures its current status value. This capture operation occurs
on the rising edge of TCK, upon which the T AP controller exits the Capture-IR state. For the ’ABTH18504A and
’ABTH182504A, the status value loaded in the Capture-IR state is the fixed binary value 10000001.
Shift-IR
Upon entry to the Shift-IR state, the instruction register is placed in the scan path between TDI and TDO, and
on the first falling edge of TCK, TDO goes from the high-impedance state to an active state. TDO enables to
the logic level present in the least-significant bit of the instruction register.
While in the stable Shift-IR state, instruction data is serially shifted through the instruction register on each TCK
cycle. The first shift occurs on the first rising edge of TCK after entry to the Shift-IR state (i.e., no shifting occurs
during the TCK cycle, in which the TAP controller changes from Capture-IR to Shift-IR or from Exit2-IR to
Shift-IR). The last shift occurs on the rising edge of TCK, upon which the T AP controller exits the Shift-IR state.
Exit1-IR, Exit2-IR
The Exit1-IR and Exit2-IR states are temporary states that end an instruction-register scan. It is possible to
return to the Shift-IR state from either Exit1-IR or Exit2-IR without recapturing the instruction register. On the
first falling edge of TCK after entry to Exit1-IR, TDO goes from the active state to the high-impedance state.
Pause-IR
No specific function is performed in the stable Pause-IR state, in which the TAP controller can remain
indefinitely. The Pause-IR state can suspend and resume instruction-register scan operations without loss
of data.
Update-IR
The current instruction is updated and takes effect on the falling edge of TCK, following entry to the
Update-IR state.
8
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SN54ABTH18504A, SN54ABTH182504A, SN74ABTH18504A, SN74ABTH182504A
SCAN TEST DEVICES WITH
20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS165C – AUGUST 1993 – REVISED JUL Y 1996
register overview
With the exception of the bypass and device-identification registers, any test register can be thought of as a
serial shift register with a shadow latch on each bit. The bypass and device-identification registers differ in that
they contain only a shift register. During the appropriate capture state (Capture-IR for instruction register,
Capture-DR for data registers), the shift register can be parallel loaded from a source specified by the current
instruction. During the appropriate shift state (Shift-IR or Shift-DR), the contents of the shift register are shifted
out from TDO while new contents are shifted in at TDI. During the appropriate update state (Update-IR or
Update-DR), the shadow latches are updated from the shift register.
instruction register description
The instruction register (IR) is eight bits long and tells the device what instruction is to be executed. Information
contained in the instruction includes the mode of operation (either normal mode, in which the device performs
its normal logic function, or test mode, in which the normal logic function is inhibited or altered), the test operation
to be performed, which of the four data registers is to be selected for inclusion in the scan path during
data-register scans, and the source of data to be captured into the selected data register during Capture-DR.
Table 3 lists the instructions supported by the ’ABTH18504A and ’ABTH182504A. The even-parity feature
specified for SCOPE devices is supported in these devices. Bit 7 of the instruction opcode is the parity bit.
Any instructions that are defined for SCOPE devices but are not supported by these devices default to
BYPASS.
During Capture-IR, the IR captures the binary value 10000001. As an instruction is shifted in, this value is shifted
out via TDO and can be inspected as verification that the IR is in the scan path. During Update-IR, the value
that has been shifted into the IR is loaded into shadow latches. At this time, the current instruction is updated
and any specified mode change takes effect. At power up or in the Test-Logic-Reset state, the IR is reset to the
binary value 10000001, which selects the IDCODE instruction. The IR order of scan is shown in Figure 2.
Bit 7
Parity
(MSB)
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Bit 0
(LSB)
TDOTDI
Figure 2. Instruction Register Order of Scan
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SN54ABTH18504A, SN54ABTH182504A, SN74ABTH18504A, SN74ABTH182504A
SCAN TEST DEVICES WITH
20-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS165C – AUGUST 1993 – REVISED JUL Y 1996
data register description
boundary-scan register
The boundary-scan register (BSR) is 48 bits long. It contains one boundary-scan cell (BSC) for each
normal-function input pin and one BSC for each normal-function I/O pin (one single cell for both input data and
output data). The BSR is used 1) to store test data that is to be applied externally to the device output pins,
and/or 2) to capture data that appears internally at the outputs of the normal on-chip logic and/or externally at
the device input pins.
The source of data to be captured into the BSR during Capture-DR is determined by the current instruction. The
contents of the BSR can change during Run-Test/Idle as determined by the current instruction. At power up or
in T est-Logic-Reset, BSCs 47–46 are reset to logic 1, ensuring that these cells, which control A-port and B-port
outputs, are set to benign values (i.e., if test mode were invoked, the outputs would be at high-impedance state).
Reset values of other BSCs should be considered indeterminate.
The BSR order of scan is from TDI through bits 47–0 to TDO. T able 1 shows the BSR bits and their associated
device pin signals.
Table 1. Boundary-Scan Register Configuration
BSR BIT
NUMBER
47 OEAB 39 A20-I/O 19 B20-I/O
46 OEBA 38 A19-I/O 18 B19-I/O
45 CLKAB 37 A18-I/O 17 B18-I/O
44 CLKBA 36 A17-I/O 16 B17-I/O
43 CLKENAB 35 A16-I/O 15 B16-I/O
42 CLKENBA 34 A15-I/O 14 B15-I/O
41 LEAB 33 A14-I/O 13 B14-I/O
40 LEBA 32 A13-I/O 12 B13-I/O
–– –– 31 A12-I/O 11 B12-I/O
–– –– 30 A11-I/O 10 B11-I/O
–– –– 29 A10-I/O 9 B10-I/O
–– –– 28 A9-I/O 8 B9-I/O
–– –– 27 A8-I/O 7 B8-I/O
–– –– 26 A7-I/O 6 B7-I/O
–– –– 25 A6-I/O 5 B6-I/O
–– –– 24 A5-I/O 4 B5-I/O
–– –– 23 A4-I/O 3 B4-I/O
–– –– 22 A3-I/O 2 B3-I/O
–– –– 21 A2-I/O 1 B2-I/O
–– –– 20 A1-I/O 0 B1-I/O
DEVICE
SIGNAL
BSR BIT
NUMBER
DEVICE
SIGNAL
BSR BIT
NUMBER
DEVICE
SIGNAL
10
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SCBS165C – AUGUST 1993 – REVISED JUL Y 1996
boundary-control register
The boundary-control register (BCR) is three bits long. The BCR is used in the context of the boundary-run
(RUNT) instruction to implement additional test operations not included in the basic SCOPE instruction set.
Such operations include PRPG, PSA, and binary count up (COUNT). Table 4 shows the test operations that
are decoded by the BCR.
During Capture-DR, the contents of the BCR are not changed. At power up or in Test-Logic-Reset, the BCR is
reset to the binary value 010, which selects the PSA test operation. The BCR order of scan is shown in Figure 3.
Bit 2
(MSB)
Bit 1
Bit 0
(LSB)
TDOTDI
Figure 3. Boundary-Control Register Order of Scan
bypass register
The bypass register is a 1-bit scan path that can be selected to shorten the length of the system scan path,
reducing the number of bits per test pattern that must be applied to complete a test operation. During
Capture-DR, the bypass register captures a logic 0. The bypass register order of scan is shown in Figure 4.
Bit 0
TDOTDI
Figure 4. Bypass Register Order of Scan
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11
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