Texas Instruments SN74ABTH16823DLR, SN74ABTH16823DGGR, SN74ABTH16823DL Datasheet

SN54ABTH16823, SN74ABTH16823

18-BIT BUS-INTERFACE FLIP-FLOPS

WITH 3-STATE OUTPUTS

SCBS664B – APRIL 1996 – REVISED MA Y 1997

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

Members of the Texas Instruments

Widebus

 Family

D

State-of-the-Art

EPIC-ΙΙB

 BiCMOS Design

Significantly Reduces Power Dissipation

D

ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)

D

T ypical V

OLP

(Output Ground Bounce) < 1 V

at V

CC

= 5 V, TA = 25°C

D

High-Impedance State During Power Up
and Power Down

D

Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise

D

Flow-Through Architecture Optimizes PCB
Layout

D

High-Drive Outputs (–32-mA IOH, 64-mA IOL)

D

Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors

D

Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings

description

These 18-bit flip-flops feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing wider buffer
registers, I/O ports, bidirectional bus drivers with
parity, and working registers.

The ’ABTH16823 can be used as two 9-bit flip-flops or one 18-bit flip-flop. With the clock-enable (CLKEN

) input
low, the D-type flip-flops enter data on the low-to-high transitions of the clock. Taking CLKEN high disables the
clock buffer , latching the outputs. T aking the clear (CLR) input low causes the Q outputs to go low independently
of the clock.

A buffered output-enable (OE) input can be used to place the nine outputs in either a normal logic state (high
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly . The high-impedance state and increased drive provide the capability to drive bus lines
without need for interface or pullup components.

OE does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.

Copyright  1997, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.

SN54ABTH16823 . . . WD PACKAGE

SN74ABTH16823 . . . DGG OR DL PACKAGE

(TOP VIEW)

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27
28

56
55
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31
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29

1CLR

1OE

1Q1

GND

1Q2
1Q3

V

CC

1Q4
1Q5
1Q6

GND

1Q7
1Q8
1Q9
2Q1
2Q2
2Q3

GND

2Q4
2Q5
2Q6

V

CC

2Q7
2Q8

GND

2Q9

2OE

2CLR

1CLK
1CLKEN
1D1
GND
1D2
1D3
V

CC

1D4
1D5
1D6
GND
1D7
1D8
1D9
2D1
2D2
2D3
GND
2D4
2D5
2D6
V

CC

2D7
2D8
GND
2D9
2CLKEN
2CLK

SN54ABTH16823, SN74ABTH16823
18-BIT BUS-INTERFACE FLIP-FLOPS
WITH 3-STATE OUTPUTS

SCBS664B – APRIL 1996 – REVISED MA Y 1997

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description (continued)

When VCC is between 0 and 2.1 V , the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN54ABTH16823 is characterized for operation over the full military temperature range of –55°C to 125°C.

The SN74ABTH16823 is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

(each 9-bit flip-flop)

INPUTS

OUTPUT

OE

CLR CLKEN

CLK D

Q

L L X X X L
L HL↑ HH
L HL↑ LL
L HLLX Q

0

L HHXX Q

0

H X X X X Z

SN54ABTH16823, SN74ABTH16823

18-BIT BUS-INTERFACE FLIP-FLOPS

WITH 3-STATE OUTPUTS

SCBS664B – APRIL 1996 – REVISED MA Y 1997

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic symbol

†

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

EN1

2

56

1CLK 3C4

4D

54

1D1 1Q1

3

52

1D2 1Q2

5

51

1D3 1Q3

6

49

1D4

1Q4

8

48

1D5

1Q5

9

47

1D6

1Q6

10

45

1D7

1Q7

12

44

1D8

1Q8

13

43

1D9 1Q9

14

1, 2

8D

42

2D1 2Q1

15

41

2D2

2Q2

16

40

2D3 2Q3

17

38

2D4

2Q4

19

37

2D5

2Q5

20

36

2D6

2Q6

21

34

2D7 2Q7

23

33

2D8 2Q8

24

31

2D9 2Q9

26

5, 6

R2

1

G3

55

EN5

27

29

2CLK

7C8

R6

28

G7

30

1OE

1CLR

1CLKEN

2OE

2CLR

2CLKEN