SN54ABTH16460, SN74ABTH16460
4-TO-1 MULTIPLEXED/DEMULTIPLEXED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS207F – OCTOBER 1992 – REVISED MA Y 1997
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Members of the Texas Instruments
Widebus
Family
D
State-of-the-Art
EPIC-ΙΙB
BiCMOS Design
Significantly Reduces Power Dissipation
D
Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
D
T ypical V
OLP
(Output Ground Bounce)
< 1 V at VCC = 5 V, TA = 25°C
D
High-Impedance State During Power Up
and Power Down
D
Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
D
Flow-Through Architecture Optimizes PCB
Layout
D
High-Drive Outputs (–32-mA IOH, 64-mA IOL)
D
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
description
The ’ABTH16460 are 4-bit to 1-bit multiplexed
registered transceivers used in applications
where four separate data paths must be
multiplexed onto or demultiplexed from a single
data path. Typical applications include
multiplexing and/or demultiplexing of address and
data information in microprocessor or
bus-interface applications. These devices also
are useful in memory-interleaving applications.
Five 4-bit I/O ports (1A–4A, 1B1–4, 2B1–4, 3B1–4, and 4B1–4) are available for address and/or data transfer.
The output-enable (OEB
, OEB1–OEB4, and OEA) inputs control the bus-transceiver functions. These control
signals also allow 4-bit or 16-bit control, depending on the OEB level.
Copyright 1997, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.
SN54ABTH16460 . . . WD PACKAGE
SN74ABTH16460 . . . DGG OR DL PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
LEAB1
LEAB2
LEBA
GND
LEB1
LEB2
V
CC
CLKBA
OEB
CLKAB
GND
1A
2A
CE_SEL0
CE_SEL1
3A
4A
GND
CLKENAB
CLKENB
CLKENBA
V
CC
LEB3
LEB4
GND
OEA
LEAB3
LEAB4
OEB1
OEB2
SEL0
GND
1B1
1B2
V
CC
1B3
1B4
2B1
GND
2B2
2B3
2B4
3B1
3B2
3B3
GND
3B4
4B1
4B2
V
CC
4B3
4B4
GND
SEL1
OEB3
OEB4
SN54ABTH16460, SN74ABTH16460
4-TO-1 MULTIPLEXED/DEMULTIPLEXED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS207F – OCTOBER 1992 – REVISED MA Y 1997
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description (continued)
Address and/or data information can be stored using the internal storage latches/flip-flops. The latch-enable
(LEB1–LEB4, LEBA, and LEAB1–LEAB4) and clock/clock-enable (CLK/CLKEN) inputs are used to control data
storage. When either one of the latch-enable inputs is high, the latch is transparent (clock is a don’t care as long
as the latch enable is high). When the latch-enable input goes low (providing that the clock does not transit from
low to high), the data present at the inputs is latched and remains latched until the latch-enable input is returned
high. When the clock enable is low and the corresponding latch enable is low, data can be clocked on the
low-to-high transition of the clock. When either the clock enable or the corresponding latch enable is high, the
clock is a don’t care.
Four select pins (SEL0, SEL1, CE_SEL0, and CE_SEL1) are provided to multiplex data (A port), or to select
one of four clock enables (B port). This allows the user the flexibility of controlling one bit at a time.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
When V
CC
is between 0 and 2.1 V , the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABTH16460 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABTH16460 is characterized for operation from –40°C to 85°C.
Function Tables
A-TO-B OUTPUT ENABLE
†
INPUTS
OUTPUT
OEB OEBn
Bn
H H Z
H LZ
L HZ
L L Active
†
n = 1, 2, 3, 4
A-TO-B STORAGE
(assuming OEB
= L, OEBn = L)
‡
INPUTS
OUTPUTS
CLKENAB CE_SEL1 CE_SEL0 CLKAB LEAB1 LEAB2 LEAB3 LEAB4 B1 B2 B3 B4
X X X H or L H L L L A A
0
A
0
A
0
X X X H or L H H H L A AAA
0
L X X L LLLLA0A
0
A
0
A
0
L LL↑ LLLLAA
0
A
0
A
0
L LH↑ LLLLA0AA0A
0
L HL↑ LLLLA0A
0
AA
0
L HH↑ LLLLA0A
0
A
0
A
H X X ↑ L L L L A
0
A
0
A
0
A
0
‡
This table does not cover all the latch-enable cases since they have similar results.
SN54ABTH16460, SN74ABTH16460
4-TO-1 MULTIPLEXED/DEMULTIPLEXED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS207F – OCTOBER 1992 – REVISED MA Y 1997
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Function Tables (Continued)
B-TO-A STORAGE
(before point P)
INPUTS
CLKENB
CLKBA LEB1 LEB2 LEB3 LEB4 SEL1 SEL0
P
X X H L L L L L B1
X XLHLLLHB2
X X LLHLHLB3
X XLLLHHHB4
L L B1
L HB2
L↑LLL
L
H LB3
H HB4
L L B1
0
†
L HB2
0
†
LLLLL
L
H LB3
0
†
H H B4
0
†
†
Output level before the indicated steady-state input conditions were established
B-TO-A STORAGE
(after point P)
INPUTS
OUTPUT
CLKENBA
CLKBA LEBA
OEA
B
A
X X X H X Z
X XHLL L
X XHLH H
H XLLXA
0
†
L ↑ LLL L
L ↑ LLH H
L L L L X A
0
†
†
Output level before the indicated steady-state input conditions
were established
SN54ABTH16460, SN74ABTH16460
4-TO-1 MULTIPLEXED/DEMULTIPLEXED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS207F – OCTOBER 1992 – REVISED MA Y 1997
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
LE
D
CLK
CE
LE
D
CLK
CE
CLK
CE
D
LE
CLK
CE
D
LE
LE
CLK
CE
D
LE
CLK
CE
D
LE
CLK
CE
D
LE
CLK
CE
D
M
U
X
CE
CLK
D
LE
P
CE_SEL0
CE_SEL1
CLKENAB
1B1
1B2
1B3
1B4
CLKENAB
Selector
One of Four
Channels
CLKAB
OEA
1A
OEB
OEB4
OEB3
OEB2
OEB1
CLKENBA
CLKBA
LEBA
SEL0
SEL1
CLKENB
LEB1
LEB2
LEB3
LEB4 LEAB4
LEAB3
LEAB2
LEAB1
24
23
6
5
31
54
3
8
21
10
26
12
48
49
51
52
19
15
14
9
29
30
55
56
1
2
27
28
20
SN54ABTH16460, SN74ABTH16460
4-TO-1 MULTIPLEXED/DEMULTIPLEXED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS207F – OCTOBER 1992 – REVISED MA Y 1997
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (except I/O ports) (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high or power-off state, VO –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . .
Current into any output in the low state, IO: SN54ABTH16460 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74ABTH16460 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(VI < 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
JA
(see Note 2): DGG package 81°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DL package 74°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51.
recommended operating conditions (see Note 3)
SN54ABTH16460 SN74ABTH16460
MIN MAX MIN MAX
UNIT
V
CC
Supply voltage 4.5 5.5 4.5 5.5 V
V
IH
High-level input voltage 2 2 V
V
IL
Low-level input voltage 0.8 0.8 V
V
I
Input voltage 0 V
CC
0 V
CC
V
I
OH
High-level output current –24 –32 mA
I
OL
Low-level output current 48 64 mA
∆t/∆v Input transition rise or fall rate Outputs enabled 10 10 ns/V
∆t/∆V
CC
Power-up ramp rate 200 200 µs/V
T
A
Operating free-air temperature –55 125 –40 85 °C
NOTE 3: Unused control pins must be held high or low to prevent them from floating.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54ABTH16460, SN74ABTH16460
4-TO-1 MULTIPLEXED/DEMULTIPLEXED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS207F – OCTOBER 1992 – REVISED MA Y 1997
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TA = 25°C SN54ABTH16460 SN74ABTH16460
PARAMETER
TEST CONDITIONS
MIN TYP†MAX MIN MAX MIN MAX
UNIT
V
IK
VCC = 4.5 V, II = –18 mA –1.2 –1.2 –1.2 V
VCC = 4.5 V, IOH = –3 mA 2.5 2.5 2.5
VCC = 5 V, IOH = –3 mA 3 3 3
V
OH
IOH = –24 mA 2 2
V
V
CC
=
4.5 V
IOH = –32 mA 2* 2
IOL = 48 mA 0.36 0.5
VOLV
CC
= 4.5
V
IOL = 64 mA 0.55* 0.55
V
V
hys
100 mV
Control
inputs
VCC = 0 to 5.5 V,
VI = VCC or GND
±1 ±1 ±1
I
I
A or B ports
VCC = 2.1 V to 5.5 V,
VI = VCC or GND
±20 ±20 ±20
µ
A
p
VI = 0.8 V 75 500 75 500 75 500
I
I(hold)
A or B ports
V
CC
=
4.5 V
VI = 2 V –75 –500 –75 –500 –75 –500
µ
A
I
OZPU
‡
VCC = 0 to 2.1 V,
VO = 0.5 V to 2.7 V, OE
= X
±50 ±50 ±50 µA
I
OZPD
‡
VCC = 2.1 V to 0,
VO = 0.5 V to 2.7 V, OE
= X
±50 ±50 ±50 µA
I
off
VCC = 0, VI or VO ≤ 4.5 V ±100 ±100 µA
I
CEX
VCC = 5.5 V,
VO = 5.5 V
Outputs high 50 50 50 µA
I
O
§
VCC = 5.5 V, VO = 2.5 V –50 –100 –200 –50 –200 –50 –200 mA
Outputs high 1.5 1.5 1.5
VCC = 5.5 V,
A outputs low 10 10 10
I
CC
I
O
=
0
,
V
= V
or GND
B outputs low 32 32 32
mA
V
I
=
V
CC
or
GND
Outputs disabled 1.5 1.5 1.5
∆I
CC
¶
VCC = 5.5 V , One input at 3.4 V,
Other inputs at VCC or GND
1.5 1.5 1.5 mA
C
i
Control
inputs
VI = 2.5 V or 0.5 V 8 pF
C
io
A or B ports VO = 2.5 V or 0.5 V 3.5 pF
* On products compliant to MIL-PRF-38535, this parameter does not apply.
†
All typical values are at VCC = 5 V.
‡
This parameter is characterized but not production tested.
§
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
¶
This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54ABTH16460, SN74ABTH16460
4-TO-1 MULTIPLEXED/DEMULTIPLEXED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS207F – OCTOBER 1992 – REVISED MA Y 1997
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
SN54ABTH16460 SN74ABTH16460
MIN MAX MIN MAX
UNIT
f
clock
Clock frequency 0 160 0 160 MHz
CLKAB high or low 3.8 3.8
CLKBA high or low 4.5 4.5
t
w
Pulse duration
LEAB1, 2, 3, or 4 high
2.2 2.2
ns
LEBA high 2.1 2.1
LEB1, 2, 3, or 4 high 2.4 2.4
A bus 2.5 2.5
Before CLKAB
↑
CE_SEL0/1 3.2 3.2
CLKENAB 3.2 3.2
Before LEAB1, 2, 3, or 4↓ A bus 3.6 3.6
B bus 3.8 3.8
CLKENB 2.3 2.3
t
su
Setup time Before CLKBA
↑
CLKENBA 2.5 2.5
ns
LEB1, 2, 3, or 4 4.3 4.3
SEL0/1 4.5 4.5
Before LEB1, 2, 3, or 4↓ B bus 3.2 3.2
B bus 4 4
Before LEBA
↓
LEB1, 2, 3, or 4 4.4 4.4
SEL0/1 4.3 4.3
A bus 0.5 0.5
After CLKAB
↑
CE_SEL0/1 1.1 1.1
CLKENAB 0.5 0.5
After LEAB1, 2, 3, or 4↓ A bus 1.2 1.2
B bus 1.3 1.3
t
h
Hold time
CLKENB 1 1
ns
After CLKBA↑
CLKENBA 1 1
SEL0/1 0 0
After LEB1, 2, 3, or 4↓ B bus 1.5 1.5
B bus 0.4 0.4
After LEBA↓
SEL0/1 0.1 0.1
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54ABTH16460, SN74ABTH16460
4-TO-1 MULTIPLEXED/DEMULTIPLEXED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS207F – OCTOBER 1992 – REVISED MA Y 1997
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C
L
= 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
VCC = 5 V,
TA = 25°C
SN54ABTH16460 SN74ABTH16460
UNIT
(INPUT)
(OUTPUT)
MIN TYP MAX MIN MAX MIN MAX
f
max
160 160 160 MHz
t
PLH
2.5 3.6 5.9 2.5 7.1 2.5 6.5
t
PHL
B
A
2 3.5 5.8 2 6.8 2 6.5
ns
t
PZH
1.5 2.8 4.8 1.5 5.9 1.5 5.6
t
PZL
OEA
A
1.5 2.6 4.6 1.5 5.5 1.5 5.2
ns
t
PHZ
2.5 3.8 5.3 2.5 6 2.5 5.9
t
PLZ
OEA
A
1.5 4.6 6.1 1.5 7 1.5 6.5
ns
t
PLH
2 3.2 5.2 2 6.2 2 5.7
t
PHL
A
B
1.5 3.1 5.2 1.5 6.1 1.5 5.7
ns
t
PZH
1.5 3.3 5.7 1.5 6.7 1.5 6.4
t
PZL
OEB
B
1.5 3.2 5.5 1.5 6.6 1.5 6.3
ns
t
PHZ
3 4.7 6.3 3 7.1 3 7
t
PLZ
OEB
B
2 4 5.5 2 6.6 2 6.1
ns
t
PZH
1.5 3 5.2 1.5 6 1.5 5.8
t
PZL
OEB1, 2, 3, 4
B
1.5 2.9 4.9 1.5 5.9 1.5 5.6
ns
t
PHZ
2.5 4 5.7 2.5 6.2 2.5 6.1
t
PLZ
OEB1, 2, 3, 4
B
1.5 3.5 4.8 1.5 5.8 1.5 5.3
ns
t
PLH
1.5 4.2 6.7 1.5 8.1 1.5 7.4
t
PHL
CLKBA
A
1.5 4.4 6.9 1.5 8.4 1.5 7.7
ns
t
PLH
2 3.4 5.6 2 6.8 2 6.2
t
PHL
CLKAB
B
2 3.4 5.3 2 6.3 2 5.9
ns
t
PLH
2 3 5 2 6.1 2 5.6
t
PHL
LEBA
A
2 3.1 4.8 2 5.8 2 5.3
ns
t
PLH
2 3.2 5.2 2 6.3 2 5.8
t
PHL
LEAB1, 2, 3, 4
B
2 3.3 5 2 6.1 2 5.6
ns
t
PLH
2.5 4 6.5 2.5 7.8 2.5 7.2
t
PHL
LEBA1, 2, 3, 4
A
2.5 4 6.1 2.5 7.5 2.5 6.8
ns
t
PLH
2 4.1 6.7 2 8.1 2 7.5
t
PHL
SEL
A
2 3.8 6.2 2 7.3 2 6.9
ns
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54ABTH16460, SN74ABTH16460
4-TO-1 MULTIPLEXED/DEMULTIPLEXED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS207F – OCTOBER 1992 – REVISED MA Y 1997
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
1.5 V
t
h
t
su
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
7 V
Open
GND
500 Ω
500 Ω
Data Input
Timing Input
1.5 V
3 V
0 V
1.5 V 1.5 V
3 V
0 V
3 V
0 V
1.5 V
t
w
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
t
PLH
t
PHL
t
PHL
t
PLH
V
OH
V
OH
V
OL
V
OL
1.5 V 1.5 V
3 V
0 V
1.5 V1.5 V
Input
1.5 V
Output
Control
Output
Waveform 1
S1 at 7 V
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
V
OL
V
OH
t
PZL
t
PZH
t
PLZ
t
PHZ
1.5 V1.5 V
3.5 V
0 V
1.5 V
VOL + 0.3 V
1.5 V
VOH – 0.3 V
≈ 0 V
3 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
Open
7 V
Open
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
1.5 V
Figure 1. Load Circuit and Voltage Waveforms
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICA TIONS IS UNDERSTOOD T O
BE FULLY AT THE CUSTOMER’S RISK.
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