Texas Instruments SN74ABT827DBLE, SN74ABT827DBR, SN74ABT827DW, SN74ABT827DWR, SN74ABT827NT Datasheet
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SN54ABT827, SN74ABT827
10-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS159D – JANUARY 1991 – REVISED MA Y 1997
D
State-of-the-Art
EPIC-ΙΙB
BiCMOS Design
Significantly Reduces Power Dissipation
D
Flow-Through Architecture Optimizes PCB
Layout
D
Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
D
T ypical V
(Output Ground Bounce) < 1 V
OLP
at VCC = 5 V, TA = 25°C
D
High-Impedance State During Power Up
and Power Down
D
High-Drive Outputs (–32-mA IOH, 64-mA IOL)
D
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK), and
Plastic (NT) and Ceramic (JT) DIPs
description
These 10-bit buffers or bus drivers provide a
high-performance bus interface for wide data
paths or buses carrying parity.
The 3-state control gate is a 2-input AND gate with
active-low inputs so that if either output-enable
(OE1 or OE2) input is high, all ten outputs are in
the high-impedance state. The ’ABT827 provide
true data at the outputs.
When VCC is between 0 and 2.1 V, the device
is in the high-impedance state during power up
or power down. However, to ensure
the high-impedance state above 2.1 V, OE
be tied to VCC through a pullup resistor; the
minimum value of the resistor is determined by
the current-sinking capability of the driver.
should
SN74ABT827 . . . DB, DW, NT, OR PW PACKAGE
SN54ABT827 . . . JT PACKAGE
(TOP VIEW)
1
OE1
2
A1
3
A2
4
A3
5
A4
6
A5
7
A6
8
A7
9
A8
10
A9
11
A10
GND
SN54ABT827 . . . FK PACKAGE
A3
A4
A5
NC
A6
A7
A8
NC – No internal connection
12
(TOP VIEW)
A2A1OE1NCY1
3212827
426
5
6
7
8
9
10
11
12 13
14 15 16 1718
A9
A10
GND
24
23
22
21
20
19
18
17
16
15
14
13
NC
CC
V
OE2
V
CC
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
OE2
Y10
Y2
25
24
23
22
21
20
19
Y9
Y3
Y4
Y5
NC
Y6
Y7
Y8
The SN54ABT827 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74ABT827 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
OE1 OE2 A
L L L L
L LH H
H XX Z
X H X Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
INPUTS
OUTPUT
Y
Copyright 1997, Texas Instruments Incorporated
1
SN54ABT827, SN74ABT827
†
10-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS159D – JANUARY 1991 – REVISED MA Y 1997
logic symbol
1
OE1
13
OE2
2
A1
3
A2
4
A3
5
A4
6
A5
7
A6
8
A7
9
A8
10
A9
11
A10
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
Pin numbers shown are for the DB, DW, JT, NT, and PW packages.
&
EN
1
23
22
21
20
19
18
17
16
15
14
logic diagram (positive logic)
1
OE1
13
OE2
223
A1
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y1
To Nine Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
‡
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
Voltage range applied to any output in the high or power-off state, VO –0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . .
Current into any output in the low state, IO: SN54ABT827 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74ABT827 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
(VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OK
Package thermal impedance, θJA (see Note 2): DB package 104°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DW package 81°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NT package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 120°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for through-hole packages,
which use a trace length of zero.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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