Texas Instruments SN74ABT7819-20PN, SN74ABT7819-30PH, SN74ABT7819-30PN, SN74ABT7819-10PH, SN74ABT7819-10PN Datasheet
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D
Member of the Texas Instruments
Widebus Family
D
Free-Running CLKA and CLKB Can Be
Asynchronous or Coincident
D
Read and Write Operations Synchronized
to Independent System Clocks
D
Two Separate 512 × 18 Clocked FIFOs
Buffering Data in Opposite Directions
D
IRA and ORA Synchronized to CLKA
D
IRB and ORB Synchronized to CLKB
SN74ABT7819
512 × 18 × 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCBS125G – JULY 1992 – REVISED JULY 1998
D
Microprocessor Interface Control Logic
D
Programmable Almost-Full/Almost-Empty
Flag
D
Fast Access Times of 9 ns With a 50-pF
Load and Simultaneous Switching Data
Outputs
D
Data Rates up to 100 MHz
D
Advanced BiCMOS Technology
D
Package Options Include 80-Pin Quad Flat
(PH) and 80-Pin Thin Quad Flat (PN)
Packages
PH PACKAGE
(TOP VIEW)
RSTA
PENA
AF/AEA
HFA
IRA
GND
A0
A1
V
CC
A2
A3
GND
A4
A5
GND
A6
A7
GND
A8
A9
V
CC
A10
A11
GND
CSA
W/RA
GND
WENA
CLKA
RENA
8079 78 77 76 75 74 73 72 7170 69 68 67 66
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
26 27 28 2930 3132 33 343536 37 38 39
ORA
VCCV
CC
RENB
ORB
CLKB
WENB
GND
W/RB
CSB
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
4025
RSTB
PENB
AF/AEB
HFB
IRB
GND
B0
B1
V
CC
B2
B3
GND
B4
B5
GND
B6
B7
GND
B8
B9
V
CC
B10
B1 1
GND
CC
A12
A13
V
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
A14
A15
A16
GND
A17
B17
B16
B15
GND
B14
V
CC
B13
B12
Copyright 1998, Texas Instruments Incorporated
1
SN74ABT7819
512 × 18 × 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCBS125G – JULY 1992 – REVISED JULY 1998
PN PACKAGE
(TOP VIEW)
AF/AEA
HFA
IRA
GND
A0
A1
V
CC
A2
A3
GND
A4
A5
GND
A6
A7
GND
A8
A9
V
CC
A10
CSA
GND
W/RA
RENA
CLKA
RSTA
PENA
80 79 78 77 76 75 74 73 71 70 69 68 67 66 65 64 63 62 6172
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21 22 23 24 25 4026 27 28 29 30 31 32 33 34 35 36 37 38 39
WENA
ORA
VCCV
CC
ORB
CLKB
RENB
WENB
GND
CSB
W/RB
RSTB
PENB
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
AF/AEB
HFB
IRB
GND
B0
B1
V
CC
B2
B3
GND
B4
B5
GND
B6
B7
GND
B8
B9
V
CC
B10
A12
A13
V
CC
A14
A15
A16
GND
A17
B17
B16
GND
A11
GND
B15
B14
V
CC
B13
B12
GND
B11
description
A FIFO memory is a storage device that allows data to be written into and read from its array at independent
data rates. The SN74ABT7819 is a high-speed, low-power BiCMOS bidirectional clocked FIFO memory . Two
independent 512 ×18 dual-port SRAM FIFOs on the chip buffer data in opposite directions. Each FIFO has flags
to indicate empty and full conditions, a half-full flag, and a programmable almost-full/almost-empty flag.
The SN74ABT7819 is a clocked FIFO, which means each port employs a synchronous interface. All data
transfers through a port are gated to the low-to-high transition of a continuous (free-running) port clock by enable
signals. The continuous clocks for each port are independent of one another and can be asynchronous or
coincident. The enables for each port are arranged to provide a simple bidirectional interface between
microprocessors and/or buses with synchronous control.
The state of the A0–A17 outputs is controlled by CSA
are active. The A0–A17 outputs are in the high-impedance state when either CSA
written to FIFOA–B from port A on the low-to-high transition of CLKA when CSA
is high, and the IRA flag is high. Data is read from FIFOB–A to the A0–A17 outputs on the low-to-high transition
of CLKA when CSA
is low, W/RA is low, RENA is high, and the ORA flag is high.
and W/RA. When both CSA and W/RA are low, the outputs
or W/RA is high. Data is
is low, W/RA is high, WENA
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
A0–A17
PORT-A OPERATION
B0–B17
PORT-B OPERATION
SN74ABT7819
512 × 18 × 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCBS125G – JULY 1992 – REVISED JULY 1998
description (continued)
The state of the B0–B17 outputs is controlled by CSB and W/RB. When both CSB and W/RB are low, the outputs
are active. The B0–B17 outputs are in the high-impedance state when either CSB
written to FIFOB–A from port B on the low-to-high transition of CLKB when CSB
is high, and the IRB flag is high. Data is read from FIFOA–B to the B0–B17 outputs on the low-to-high transition
of CLKB when CSB
is low, W/RB is low, RENB is high, and the ORB flag is high.
or W/RB is high. Data is
is low, W/RB is high, WENB
The setup- and hold-time constraints for the chip selects (CSA
, CSB) and write/read selects (W/RA, W/RB)
enable write and read operations on memory and are not related to the high-impedance control of the data
outputs. If a port read enable (RENA or RENB) and write enable (WENA or WENB) are set low during a clock
cycle, the chip select and write/read select can switch at any time during the cycle to change the state of the
data outputs.
The input-ready (IR) and output-ready (OR) flags of a FIFO are two-stage synchronized to the port clocks for
use as reliable control signals. CLKA synchronizes the status of the input-ready flag of FIFOA–B (IRA) and the
output-ready flag of FIFOB–A (ORA). CLKB synchronizes the status of the input-ready flag of FIFOB–A (IRB)
and the output-ready flag of FIFOA–B (ORB). When the IR flag of a port is low, the FIFO receiving input from
the port is full and writes are disabled to its array . When the OR flag of a port is low , the FIFO that outputs data
to the port is empty and reads from its memory are disabled. The first word loaded to an empty memory is sent
to the FIFO output register at the same time its OR flag is asserted (high). When the memory is read empty and
the OR flag is forced low, the last valid data remains on the FIFO outputs until the OR flag is asserted (high)
again. In this way, a high on the OR flag indicates new data is present on the FIFO outputs.
The SN74ABT7819 is characterized for operation from 0°C to 70°C.
Function Tables
PORT A
SELECT INPUTS
CLKA CSA W/RA WENA RENA
X H X X X High Z None
↑ L H H X High Z Write A0–A17 to FIFOA–B
↑ L L X H Active Read FIFOB–A to A0–A17
PORT B
SELECT INPUTS
CLKB CSB W/RB WENB RENB
X H X X X High Z None
↑ L H H X High Z Write B0–B17 to FIFOB–A
↑ L L X H Active Read FIFOA–B to B0–B17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN74ABT7819
512 × 18 × 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCBS125G – JULY 1992 – REVISED JULY 1998
logic symbol
†
CLKA
CSA
W/R
WENA
RENA
RSTA
PENA
IRA
ORA
HFA
AF/AEA
76
80
79
A
77
75
1
2
5
74
4
3
CLOCK A
&
OE1
&
WRITE
ENABLE
FIFOA–B
&
READ
ENABLE
FIFOB–A
RESET FIFO A–B
PROGRAM ENABLE
FIFO A–B
INPUT-READY
PORT A
OUTPUT-READY
PORT A
HALF-FULL
FIFOA–B
ALMOST-FULL/EMPTY
FIFOA–B
Φ
FIFO 512 × 18 × 2
SN74ABT7819
PROGRAM ENABLE
ALMOST-FULL/EMPTY
CLOCK B
&
OE2
WRITE
ENABLE
FIFOB–A
READ
ENABLE
FIFOA–B
RESET FIFO B–A
INPUT-READY
OUTPUT-READY
HALF-FULL
&
&
FIFO B–A
PORT B
PORT B
FIFOB–A
FIFOB–A
69
65
66
68
70
64
63
60
71
61
62
CLKB
CSB
W/RB
WENB
RENB
RSTB
PENB
IRB
ORB
HFB
AF/AEB
7
A0
8
A1
10
A2
11
A3
13
A4
14
A5
16
A6
17
A7
19
A8
20
A9
22
A10
23
A11
25
A12
26
A13
28
A14
29
A15
31
A16
32
A17
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the PH package.
0
1
Data
17
Data
2
17
58
0
57
55
54
52
51
49
48
46
45
43
42
40
39
37
36
34
33
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
PENA
RENA
WENA
CSA
W/R
A
CLKA
RSTA
SN74ABT7819
512 × 18 × 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCBS125G – JULY 1992 – REVISED JULY 1998
Port-A
Control
Logic
Read
Pointer
ORA
A0–A17
IRA
AF/AEA
HFA
18
18
Register
Logic
FIFOB–A
8
Register Register
Dual-Port SRAM
18
Flag
Write
Pointer
512 × 18
FIFOA–B
512 × 18
Dual-Port SRAM
FIFOB–A
Write
Pointer
8
Flag
Logic
FIFOA–B
Register
18
IRB
AF/AEB
HFB
B0–B17
ORB
Read
Pointer
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Port-B
Control
Logic
RSTB
CLKB
CSB
B
W/R
WENB
RENB
PENB
5
SN74ABT7819
I/O
DESCRIPTION
512 × 18 × 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCBS125G – JULY 1992 – REVISED JULY 1998
enable logic diagram (positive logic)
CSA
W/RA
WENA
WEN FIFOA–B
A0–A17 (output enable)
RENA
WEN FIFOB–A
B0–B17 (output enable)
REN FIFOA–B
TERMINAL
NAME NO.
A0–A17
AF/AEA 3 O
AF/AEB 62 O
B0–B17
CLKA 76 I
CLKB 69 I
CSA
CSB
†
Terminals listed are for the PH package.
†
7–8, 10–11,
13–14, 16–17,
19–20, 22–23,
25–26, 28–29,
31–32
58–57, 55–54,
52–51, 49–48,
46–45, 43–42,
40–39, 37–36,
34–33
80 I
65 I
I/O Port-A data. The 18-bit bidirectional data port for side A.
I/O Port-B data. The 18-bit bidirectional data port for side B.
REN FIFOB–A
CSB
W/RB
WENB
RENB
Terminal Functions
FIFOA–B almost-full/almost-empty flag. Depth offsets can be programmed for AF/AEA or the default
value of 128 can be used for both the almost-empty offset (X) and the almost-full offset (Y). AF/AEA is
high when X or fewer words or (512 – Y) or more words are stored in FIFOA–B. AF/AEA is forced high
when FIFOA–B is reset.
FIFOB–A almost-full/almost-empty flag. Depth offsets can be programmed for AF/AEB or the default
value of 128 can be used for both the almost-empty offset (X) and the almost-full offset (Y). AF/AEB is
high when X or fewer words or (512 – Y) or more words are stored in FIFOB–A. AF/AEB is forced high
when FIFOB–A is reset.
Port-A clock. CLKA is a continuous clock that synchronizes all data transfers through port A to its
low-to-high transition and can be asynchronous or coincident to CLKB.
Port-B clock. CLKB is a continuous clock that synchronizes all data transfers through port B to its
low-to-high transition and can be asynchronous or coincident to CLKA.
Port-A chip select. CSA must be low to enable a low-to-high transition of CLKA to either write data from
A0–A17 to FIFOA–B or read data from FIFOB–A to A0–A17. The A0–A17 outputs are in the
high-impedance state when CSA
Port-B chip select. CSB must be low to enable a low-to-high transition of CLKB to either write data from
B0–B17 to FIFOB–A or read data from FIFOA–B to B0–B17. The B0–B17 outputs are in the
high-impedance state when CSB
is high.
is high.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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