Texas Instruments SN65LVDS93DGG, SN65LVDS93DGGR Datasheet
SN65LVDS93
LVDS SERDES TRANSMITTER
SLLS302F – MAY 1998 – REVISED FEBRUAR Y 2000
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
28:4 Data Channel Compression at up to
1.82 Gigabits per Second Throughput
D
Suited for Point-to-Point Subsystem
Communication With Very Low EMI
D
28 Data Channels Plus Clock in
Low-Voltage TTL and 4 Data Channels Plus
Clock Out Low-Voltage Differential
D
Selectable Rising or Falling Clock Edge
Triggered Inputs
D
Bus Pins Tolerate 6-kV HBM ESD
D
Operates From a Single 3.3-V Supply and
250 mW (Typ)
D
5-V Tolerant Data Inputs
D
Packaged in Thin Shrink Small-Outline
Package With 20 Mil Terminal Pitch
D
Consumes <1 mW When Disabled
D
Wide Phase-Lock Input Frequency Range
20 MHz to 65 MHz
D
No External Components Required for PLL
D
Outputs Meet or Exceed the Requirements
of ANSI EIA/TIA-644 Standard
D
Industrial Temperature Qualified
T
A
= –40°C to 85°C
D
Replacement for the DS90CR285
description
The SN65LVDS93 LVDS serdes (serializer/deserializer) transmitter contains four 7-bit parallelload serial-out shift registers, a 7× clock
synthesizer, and five low-voltage differential signaling (LVDS) drivers in a single integrated circuit. These
functions allow 28 bits of single-ended LVTTL data to be synchronously transmitted over five balanced-pair
conductors for receipt by a compatible receiver, such as the SN65LVDS94.
When transmitting, data bits D0 through D27 are each loaded into registers upon the edge of the input clock
signal (CLKIN). The rising or falling edge of the clock can be selected via the clock select (CLKSEL) pin. The
frequency of CLKIN is multiplied seven times and then used to serially unload the data registers in 7-bit slices.
The four serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers. The
frequency of CLKOUT is the same as the input clock, CLKIN.
The SN65LVDS93 requires no external components and little or no control. The data bus appears the same
at the input to the transmitter and output of the receiver with the data transmission transparent to the user(s).
The only user intervention is selecting a clock rising edge by inputting a high level to CLKSEL or a falling edge
with a low-level input and the possible use of the shutdown/clear (SHTDN
). SHTDN is an active-low input to
inhibit the clock and shut off the LVDS output drivers for lower power consumption. A low level on this signal
clears all internal registers at a low level.
The SN65LVDS93 is characterized for operation over ambient air temperatures of –40°C to 85°C.
Copyright 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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V
CC
D5
D6
D7
GND
D8
D9
D10
V
CC
D11
D12
D13
GND
D14
D15
D16
CLKSEL
D17
D18
D19
GND
D20
D21
D22
D23
V
CC
D24
D25
D4
D3
D2
GND
D1
D0
D27
LVDSGND
Y1M
Y1P
Y2M
Y2P
LVDSV
CC
LVDSGND
Y3M
Y3P
CLKOUTM
CLKOUTP
Y4M
Y4P
LVDSGND
PLLGND
PLLV
CC
PLLGND
SHTDN
CLKIN
D26
GND
DGG PACKAGE
(TOP VIEW)
SN65LVDS93
LVDS SERDES TRANSMITTER
SLLS302F – MAY 1998 – REVISED FEBRUAR Y 2000
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
A,B, ...G
SHIFT/LOAD
CLK
Parallel-Load 7-Bit
Shift Register
7
A,B, ...G
SHIFT/LOAD
CLK
Parallel-Load 7-Bit
Shift Register
7
A,B, ...G
SHIFT/LOAD
CLK
Parallel-Load 7-Bit
Shift Register
7
A,B, ...G
SHIFT/LOAD
CLK
Parallel-Load 7-Bit
Shift Register
7
Control Logic
7×CLK
CLK
CLKINH
7× Clock/PLL
SHTDN
CLKIN
D5, D10, D11, D16,
D17, D23, D27
D19, D20, D21, D22,
D24, D25, D26
D8, D9, D12, D13,
D14, D15, D18
D0, D1, D2, D3,
D4, D6, D7
Y0P
Y0M
Y1P
Y1M
Y2P
Y2M
Y3P
Y3M
CLKOUTP
CLKOUTM
Input Bus
CLKSEL
RISING/FALLING
EDGE
SN65LVDS93
LVDS SERDES TRANSMITTER
SLLS302F – MAY 1998 – REVISED FEBRUAR Y 2000
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CLKOUT
CLKIN
or
CLKIN
D0
Y0
Y1
Y2
Y3
D0–1 D7 D6 D4 D3 D2 D1 D0 D7+1
D8–1 D18 D15 D14 D13 D12 D9 D8 D18+1
D19–1 D26 D25 D24 D22 D21 D20 D19 D26+1
D27–1 D23 D17 D16 D11 D10 D5 D27 D23+1
Current Cycle
Next
Cycle
Previous Cycle
Figure 1. Typical ’LVDS93 Load and Shift Sequences
equivalent input and output schematic diagrams
V
CC
50 Ω
300 kΩ
7 V
Dn or
SHTDN
V
CC
7 V
10 kΩ
5 Ω
YnP or YnM
INPUT OUTPUT
SN65LVDS93
LVDS SERDES TRANSMITTER
SLLS302F – MAY 1998 – REVISED FEBRUAR Y 2000
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
†
Supply voltage range, VCC (see Note 1) –0.5 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range at any output terminal, VO –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range at any input terminal, V
I
–0.5 V to 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrostatic discharge (see Note 2): Bus Pins (Class 3A) 6 KV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bus Pins (Class 2B) 400 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bus Pins (Class 2A) 6 KV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bus Pins (Class 2B) 200 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, T
A
–40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to the GND terminals.
2. This rating is measured using MIL-STD-883C Method, 3015.7.
DISSIPATION RATING T ABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
‡
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
DGG 1377 mW 11 mW/°C 882 mW 717 mW
‡
This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, V
CC
3 3.3 3.6 V
High-level input voltage, V
IH
2 V
Low-level input voltage, V
IL
0.8 V
Differential load impedance, Z
L
90 132 Ω
Operating free-air temperature, T
A
–40 85 °C
SN65LVDS93
LVDS SERDES TRANSMITTER
SLLS302F – MAY 1998 – REVISED FEBRUAR Y 2000
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
V
T
Input voltage threshold 1.4 V
|VOD| Differential steady-state output voltage magnitude 247 454 mV
∆|VOD|
Change in the steady-state differential output
voltage magnitude between opposite binary states
RL = 100 Ω, See Figure 3
50 mV
V
OC(SS)
Steady-state common-mode output voltage See Figure 3 1.125 1.375 V
V
OC(PP)
Peak-to-peak common-mode output voltage 150 mV
I
IH
High-level input current VIH = V
CC
20 µA
I
IL
Low-level input current VIL = 0 V ±10 µA
p
VOY = 0 V ±24 mA
IOSShort-circuit output current
VOD = 0 V ±12 mA
I
OZ
High-impedance state output current VO = 0 V to V
CC
±20 µA
Disabled, All inputs at GND 350 µA
I
CC(AVG)
Quiescent current (average)
Enabled, RL = 100 Ω (5 places),
Worst-case pattern (see Figure 4),
tc = 15.38 ns
95 120 mA
C
i
Input capacitance 3 pF
†
All typical values are at VCC = 3.3 V, TA = 25°C.
timing requirements
MIN NOM MAX
UNIT
t
c
Input clock period 15.4 t
c
50 ns
t
w
High-level input clock pulse width duration 0.4t
c
0.6t
c
ns
t
t
Input signal transition time 5 ns
t
su
Data setup time, D0 through D27 before CLKIN↑ or CLKIN↓ (See Figure 2) 3 ns
t
h
Data hold time, D0 through D27 after CLKIN↓ or CLKIN↑ (See Figure 2) 1.5 ns
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