Texas Instruments SN65LVDS388DBT, SN65LVDS388DBTR, SN65LVDT386DGG, SN65LVDT386DGGR, SN65LVDT388DBT Datasheet

...

SN65LVDS386, SN65LVDT386, SN75LVDS386, SN75LVDT386 SN65LVDS388, SN65LVDT388, SN75LVDS388, SN75LVDT388

HIGH-SPEED DIFFERENTIAL LINE RECEIVERS

SLLS394A – SEPTEMBER 1999 – REVISED DECEMBER 1999

Eight (‘388) or Sixteen (‘386) Line Receivers Meet or Exceed the Requirements of ANSI TIA/EIA-644 Standard

Integrated 110-Ω Line Termination Resistors on LVDT Products

Designed for Signaling Rates† Up To 630 Mbps

SN65 Version’s Bus-Terminal ESD Exceeds 15 kV

Operates From a Single 3.3-V Supply

Typical Propagation Delay Time of 2.6 ns

Output Skew 100 ps (Typ) Part-To-Part Skew is Less Than 1 ns

LVTTL Levels are 5-V Tolerant

Open-Circuit Fail Safe

Flow-Through Pin Out

Packaged in Thin Shrink Small-Outline Package With 20-mil Terminal Pitch

description

The ‘LVDS388 and ‘LVDT388 (T designates integrated termination) are eight and the ‘LVDS386 and ‘LVDT386 sixteen differential line receivers respectively that implement the electrical characteristics of low-voltage differential signaling (L VDS). This signaling technique lowers the output voltage levels of 5-V differential standard levels (such as EIA/TIA-422B) to reduce the power, increase the switching speeds, and allow operation with a 3-V supply rail. Any of the eight or sixteen differential receivers will provide a valid logical output state with a ±100 mV differential input voltage within the input commonmode voltage range. The input common-mode voltage range allows 1 V of ground potential difference between two L VDS nodes. Additionally , the high-speed switching of L VDS signals almost always require the use of a line impedance matching resistor at the receiving end of the cable or transmission media. The LVDT products eliminate this external resistor by integrating it with the receiver.

SN65LVDS388, SN75LVDS388 SN65LVDT388, SN75LVDT388

DBT PACKAGE

(TOP VIEW)

38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20

GND V

ENA A1Y A2Y ENB B1Y B2Y GND V

GND C1Y C2Y ENC D1Y D2Y END V

GND

A1A A1B A2A A2B

NC B1A B1B B2A B2B

NC C1A C1B C2A C2B

NC D1A D1B D2A D2B

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

SN65LVDS386, SN75LVDS386 SN65LVDT386, SN75LVDT386

DGG PACKAGE

(TOP VIEW)

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

GND V

GND ENA A1Y A2Y A3Y A4Y ENB B1Y B2Y B3Y B4Y GND V

GND C1Y C2Y C3Y C4Y ENC D1Y D2Y D3Y D4Y END GND V

GND

A1A A1B A2A A2B A3A A3B A4A A4B B1A B1B B2A B2B B3A B3B B4A B4B C1A C1B C2A C2B C3A C3B C4A C4B D1A D1B D2A D2B D3A D3B D4A D4B

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

†

Signaling rate, 1/t, where t is the minimum unit interval and is expressed in the units bits/s (bits per second)

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN65LVDS386, SN65LVDT386, SN75LVDS386, SN75LVDT386 SN65LVDS388, SN65LVDT388, SN75LVDS388, SN75LVDT388 HIGH-SPEED DIFFERENTIAL LINE RECEIVERS

SLLS394A – SEPTEMBER 1999 – REVISED DECEMBER 1999

description (continued)

The intended application of this device and signaling technique is for point-to-point baseband data transmission over controlled impedance media of approximately 100 Ω. The transmission media may be printed circuit board traces, backplanes, or cables. The large number of receivers integrated into the same substrate along with the low pulse skew of balanced signaling, allows extremely precise timing alignment of clock and data for synchronous parallel data transfers. When used with its companion, 8- or 16-channel driver, the SN65LVDS389 or SN65L VDS387, over 300 million data transfers per second in single-edge clocked systems are possible with very little power. (Note: The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other system characteristics.)

Available Options

Part number

SN65LVDS386DGG SN65LVDT386DGG SN75LVDS386DGG SN75LVDT386DGG SN65LVDS388DBT SN65LVDT388DBT SN75LVDS388DBT SN75LVDT388DBT

Temperature

Range

–40_C to 85_C –40_C to 85_C

0_C to 70_C

0_C to 70_C –40_C to 85_C –40_C to 85_C

0_C to 70_C

Number of

Receivers

16 15 kV 16 15 kV 16 4 kV 16 4 kV

8 15 kV 8 15 kV 8 4 kV 8 4 kV

Bus-Pin ESD

logic diagram (positive logic)

’LVDx386

’LVDT386 ONLY

1A 1B

2A 2B

3A 3B 4A 4B

H = high level, L = low level, X = irrelevant, Z = high impedance (off), ? = indeterminate

’LVDT388 ONLY

1A 1B

2A 2B

’LVDx388

Function Table

SNx5LVD386/388 and SNx5LVDT386/388

DIFFERENTIAL INPUT

A-B EN Y

VID ≥ 100 mV H H

-100 mV < VID ≤ 100 mV H ? VID≤ -100 mV H L

X L Z

Open H H

ENABLES OUTPUT

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN65LVDS386, SN65LVDT386, SN75LVDS386, SN75LVDT386 SN65LVDS388, SN65LVDT388, SN75LVDS388, SN75LVDT388

equivalent input and output schematic diagrams

HIGH-SPEED DIFFERENTIAL LINE RECEIVERS

SLLS394A – SEPTEMBER 1999 – REVISED DECEMBER 1999

300 kΩ300 kΩ

A Input B Input

7 V 7 V

110 Ω

’LVDT Devices Only

100 Ω

7 V

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

300 kΩ

5 Ω

Y Output

7 V

†

Supply voltage range, VCC (see Note 1) –0.5 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range: Enables or Y –0.5 V to VCC + 2 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A or B –0.5 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Electrostatic discharge: (see Note 2)

SN65’ (A, B, and GND) Class 3, A:15 kV, B: 700 V. . . . . . . . . . . . . . . . . . . . . . . . . . . .

SN65’ (All pins) Class 3, A: 8 kV, B:600 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SN75’ (A, B, and GND) Class 2, A:4 kV, B: 400 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SN75’ (All pins) Class 2, A: 2 kV, B:200 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 in) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.

‡

This is the inverse of the junction-to-ambient thermal resistance when board-mounted (low-k) and with no air flow.

2. Tested in accordance with MIL-STD-883C Method 3015.7.

DISSIPATION RATING TABLE

PACKAGE

DBT 1071 mW 8.5 mW/°C 688 mW 556 mW

DGG 2094 mW 16.7 mW/°C 1342 mW 1089 mW

TA ≤ 25°C

DERATING FACTOR

ABOVE TA = 25°C

‡

TA = 70°C

POWER RATING

TA = 85°C

POWER RATING

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN65LVDS386, SN65LVDT386, SN75LVDS386, SN75LVDT386

O erating free-air tem erature, T

SN65LVDS388, SN65LVDT388, SN75LVDS388, SN75LVDT388 HIGH-SPEED DIFFERENTIAL LINE RECEIVERS

SLLS394A – SEPTEMBER 1999 – REVISED DECEMBER 1999

recommended operating conditions

MIN NOM MAX UNIT

Supply voltage, V High-level input voltage, V Low-level input voltage, V Magnitude of differential input voltage, VID 0.1 0.6 V

Common–mode input voltage, VIC (see Figure 4)

SN75’ 0 70 °C SN65’ –40 85 °C

3 3.3 3.6 V 2 V

|VID|

2.4

VCC – 0.8

0.8 V

|VID|

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

See Figure 1 and Table 1

Supply current

’LVDS

Input current (A or B inputs)

’LVDT

High–impedance output current

See Figure 3

SN65LVDS386, SN65LVDT386, SN75LVDS386, SN75LVDT386 SN65LVDS388, SN65LVDT388, SN75LVDS388, SN75LVDT388

HIGH-SPEED DIFFERENTIAL LINE RECEIVERS

SLLS394A – SEPTEMBER 1999 – REVISED DECEMBER 1999

electrical characteristics over recommended operating conditions (unless otherwise noted).

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

ITH+

ITH–

I(OFF)

(t)

†

All typical values are at 25°C and with a 3.3 V supply.

Positive–going differential input voltage threshold Negative–going differential input voltage threshold High–level output voltage IOH = –8 mA 2.4 3 V Low–level output voltage IOL = 8 mA 0.2 0.4 V

’

Differential input current |IIA – IIB| ‘LVDS

Differential input current (IIA – IIB) ‘LVDT Power–off Input current (A or B inputs) ‘LVDS VCC = 0 V, VI=2.4 V 12 ±20 µA

Power–off Input current (A or B inputs) ‘LVDT VCC = 0 V, VI=2.4 V ±40 µA High–level input current (enables) VIH = 2 V 10 µA Low–level input current (enables) VIL = 0.8 V 10 µA

Input Capacitance, A or B input to GND VID = 0.4 sin 2.5E09 t V 5 pF T ermination impedance VID = 0.4 sin 2.5E09 t V 88 132 Ω

’

Enabled, No load 50 70 Disabled 3 VI = 0 V –13 –20 VI = 2.4 V –1.2 –3 VI = 0 V, other input open –40 VI = 2.4 V, other input open –2.4 VIA= 0 V, VIB = 0.1V,

VIA= 2.4 V, VIB = 2.3 V VIA= 0.2 V, VIB = 0V,

VIA= 2.4 V, VIB = 2.2 V

VO = 0 V ±1 VO = 3.6 V 10

–100 mV

1.5 2.2 mA

100 mV

±2 µA

switching characteristics over recommended operating conditions (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

PLH

PHL

sk(p)

sk(o)

sk(pp)

PZH

PZL

PHZ

PLZ

†

All typical values are at 25°C and with a 3.3 V supply.

‡

sk(o)

sk(pp)

with the same supply voltages, at the same temperature, and have identical packages and test circuits.

Propagation delay time, low-to-high-level output 1 2.6 4 ns Propagation delay time, high-to-low-level output 1 2.5 4 ns Differential output signal rise time 500 800 1200 ps Differential output signal fall time Pulse skew (|t

Output skew Part-to-part skew

Propagation delay time, high-impedance-to-high-level output 7 15 ns Propagation delay time, high-impedance-to-low-level output Propagation delay time, high-level-to-high-impedance output Propagation delay time, low-level-to-high-impedance output 7 15 ns

is the magnitude of the time difference between the t

is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate

‡

PHL

– t

PLH

or t

PLH

of all drivers of a single device with all of their inputs connected together.

PHL

See Figure 2

500 800 1200 ps

150 600 ps 100 400 ps

1 ns

7 15 ns 7 15 ns

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

+ 10 hidden pages