Eight (’389) or Sixteen (’387) Line Drivers
Meet or Exceed the Requirements of ANSI
EIA/TIA-644 Standard
D
Designed for Signaling Rates up to
630 Mbps With Very Low Radiation (EMI)
D
Low-Voltage Differential Signaling With
Typical Output Voltage of 350 mV and a
100 Ω Load
D
Propagation Delay Times Less Than 2.9 ns
D
Output Skew Is Less Than 150 ps
D
Part-to-Part Skew Is Less Than 1.5 ns
D
35 mW Total Power Dissipation in Each
Driver Operating at 200 MHz
D
Driver is High Impedance When Disabled or
With VCC < 1.5 V
D
SN65’ Version Bus-Pin ESD Protection
Exceeds 12 kV
D
Packaged in Thin Shrink Small-Outline
Package With 20-mil Terminal Pitch
D
Low-Voltage TTL (LVTTL) Logic Inputs Are
5-V Tolerant
description
The SN65L VDS389 and SN75L VDS389 are eight
and the SN65LVDS387 and SN75LVDS387 are
sixteen differential line drivers that implement the
electrical characteristics of low-voltage differential
signalling (LVDS). This signaling technique lowers the output voltage levels of 5-V differential
standard levels (such as EIA/TIA-422B) to reduce
the power, increase the switching speeds, and allow operation with a 3.3-V supply rail. Any of the
sixteen current-mode drivers will deliver a minimum differential output voltage magnitude of
247 mV into a 100-Ω load when enabled.
The intended application of this device and signaling technique is for point-to-point and multidrop baseband data
transmission over controlled impedance media of approximately 100 Ω. The transmission media can be
printed-circuit board traces, backplanes, or cables. The large number of drivers integrated into the same
substrate, along with the low pulse skew of balanced signaling, allows extremely precise timing alignment of
clock and data for synchronous parallel data transfers. When used with the companion 16- or 8-channel
receivers, the SN65LVDS386 or SN65LVDS388, over 300 million data transfers per second in single-edge
clocked systems are possible with very little power. (Note: The ultimate rate and distance of data transfer is
dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other
system characteristics.)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TI is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1999, Texas Instruments Incorporated
1
SN65LVDS387, SN75LVDS387, SN65LVDS389, SN75LVDS389
HIGH-SPEED DIFFERENTIAL LINE DRIVERS
SLLS362B – SEPTEMBER 1999 – REVISED NOVEMBER 1999
description (continued)
The drivers are enabled in groups of four and are designated as banks A, B, C, and D. When disabled, the driver
outputs are a high impedance. Each driver input (A) and enable (EN) have an internal pulldown that will drive
the input to a low level when open circuited.
The SN65LVDS387 and SN65LVDS389 are characterized for operation from –40°C to 85°C. The
SN75LVDS387 and SN75LVDS389 are characterized for operation from 0°C to 70°C.
logic diagram (positive logic)
1A
2A
EN
3A
4A
(1/4 of ’LVDS387 or 1/2 of ’LVDS389 shown)
AVAILABLE OPTIONS
PART NUMBER
SN65LVDS387DGG–40°C to 85°C1612 kV
SN75LVDS387DGG0°C to 70°C164 kV
SN65LVDS389DBT–40°C to 85°C812 kV
SN75LVDS389DBT0°C to 70°C84 kV
†
This package is available taped and reeled. To order this packaging option, add
an R suffix to the part number (e.g., SN65LVDS387DGGR).
†
TEMPERATURE
RANGE
DRIVER FUNCTION TABLE
1Y
1Z
2Y
2Z
3Y
3Z
4Y
4Z
NO. OF
DRIVERS
BUS-PIN
ESD
INPUT
AENYZ
HHHL
LHLH
XLZZ
OPENHLH
H = high-level, L = low-level, X = irrelevant,
Z = high-impedance (off)
Lead temperature 1,6 mm (1/16 in) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
‡
This is the inverse of the junction-to-ambient thermal resistance when board-mounted (low-k) and with no air flow.
2. Tested in accordance with MIL-STD-883C Method 3015.7.
DISSIPATION RATING TABLE
PACKAGE
DBT1071 mW8.5 mW/°C688 mW556 mW
DGG2094 mW16.7 mW/°C1342 mW1089 mW
TA ≤ 25°C
DERATING FACTOR
ABOVE TA = 25°C
‡
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
recommended operating conditions
Supply voltage, V
High-level input voltage, V
Low-level input voltage, V
High-impedance output currentVO = 0 V or V
Power-off output currentVCC = 1.5 V,VO = 2.4 V±1µA
Input capacitanceVI = 0.4 sin (4E6πt) + 0.5 V5pF
Output capacitance
=
L
See Figure 1 and 2
See 3
’LVDS387
’LVDS389
’LVDS387
’LVDS389
VOY or VOZ = 0 V±24mA
VOD = 0 V±12mA
VI = 0.4 sin (4E6πt) + 0.5 V,
Disabled
,,
CC
Enabled,
=
L
VIN = 0.8 V or 2 V
Disabled,
VIN = 0 V or V
,
CC
247340454
–5050
–5050mV
8595
5070
0.51.5
0.51.5
±1µA
9.4pF
mV
mA
switching characteristics over recommended operating conditions (unless otherwise noted)
PARAMETERTEST CONDITIONSMIN TYP†MAXUNIT
t
PLH
t
PHL
t
r
t
f
t
sk(p)
t
sk(o)
t
sk(pp)
t
PZH
t
PZL
t
PHZ
t
PLZ
†
All typical values are at 25°C and with a 3.3 V supply.
‡
t
sk(o)
§
t
sk(pp)
with the same supply voltages, at the same temperature, and have identical packages and test circuits.
Propagation delay time, low-to-high-level output0.91.72.9ns
Propagation delay time, high-to-low-level output0.91.62.9ns
Differential output signal rise time
Differential output signal fall time
Pulse skew (|t
Output skew
Part-to-part skew
Propagation delay time, high-impedance-to-high-level output6.415ns
Propagation delay time, high-impedance-to-low-level output
Propagation delay time, high-level-to-high-impedance output
Propagation delay time, low-level-to-high-impedance output4.515ns
is the magnitude of the time difference between the t
is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate
‡
PHL
– t
|)
PLH
§
or t
PLH
of all drivers of a single device with all of their inputs connected together.
PHL
=
CL = 10 pF,
See Figure 4
,
0.40.81ns
0.40.81ns
150500ps
80150ps
1.5ns
5.915ns
3.515ns
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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