Four (’391), Eight (’389) or Sixteen (’387)
Line Drivers Meet or Exceed the
Requirements of ANSI EIA/TIA-644
Standard
D
Designed for Signaling Rates† up to
630 Mbps With Very Low Radiation (EMI)
D
Low-Voltage Differential Signaling With
Typical Output Voltage of 350 mV and a
100-Ω Load
D
Propagation Delay Times Less Than 2.9 ns
D
Output Skew Is Less Than 150 ps
D
Part-to-Part Skew Is Less Than 1.5 ns
D
35-mW Total Power Dissipation in Each
Driver Operating at 200 MHz
D
Driver Is High Impedance When Disabled or
With V
D
SN65’ Version Bus-Pin ESD Protection
< 1.5 V
CC
Exceeds 15 kV
D
Packaged in Thin Shrink Small-Outline
Package With 20-mil Terminal Pitch
D
Low-Voltage TTL (LVTTL) Logic Inputs Are
5-V Tolerant
description
This family of four, eight, and sixteen differential
line drivers implements the electrical characteristics of low-voltage differential signaling (LVDS).
This signaling technique lowers the output voltage
levels of 5-V differential standard levels (such as
EIA/TIA-422B) to reduce the power , increase the
switching speeds, and allow operation with a
3.3-V supply rail. Any of the sixteen current-mode
drivers will deliver a minimum differential output
voltage magnitude of 247 mV into a 100-Ω load
when enabled.
The intended application of this device and signaling technique is for point-to-point and multidrop baseband data
transmission over controlled impedance media of approximately 100 Ω. The transmission media can be
printed-circuit board traces, backplanes, or cables. The large number of drivers integrated into the same
substrate, along with the low pulse skew of balanced signaling, allows extremely precise timing alignment of
clock and data for synchronous parallel data transfers. When used with the companion 16- or 8-channel
receivers, the SN65LVDS386 or SN65LVDS388, over 300 million data transfers per second in single-edge
clocked systems are possible with very little power. (Note: The ultimate rate and distance of data transfer is
dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other
system characteristics.)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
†
Signaling rate, 1/t, where t is the minimum unit interval and is expressed in the units bits/s (bits per second)
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 2001, Texas Instruments Incorporated
1
SN65LVDS387, SN75LVDS387, SN65LVDS389
SN75LVDS389, SN65LVDS391, SN75LVDS391
HIGH-SPEED DIFFERENTIAL LINE DRIVERS
SLLS362D – SEPTEMBER 1999 – REVISED MAY 2001
description (continued)
When disabled, the driver outputs are high impedance. Each driver input (A) and enable (EN) have an internal
pulldown that will drive the input to a low level when open circuited.
The SN65L VDS387, SN65LVDS389, and SN65LVDS391 are characterized for operation from –40°C to 85°C.
The SN75LVDS387, SN75LVDS389, and SN75LVDS391 are characterized for operation from 0°C to 70°C.
logic diagram (positive logic)
1A
2A
EN
3A
4A
(1/4 of ’LVDS387 or 1/2 of ’LVDS389 shown)
PART NUMBER
SN65LVDS387DGG–40°C to 85°C1615 kV
SN75LVDS387DGG0°C to 70°C164 kV
SN65LVDS389DBT–40°C to 85°C815 kV
SN75LVDS389DBT0°C to 70°C84 kV
SN65LVDS391D–40°C to 85°C415 kV
SN75LVDS391D0°C to 70°C44 kV
SN65LVDS391PW–40°C to 85°C415 kV
SN75LVDS391PW0°C to 70°C44 kV
†
This package is available taped and reeled. To order this packaging option, add
an R suffix to the part number (e.g., SN65LVDS387DGGR).
1Y
1Z
2Y
2Z
3Y
3Z
4Y
4Z
†
EN
EN
AVAILABLE OPTIONS
TEMPERATURE
RANGE
1A
2A
3A
4A
(’LVDS391 shown)
NO. OF
DRIVERS
BUS-PIN
1Y
1Z
2Y
2Z
3Y
3Z
4Y
4Z
ESD
DRIVER FUNCTION TABLE
INPUT
AENYZ
HHHL
LHLH
XLZZ
OPENHLH
H = high-level, L = low-level, X = irrelevant,
Z = high-impedance (off)
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ENABLEOUTPUTS
O erating free-air tem erature, T
A
equivalent input and output schematic diagrams
EQUIVALENT OF EACH A OR EN INPUTTYPICAL OF ALL OUTPUTS
Lead temperature 1,6 mm (1/16 in) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
‡
This is the inverse of the junction-to-ambient thermal resistance when board-mounted (low-k) and with no air flow.
2. Tested in accordance with MIL-STD-883C Method 3015.7.
DISSIPATION RATING TABLE
PACKAGE
D950 mW7.6 mW/°C608 mW494 mW
DBT1071 mW8.5 mW/°C688 mW556 mW
DGG2094 mW16.7 mW/°C1342 mW1089 mW
PW774 mW6.2 mW/°C496 mW402 mW
TA ≤ 25°C
DERATING FACTOR
ABOVE TA = 25°C
‡
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
recommended operating conditions
Supply voltage, V
High-level input voltage, V
Low-level input voltage, V
p
MINNOM MAXUNIT
CC
IH
IL
p
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN75’070°C
SN65’–4085°C
33.33.6V
2V
0.8V
3
SN65LVDS387, SN75LVDS387, SN65LVDS389
R
100 Ω
Enabled
ICCSupply current
mA
V
IN
V
CC
IOSShort-circuit output current
R
L
100 Ω
L
See Figure 5
SN75LVDS389, SN65LVDS391, SN75LVDS391
HIGH-SPEED DIFFERENTIAL LINE DRIVERS
SLLS362D – SEPTEMBER 1999 – REVISED MAY 2001
electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETERTEST CONDITIONSMIN TYP†MAXUNIT
|VOD|Differential output voltage magnitude
∆|VOD|
V
OC(SS)
∆V
OC(SS)
V
OC(PP)
I
IH
I
IL
I
OZ
I
O(OFF)
C
IN
C
O
†
All typical values are at 25°C and with a 3.3-V supply.
Change in differential output voltage
magnitude between logic states
Steady-state common-mode output voltage1.1251.375V
Change in steady-state common-mode output
voltage between logic states
Peak-to-peak common-mode output voltage50150mV
switching characteristics over recommended operating conditions (unless otherwise noted)
PARAMETERTEST CONDITIONSMIN TYP†MAXUNIT
t
PLH
t
PHL
t
r
t
f
t
sk(p)
t
sk(o)
t
sk(pp)
t
PZH
t
PZL
t
PHZ
t
PLZ
†
All typical values are at 25°C and with a 3.3-V supply.
‡
t
sk(o)
§
t
sk(pp)
sheet when both devices operate with the same supply voltage, at the same temperature, and have the same test circuits.
Propagation delay time, low-to-high-level output0.91.72.9ns
Propagation delay time, high-to-low-level output0.91.62.9ns
Differential output signal rise time
Differential output signal fall time
Pulse skew (|t
Output skew
Part-to-part skew
Propagation delay time, high-impedance-to-high-level output6.415ns
Propagation delay time, high-impedance-to-low-level output
Propagation delay time, high-level-to-high-impedance output
Propagation delay time, low-level-to-high-impedance output4.515ns
is the magnitude of the time difference between the t
is the magnitude of the difference in propagation delay times between any specified terminals of any two devices characterized in this data
‡
PHL
– t
|)
PLH
§
or t
PLH
of all drivers of a single device with all of their inputs connected together.
NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps,
pulse width = 500 ± 10 ns. CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T . The measurement of V
is made on test equipment with a –3 dB bandwidth of at least 300 MHz.
V
OC
I
V
OC(PP)
V
O
3 V
0 V
V
OC(SS)
OC(PP)
Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output V oltage
Input
t
Y
PLH
t
PHL
2 V
1.4 V
0.8 V
Input
Z
NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps, pulse
width = 10 ± 0.2 ns. CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T.
V
OD
CL = 10 pF
(2 Places)
100 Ω± 1 %
Output
0 V
V
OD(H)
V
OD(L)
t
f
t
r
100%
80%
20%
0%
Figure 4. Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
SN65LVDS387, SN75LVDS387, SN65LVDS389
SN75LVDS389, SN65LVDS391, SN75LVDS391
HIGH-SPEED DIFFERENTIAL LINE DRIVERS
SLLS362D – SEPTEMBER 1999 – REVISED MAY 2001
PARAMETER MEASUREMENT INFORMATION
Y
0.8 V or 2 V
Input
Input
t
PZH
V
OY
or
V
OZ
t
PZL
V
OZ
or
V
OY
NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps,
pulse width = 500 ± 10 ns. CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T.
Z
CL = 10 pF
(2 Places)
49.9 Ω± 1% (2 Places)
V
OYVOZ
2 V
1.4 V
0.8 V
t
PHZ
≅ 1.4 V
1.3 V
1.2 V
t
PLZ
1.2 V
1.1 V
≅ 1 V
+
1.2 V
–
Figure 5. Enable and Disable Time Circuit and Definitions
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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