TEXAS INSTRUMENTS SN65LVDS387, SN75LVDS387, SN65LVDS389, SN75LVDS389, SN65LVDS391 Technical data

查询SN65LVDS387供应商

SN65LVDS387, SN75LVDS387, SN65LVDS389
SN75LVDS389, SN65LVDS391, SN75LVDS391

HIGH-SPEED DIFFERENTIAL LINE DRIVERS

SLLS362D – SEPTEMBER 1999 – REVISED MA Y 2001

D

Four (’391), Eight (’389) or Sixteen (’387)
Line Drivers Meet or Exceed the
Requirements of ANSI EIA/TIA-644
Standard

D

Designed for Signaling Rates† up to
630 Mbps With Very Low Radiation (EMI)

D

Low-Voltage Differential Signaling With
Typical Output Voltage of 350 mV and a
100-Ω Load

D

Propagation Delay Times Less Than 2.9 ns

D

Output Skew Is Less Than 150 ps

D

Part-to-Part Skew Is Less Than 1.5 ns

D

35-mW Total Power Dissipation in Each
Driver Operating at 200 MHz

D

Driver Is High Impedance When Disabled or
With V

D

SN65’ Version Bus-Pin ESD Protection

< 1.5 V

CC

Exceeds 15 kV

D

Packaged in Thin Shrink Small-Outline
Package With 20-mil Terminal Pitch

D

Low-Voltage TTL (LVTTL) Logic Inputs Are
5-V Tolerant

description

This family of four, eight, and sixteen differential
line drivers implements the electrical characteris­tics of low-voltage differential signaling (LVDS).
This signaling technique lowers the output voltage
levels of 5-V differential standard levels (such as
EIA/TIA-422B) to reduce the power , increase the
switching speeds, and allow operation with a

3.3-V supply rail. Any of the sixteen current-mode
drivers will deliver a minimum differential output
voltage magnitude of 247 mV into a 100-Ω load
when enabled.

’LVDS389

DBT PACKAGE

(TOP VIEW)

GND

GND

GND

GND

GND

GND

EN1,2

EN3,4

1

V

2

CC

3

ENA

4

A1A

5

A2A

6

A3A

7

A4A

8
9

V

10

CC

11

B1A

12

B2A

13

B3A

14

B4A

15

ENB

16
17
18

V

CC

19

’LVDS391

D OR PW PACKAGE

(TOP VIEW)

1

1A

2

2A

3

V

4

CC

GND

3A
4A

5
6
7
8

38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20

16
15
14
13
12
11
10

’LVDS387

DGG PACKAGE

(TOP VIEW)

A1Y

GND

A1Z
A2Y
A2Z

GND

A3Y
A3Z
A4Y
A4Z
NC
NC
NC
B1Y
B1Z
B2Y
B2Z

GND

B3Y
B3Z
B4Y

GND

B4Z

1Y
1Z
2Y
2Z
3Y

GND
3Z
4Y

9

4Z

GND

V

CC

V

CC

ENA

A1A
A2A
A3A
A4A

ENB

B1A
B2A
B3A
B4A

V

CC

V

CC

C1A
C2A
C3A
C4A

ENC

D1A
D2A
D3A
D4A

END

V

CC

V

CC

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

A1Y
A1Z
A2Y
A2Z
A3Y
A3Z
A4Y
A4Z
B1Y
B1Z
B2Y
B2Z
B3Y
B3Z
B4Y
B4Z
C1Y
C1Z
C2Y
C2Z
C3Y
C3Z
C4Y
C4Z
D1Y
D1Z
D2Y
D2Z
D3Y
D3Z
D4Y
D4Z

The intended application of this device and signaling technique is for point-to-point and multidrop baseband data
transmission over controlled impedance media of approximately 100 Ω. The transmission media can be
printed-circuit board traces, backplanes, or cables. The large number of drivers integrated into the same
substrate, along with the low pulse skew of balanced signaling, allows extremely precise timing alignment of
clock and data for synchronous parallel data transfers. When used with the companion 16- or 8-channel
receivers, the SN65LVDS386 or SN65LVDS388, over 300 million data transfers per second in single-edge
clocked systems are possible with very little power. (Note: The ultimate rate and distance of data transfer is
dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other
system characteristics.)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

†

Signaling rate, 1/t, where t is the minimum unit interval and is expressed in the units bits/s (bits per second)

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  2001, Texas Instruments Incorporated

1

SN65LVDS387, SN75LVDS387, SN65LVDS389
SN75LVDS389, SN65LVDS391, SN75LVDS391
HIGH-SPEED DIFFERENTIAL LINE DRIVERS

SLLS362D – SEPTEMBER 1999 – REVISED MAY 2001

description (continued)

When disabled, the driver outputs are high impedance. Each driver input (A) and enable (EN) have an internal
pulldown that will drive the input to a low level when open circuited.

The SN65L VDS387, SN65LVDS389, and SN65LVDS391 are characterized for operation from –40°C to 85°C.
The SN75LVDS387, SN75LVDS389, and SN75LVDS391 are characterized for operation from 0°C to 70°C.

logic diagram (positive logic)

1A

2A

EN

3A

4A

(1/4 of ’LVDS387 or 1/2 of ’LVDS389 shown)

PART NUMBER

SN65LVDS387DGG –40°C to 85°C 16 15 kV
SN75LVDS387DGG 0°C to 70°C 16 4 kV
SN65LVDS389DBT –40°C to 85°C 8 15 kV
SN75LVDS389DBT 0°C to 70°C 8 4 kV
SN65LVDS391D –40°C to 85°C 4 15 kV
SN75LVDS391D 0°C to 70°C 4 4 kV
SN65LVDS391PW –40°C to 85°C 4 15 kV
SN75LVDS391PW 0°C to 70°C 4 4 kV

†

This package is available taped and reeled. To order this packaging option, add
an R suffix to the part number (e.g., SN65LVDS387DGGR).

1Y
1Z

2Y
2Z

3Y
3Z

4Y
4Z

†

EN

EN

AVAILABLE OPTIONS

TEMPERATURE

RANGE

1A

2A

3A

4A

(’LVDS391 shown)

NO. OF

DRIVERS

BUS-PIN

1Y
1Z

2Y
2Z

3Y
3Z

4Y
4Z

ESD

DRIVER FUNCTION TABLE

INPUT

A EN Y Z

H H H L

L H L H

X L Z Z

OPEN H L H

H = high-level, L = low-level, X = irrelevant,
Z = high-impedance (off)

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ENABLE OUTPUTS

O erating free-air tem erature, T

A

equivalent input and output schematic diagrams

EQUIVALENT OF EACH A OR EN INPUT TYPICAL OF ALL OUTPUTS

V

CC

SN65LVDS387, SN75LVDS387, SN65LVDS389
SN75LVDS389, SN65LVDS391, SN75LVDS391

HIGH-SPEED DIFFERENTIAL LINE DRIVERS

SLLS362D – SEPTEMBER 1999 – REVISED MAY 2001

V

CC

7 V

50 Ω

10 kΩ

300 kΩ

–0.5 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

5 Ω

Y or Z
Output

7 V

†

A or EN

Input

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

Supply voltage range, V

Input voltage range: Inputs –0.5 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Y or Z –0.5 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Electrostatic discharge: SN65’ (Y, Z, and GND) Class 3, A:15 kV, B: 500 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SN75’ (Y, Z, and GND) Class 3, A:4 kV, B: 400 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous power dissipation (see Dissipation Rating Table). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 in) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.

‡

This is the inverse of the junction-to-ambient thermal resistance when board-mounted (low-k) and with no air flow.

2. Tested in accordance with MIL-STD-883C Method 3015.7.

DISSIPATION RATING TABLE

PACKAGE

D 950 mW 7.6 mW/°C 608 mW 494 mW

DBT 1071 mW 8.5 mW/°C 688 mW 556 mW

DGG 2094 mW 16.7 mW/°C 1342 mW 1089 mW

PW 774 mW 6.2 mW/°C 496 mW 402 mW

TA ≤ 25°C

DERATING FACTOR

ABOVE TA = 25°C

‡

TA = 70°C

POWER RATING

TA = 85°C

POWER RATING

recommended operating conditions

Supply voltage, V
High-level input voltage, V
Low-level input voltage, V

p

MIN NOM MAX UNIT

CC

IH

IL

p

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN75’ 0 70 °C
SN65’ –40 85 °C

3 3.3 3.6 V
2 V

0.8 V

3

SN65LVDS387, SN75LVDS387, SN65LVDS389

R

100 Ω

Enabled

ICCSupply current

mA

V

IN

V

CC

IOSShort-circuit output current

R

L

100 Ω

L

See Figure 5

SN75LVDS389, SN65LVDS391, SN75LVDS391
HIGH-SPEED DIFFERENTIAL LINE DRIVERS

SLLS362D – SEPTEMBER 1999 – REVISED MAY 2001

electrical characteristics over recommended operating conditions (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

|VOD| Differential output voltage magnitude
∆|VOD|
V

OC(SS)

∆V

OC(SS)

V

OC(PP)

I

IH

I

IL

I

OZ

I

O(OFF)

C

IN

C

O

†

All typical values are at 25°C and with a 3.3-V supply.

Change in differential output voltage
magnitude between logic states

Steady-state common-mode output voltage 1.125 1.375 V
Change in steady-state common-mode output

voltage between logic states
Peak-to-peak common-mode output voltage 50 150 mV

pp

High-level input current VIH = 2 V 3 20 µA
Low-level input current VIL = 0.8 V 2 10 µA

p

High-impedance output current VO = 0 V or V
Power-off output current VCC = 1.5 V, VO = 2.4 V ±1 µA
Input capacitance VI = 0.4 sin (4E6πt) + 0.5 V 5 pF

Output capacitance

=

L

See Figure 1 and Figure 2

See Figure 3

’LVDS387
’LVDS389
’LVDS391
’LVDS387
’LVDS389
’LVDS391

VOY or VOZ = 0 V ±24 mA
VOD = 0 V ±12 mA

VI = 0.4 sin (4E6πt) + 0.5 V,
Disabled

,,

,
RL = 100 Ω,
VIN = 0.8 V or 2 V

Disabled,

= 0 V or

CC

247 340 454

–50 50

–50 50 mV

85 95
50 70
20 26

0.5 1.5

0.5 1.5

0.5 1.3

±1 µA

9.4 pF

mV

switching characteristics over recommended operating conditions (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

t

PLH

t

PHL

t

r

t

f

t

sk(p)

t

sk(o)

t

sk(pp)

t

PZH

t

PZL

t

PHZ

t

PLZ

†

All typical values are at 25°C and with a 3.3-V supply.

‡

t

sk(o)

§

t

sk(pp)

sheet when both devices operate with the same supply voltage, at the same temperature, and have the same test circuits.

Propagation delay time, low-to-high-level output 0.9 1.7 2.9 ns
Propagation delay time, high-to-low-level output 0.9 1.6 2.9 ns
Differential output signal rise time
Differential output signal fall time
Pulse skew (|t

Output skew
Part-to-part skew

Propagation delay time, high-impedance-to-high-level output 6.4 15 ns
Propagation delay time, high-impedance-to-low-level output
Propagation delay time, high-level-to-high-impedance output
Propagation delay time, low-level-to-high-impedance output 4.5 15 ns

is the magnitude of the time difference between the t

is the magnitude of the difference in propagation delay times between any specified terminals of any two devices characterized in this data

‡

PHL

– t

|)

PLH

§

or t

PLH

of all drivers of a single device with all of their inputs connected together.

PHL

=
CL = 10 pF,
See Figure 4

,

0.4 0.8 1 ns

0.4 0.8 1 ns
150 500 ps

80 150 ps

1.5 ns

5.9 15 ns

3.5 15 ns

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN65LVDS387, SN75LVDS387, SN65LVDS389
SN75LVDS389, SN65LVDS391, SN75LVDS391

HIGH-SPEED DIFFERENTIAL LINE DRIVERS

SLLS362D – SEPTEMBER 1999 – REVISED MAY 2001

PARAMETER MEASUREMENT INFORMATION

I

OY

GND

Y

V

I

OZ

Z

OD

V

OY

V

V

OZ

OC

(VOY + VOZ)/2

I

I

A

V

I

Figure 1. Voltage and Current Definitions

Input

Y

V

OD

Z

100 Ω

3.75 kΩ

3.75 kΩ

±

0 V ≤ V

TEST

≤ 2.4 V

Figure 2. VOD Test Circuit

49.9 Ω ± 1% (2 Places)

Y

V

Input

Z

50 pF

NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps,

pulse width = 500 ± 10 ns. CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T . The measurement of V
is made on test equipment with a –3 dB bandwidth of at least 300 MHz.

V

OC

I

V

OC(PP)

V

O

3 V

0 V

V

OC(SS)

OC(PP)

Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output V oltage

Input

t

Y

PLH

t

PHL

2 V

1.4 V

0.8 V

Input

Z

NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps, pulse

width = 10 ± 0.2 ns. CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T.

V

OD

CL = 10 pF
(2 Places)

100 Ω ± 1 %

Output

0 V

V

OD(H)

V

OD(L)

t

f

t

r

100%
80%

20%
0%

Figure 4. Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5

SN65LVDS387, SN75LVDS387, SN65LVDS389
SN75LVDS389, SN65LVDS391, SN75LVDS391
HIGH-SPEED DIFFERENTIAL LINE DRIVERS

SLLS362D – SEPTEMBER 1999 – REVISED MAY 2001

PARAMETER MEASUREMENT INFORMATION

Y

0.8 V or 2 V

Input

Input

t

PZH

V

OY

or

V

OZ

t

PZL

V

OZ

or

V

OY

NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 0.5 Mpps,

pulse width = 500 ± 10 ns. CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T.

Z

CL = 10 pF

(2 Places)

49.9 Ω ± 1% (2 Places)

V

OYVOZ

2 V

1.4 V

0.8 V

t

PHZ

≅ 1.4 V

1.3 V

1.2 V

t

PLZ

1.2 V

1.1 V
≅ 1 V

+

1.2 V

–

Figure 5. Enable and Disable Time Circuit and Definitions

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265