TEXAS INSTRUMENTS SN65LVDS32B, SN65LVDT32B, SN65LVDS3486B, SN65LVDT3486B, SN65LVDS9637B Technical data

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1
2
3
4
5
6
7
8

16
15
14
13
12
11
10

9

1B
1A
1Y

G
2Y
2A
2B

GND

V

CC

4B
4A
4Y
G
3Y
3A
3B

SN65LVDT32B

1
2
3
4

8
7
6
5

V

CC

1Y
2Y

GND

1A
1B
2A
2B

D PACKAGE

(TOP VIEW)

D PACKAGE

(TOP VIEW)

SN65LVDS32B

G
G

1A
1B

2A
2B

3A
3B
4A
4B

1Y

2Y

3Y

4Y

Logic Diagram

(positive logic)

SN65LVDT32B
ONLY (4 Places)

1
2
3
4
5
6
7
8

16
15
14
13
12
11
10

9

1B
1A
1Y

1,2EN

2Y
2A
2B

GND

V

CC

4B
4A
4Y
3,4EN
3Y
3A
3B

SN65LVDT3486B

D PACKAGE

(TOP VIEW)

SN65LVDS3486B

1A
1B

2A
2B

3A
3B
4A
4B

1Y

2Y

3Y

4Y

Logic Diagram

(positive logic)

SN65LVDT3486B
ONLY (4 Places)

1,2EN

3,4EN

1A
1B

2A
2B

1Y

2Y

SN65LVDT9637B
ONLY

SN65LVDT9637B

SN65LVDS9637B

Logic Diagram

(positive logic)

HIGH-SPEED DIFFERENTIAL RECEIVERS

FEATURES

• Meets or Exceeds the Requirements of ANSI

EIA/TIA-644 Standard for Signaling Rates
to 400 Mbps

• Operates With a Single 3.3-V Supply

• –2-V to 4.4-V Common-Mode Input Voltage

Range

• Differential Input Thresholds <50 mV With

50 mV of Hysteresis Over Entire Common­Mode Input Voltage Range

• Integrated 110- Ω Line Termination Resistors

Offered With the LVDT Series

• Propagation Delay Times 4 ns (typ)

• Active Fail Safe Assures a High-Level Output

With No Input

• Bus-Pin ESD Protection Exceeds 15 kV HBM

• Inputs Remain High-Impedance on Power

Down

• Recommended Maximum Parallel Rate of

200 M-Transfer/s

• Available in Small-Outline Package With

1,27-mm Terminal Pitch

• Pin-Compatible With the AM26LS32, MC3486,

or µA9637

DESCRIPTION

This family of differential line receivers offers
improved performance and features that implement
the electrical characteristics of low-voltage differential
signaling (LVDS). LVDS is defined in the
TIA/EIA-644 standard. This improved performance
represents the second generation of receiver
products for this standard, providing a better overall
solution for the cabled environment. This generation
of products is an extension to TI's overall product
portfolio and is not necessarily a replacement for
older LVDS receivers.

SN65LVDS32B , , SN65LVDT32B
SN65LVDS3486B , SN65LVDT3486B
SN65LVDS9637B , SN65LVDT9637B

SLLS440B – OCTOBER 2000 – REVISED APRIL 2007

(1)

up

(1) Signaling rate, 1/t, where t is the minimum unit interval and is

expressed in the units bit/s (bits per second).

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Copyright © 2000–2007, Texas Instruments Incorporated

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SN65LVDS32B , , SN65LVDT32B
SN65LVDS3486B , SN65LVDT3486B
SN65LVDS9637B , SN65LVDT9637B

SLLS440B – OCTOBER 2000 – REVISED APRIL 2007

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

DESCRIPTION (CONTINUED)

Improved features include an input common-mode voltage range 2 V wider than the minimum required by the
standard. This will allow longer cable lengths by tripling the allowable ground noise tolerance to 3 V between a
driver and receiver. TI has additionally introduced an even wider input common-mode voltage range of –4 to 5 V
in their SN65LVDS/T33 and SN65LVDS/T34.

Precise control of the differential input voltage thresholds now allows for inclusion of 50 mV of input voltage
hysteresis to improve noise rejection on slowly changing input signals. The input thresholds are still no more
than ±50 mV over the full input common-mode voltage range.

The high-speed switching of LVDS signals almost always necessitates the use of a line impedance matching
resistor at the receiving-end of the cable or transmission media. The SN65LVDT series of receivers eliminates
this external resistor by integrating it with the receiver. The non-terminated SN65LVDS series is also available
for multidrop or other termination circuits.

The receivers can withstand ±15-kV human-body model (HBM) and ±600 V-machine model (MM) electrostatic
discharges to the receiver input pins with respect to ground without damage. This provides reliability in cabled
and other connections where potentially damaging noise is always a threat.

The receivers also include a (patent pending) fail-safe circuit that will provide a high-level output within 600 ns
after loss of the input signal. The most common causes of signal loss are disconnected cables, shorted lines, or
powered-down transmitters. This prevents noise from being received as valid data under these fault conditions.
This feature may also be used for wired-OR bus signaling.

The intended application of these devices and signaling technique is for point-to-point baseband data
transmission over controlled impedance media of approximately 100 Ω . The transmission media may be
printed-circuit board traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent
upon the attenuation characteristics of the media and the noise coupling to the environment.

The SN65LVDS32B, SN65LVDT32B, SN65LVDS3486B, SN65LVDT3486B, SN65LVDS9637B, and
SN65LVDT9637B are characterized for operation from –40°C to 85°C.

AVAILABLE OPTIONS

PART NUMBER

SN65LVDS32BD 4 No LVDS32B

SN65LVDT32BD 4 Yes LVDT32B
SN65LVDS3486BD 4 No LVDS3486
SN65LVDT3486BD 4 Yes LVDT3486
SN65LVDS9637BD 2 No DK637B
SN65LVDT9637BD 2 Yes DR637B

(1) Add the suffix R for taped and reeled carrier.

(1)

NUMBER OF TERMINATION

RECEIVERS RESISTOR

SYMBOLIZATION

2

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FUNCTION TABLES

SN65LVDS32B and SN65LVDT32B

DIFFERENTIAL INPUT ENABLES

A-B G G Y

VID≥ –32 mV

–100 mV < VID≤ –32 mV

VID≤ –100 mV

X L H Z

Open

(1) H = high level, L = low level, X = irrelevant, Z = high impedance (off), ? = indeterminate

SN65LVDS3486B and SN65LVDT3486B

DIFFERENTIAL INPUT ENABLES

A-B EN Y

VID≥ –32 mV H H

–100 mV < VID≤ –32 mV H ?

VID≤ –100 mV H L

X L Z

Open H H

SN65LVDS32B , , SN65LVDT32B
SN65LVDS3486B , SN65LVDT3486B
SN65LVDS9637B , SN65LVDT9637B

SLLS440B – OCTOBER 2000 – REVISED APRIL 2007

(1)

H X H
X L H

H X ?
X L ?

H X L
X L L

H X H
X L H

(1)

OUTPUT

OUTPUT

(1)

(1)

(1) H = high level, L = low level, X = irrelevant, Z = high impedance (off), ? = indeterminate

SN65LVDS9637B and SN65LVDT9637B

DIFFERENTIAL INPUT OUTPUT

A-B Y

VID≥ -32 mV H

–100 mV < VID≤ -32 mV ?

VID≤ -100 mV L

Open H

(1) H = high level, L = low level, ? = indeterminate

(1)

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V

CC

37 Ω

7 V

Y Output

LVDT Only 110 Ω

7 V

300 kΩ

50 Ω

V

CC

Enable

Inputs

300 kΩ

(G Only)

(EN and G Only)

7 V

V

CC

Attenuation

Network

A Input

Attenuation

Network

B Input

7 V

V

CC

Attenuation

Network

60 kΩ

250 kΩ

200 kΩ

1 pF

3 pF

7 V

7 V

6.5 kΩ 6.5 kΩ

SN65LVDS32B , , SN65LVDT32B
SN65LVDS3486B , SN65LVDT3486B
SN65LVDS9637B , SN65LVDT9637B

SLLS440B – OCTOBER 2000 – REVISED APRIL 2007

EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS

4

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SN65LVDS32B , , SN65LVDT32B
SN65LVDS3486B , SN65LVDT3486B
SN65LVDS9637B , SN65LVDT9637B

SLLS440B – OCTOBER 2000 – REVISED APRIL 2007

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

V

Supply voltage range

CC

Voltage range A or B –4 V to 6 V

Electrostatic discharge: A, B, and GND
Continuous power dissipation See Dissipation Rating Table
Storage temperature range –65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
(3) Tested in accordance with MIL-STD-883C Method 3015.7.

(2)

Enables or Y –0.5 V to V

|VA– VB| (LVDT) 1 V

(3)

DISSIPATION RATING TABLE

PACKAGE

D8 725 mW 5.8 mW/°C 377 mW

D16 950 mW 7.6 mW/°C 494 mW

TA≤ 25°C OPERATING FACTOR

POWER RATING ABOVE TA= 25°C POWER RATING

(1)

UNIT

–0.5 V to 4 V

CC

Class 3, A: 15 kV, B: 600 V

(1)

TA= 85°C

+ 3 V

(1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air

flow.

RECOMMENDED OPERATING CONDITIONS

V

CC

V

IH

V

IL

| VID| Magnitude of differential input voltage

VIor V
T

A

Supply voltage 3 3.3 3.6 V
High-level input voltage Enables 2 V
Low-level input voltage Enables 0.8 V

Voltage at any bus terminal (separately or common-mode) –2 4.4 V

IC

Operating free-air temperature –40 85 °C

MIN NOM MAX UNIT

LVDS 0.1 3 V
LVDT 0.8 V

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SN65LVDS32B , , SN65LVDT32B
SN65LVDS3486B , SN65LVDT3486B
SN65LVDS9637B , SN65LVDT9637B

SLLS440B – OCTOBER 2000 – REVISED APRIL 2007

ELECTRICAL CHARACTERISTICS

over recommended operating conditions (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP

V
V
V
V
V
V

I

CC

I

I

I

ID

I

I(OFF)

I

IH

I

IL

I

OZ

C

(1) All typical values are at 25°C and with a 3.3 V supply.

Positive-going differential input voltage threshold 50

IT1

Negative-going differential input voltage threshold –50

IT2

Differential input fail-safe voltage threshold See Table 1 and Figure 5 –32 –100 mV

IT3

Differential input voltage hysteresis, V

ID(HYS)

High-level output voltage IOH= –4 mA 2.4 V

OH

Low-level output voltage IOL= 4 mA 0.4 V

OL

Supply current G or EN at GND 1.1 5 mA

– V

IT1

IT2

'32B or '3486B

'9637B No load, Steady-state 8 12

SN65LVDS µA

Input current (A or B inputs)

SN65LVDT µA

Differential input current
(IIA- IIB)

SN65LVDS ±3 µA
SN65LVDT VID= 0.2 V, VIC= –2 V or 4.4 V 1.55 2.22 mA

SN65LVDS
Power-off input current
(A or B inputs)

SN65LVDT

High-level input current (enables) VIH= 2 V 10 µA
Low-level input current (enables) VIL= 0.8 V 10 µA
High-impedance output current ±10 µA
Input capacitance, A or B input to GND VI= 0.4 sin (4E6 π t) + 0.5 V 5 pF

I

(1)

VIB= -2 V or 4.4 V,
See Figure 1 and Figure 2

50 mV

G or EN at VCC, No load, Steady-state 16 23

VI= 0 V, Other input open ±20
VI= 2.4 V, Other input open ±20
VI= –2 V, Other input open ±40
VI= 4.4 V, Other input open ±40
VI= 0 V, Other input open ±40
VI= 2.4 V, Other input open ±40
VI= –2 V, Other input open ±80
VI= 4.4 V, Other input open ±80
VID= 100 mV, VIC= –2 V or 4.4 V,

See Figure 1

VAor VB= 0 V or 2.4 V, V
VAor VB= –2 V or 4.4 V, V
VAor VB= 0 V or 2.4 V, V
VAor VB= –2 V or 4.4 V, V

= 0 V ±20

CC

= 0 V ±35

CC

= 0 V ±30

CC

= 0 V ±50

CC

MAX UNIT

mV

µA

6

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SN65LVDS32B , , SN65LVDT32B
SN65LVDS3486B , SN65LVDT3486B
SN65LVDS9637B , SN65LVDT9637B

SLLS440B – OCTOBER 2000 – REVISED APRIL 2007

SWITCHING CHARACTERISTICS

over operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP

t

Propagation delay time, low-to-high-level output 2.5 4 6 ns

PLH

t

Propagation delay time, high-to-low-level output 2.5 4 6 ns

PHL

t

Delay time, fail-safe deactivate time 9 ns

d1

t

Delay time, fail-safe activate time 0.3 1.5 µs

d2

t

Pulse skew (|t

sk(p)

t

Output skew

sk(o)

t

Part-to-part skew

sk(pp)

t

Output signal rise time 0.8 ns

r

t

Output signal fall time 0.8 ns

f

t

Propagation delay time, high-level-to-high-impedance output 5.5 9 ns

PHZ

t

Propagation delay time, low-level-to-high-impedance output 4.4 9 ns

PLZ

t

Propagation delay time, high-impedance -to-high-level output 3.8 9 ns

PZH

t

Propagation delay time, high-impedance-to-low-level output 7 9 ns

PZL

- t

PHL1

(2)

|) 200 ps

PLH1

(3)

(1) All typical values are at 25°C and with a 3.3-V supply.
(2) t

(3) t

is the magnitude of the time difference between the t

sk(o)

together.

is the magnitude of the time difference in propagation delay times between any specified terminals of two devices when both

sk(pp)

devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.

or t

PLH

See Figure 3

See Figure 3 and

Figure 6

CL= 10 pF, See Figure 3 1 ns

See Figure 4

of all receivers of a single device with all of their inputs driven

PHL

(1)

MAX UNIT

150 ps

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